Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 12:56:22 -06:00
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using ARMeilleure.State;
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using System;
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using System.Diagnostics;
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namespace ARMeilleure.Instructions
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{
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static class SoftFloat
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{
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static SoftFloat()
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{
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RecipEstimateTable = BuildRecipEstimateTable();
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RecipSqrtEstimateTable = BuildRecipSqrtEstimateTable();
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}
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internal static readonly byte[] RecipEstimateTable;
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internal static readonly byte[] RecipSqrtEstimateTable;
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private static byte[] BuildRecipEstimateTable()
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{
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byte[] tbl = new byte[256];
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for (int idx = 0; idx < 256; idx++)
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{
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uint src = (uint)idx + 256u;
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Debug.Assert(256u <= src && src < 512u);
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src = (src << 1) + 1u;
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uint aux = (1u << 19) / src;
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uint dst = (aux + 1u) >> 1;
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Debug.Assert(256u <= dst && dst < 512u);
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tbl[idx] = (byte)(dst - 256u);
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}
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return tbl;
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}
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private static byte[] BuildRecipSqrtEstimateTable()
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{
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byte[] tbl = new byte[384];
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for (int idx = 0; idx < 384; idx++)
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{
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uint src = (uint)idx + 128u;
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Debug.Assert(128u <= src && src < 512u);
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if (src < 256u)
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{
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src = (src << 1) + 1u;
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}
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else
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{
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src = (src >> 1) << 1;
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src = (src + 1u) << 1;
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}
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uint aux = 512u;
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while (src * (aux + 1u) * (aux + 1u) < (1u << 28))
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{
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aux = aux + 1u;
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}
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uint dst = (aux + 1u) >> 1;
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Debug.Assert(256u <= dst && dst < 512u);
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tbl[idx] = (byte)(dst - 256u);
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}
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return tbl;
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}
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}
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static class SoftFloat16_32
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{
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public static float FPConvert(ushort valueBits)
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{
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ExecutionContext context = NativeInterface.GetContext();
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double real = valueBits.FPUnpackCv(out FPType type, out bool sign, context);
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float result;
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if (type == FPType.SNaN || type == FPType.QNaN)
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{
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if ((context.Fpcr & FPCR.Dn) != 0)
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{
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result = FPDefaultNaN();
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}
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else
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{
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result = FPConvertNaN(valueBits);
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}
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if (type == FPType.SNaN)
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{
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FPProcessException(FPException.InvalidOp, context);
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}
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}
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else if (type == FPType.Infinity)
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{
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result = FPInfinity(sign);
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}
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else if (type == FPType.Zero)
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{
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result = FPZero(sign);
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}
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else
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{
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result = FPRoundCv(real, context);
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}
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return result;
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}
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private static float FPDefaultNaN()
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{
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return -float.NaN;
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}
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private static float FPInfinity(bool sign)
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{
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return sign ? float.NegativeInfinity : float.PositiveInfinity;
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}
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private static float FPZero(bool sign)
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{
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return sign ? -0f : +0f;
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}
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private static float FPMaxNormal(bool sign)
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{
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return sign ? float.MinValue : float.MaxValue;
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}
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private static double FPUnpackCv(
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this ushort valueBits,
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out FPType type,
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out bool sign,
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ExecutionContext context)
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{
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sign = (~(uint)valueBits & 0x8000u) == 0u;
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uint exp16 = ((uint)valueBits & 0x7C00u) >> 10;
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uint frac16 = (uint)valueBits & 0x03FFu;
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double real;
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if (exp16 == 0u)
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{
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if (frac16 == 0u)
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{
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type = FPType.Zero;
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real = 0d;
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}
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else
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{
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type = FPType.Nonzero; // Subnormal.
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real = Math.Pow(2d, -14) * ((double)frac16 * Math.Pow(2d, -10));
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}
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}
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else if (exp16 == 0x1Fu && (context.Fpcr & FPCR.Ahp) == 0)
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{
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if (frac16 == 0u)
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{
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type = FPType.Infinity;
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real = Math.Pow(2d, 1000);
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}
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else
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{
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type = (~frac16 & 0x0200u) == 0u ? FPType.QNaN : FPType.SNaN;
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real = 0d;
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}
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}
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else
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{
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type = FPType.Nonzero; // Normal.
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real = Math.Pow(2d, (int)exp16 - 15) * (1d + (double)frac16 * Math.Pow(2d, -10));
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}
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return sign ? -real : real;
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}
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private static float FPRoundCv(double real, ExecutionContext context)
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{
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const int minimumExp = -126;
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const int e = 8;
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const int f = 23;
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bool sign;
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double mantissa;
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if (real < 0d)
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{
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sign = true;
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mantissa = -real;
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}
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else
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{
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sign = false;
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mantissa = real;
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}
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int exponent = 0;
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while (mantissa < 1d)
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{
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mantissa *= 2d;
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exponent--;
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}
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while (mantissa >= 2d)
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{
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mantissa /= 2d;
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exponent++;
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}
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if ((context.Fpcr & FPCR.Fz) != 0 && exponent < minimumExp)
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{
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context.Fpsr |= FPSR.Ufc;
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return FPZero(sign);
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}
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uint biasedExp = (uint)Math.Max(exponent - minimumExp + 1, 0);
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if (biasedExp == 0u)
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{
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mantissa /= Math.Pow(2d, minimumExp - exponent);
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}
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uint intMant = (uint)Math.Floor(mantissa * Math.Pow(2d, f));
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double error = mantissa * Math.Pow(2d, f) - (double)intMant;
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if (biasedExp == 0u && (error != 0d || (context.Fpcr & FPCR.Ufe) != 0))
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{
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FPProcessException(FPException.Underflow, context);
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}
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bool overflowToInf;
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bool roundUp;
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switch (context.Fpcr.GetRoundingMode())
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{
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default:
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case FPRoundingMode.ToNearest:
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roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u));
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overflowToInf = true;
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break;
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case FPRoundingMode.TowardsPlusInfinity:
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roundUp = (error != 0d && !sign);
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overflowToInf = !sign;
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break;
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case FPRoundingMode.TowardsMinusInfinity:
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roundUp = (error != 0d && sign);
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overflowToInf = sign;
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break;
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case FPRoundingMode.TowardsZero:
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roundUp = false;
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overflowToInf = false;
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break;
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}
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if (roundUp)
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{
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intMant++;
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if (intMant == 1u << f)
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{
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biasedExp = 1u;
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}
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if (intMant == 1u << (f + 1))
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{
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biasedExp++;
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intMant >>= 1;
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}
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}
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float result;
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if (biasedExp >= (1u << e) - 1u)
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{
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result = overflowToInf ? FPInfinity(sign) : FPMaxNormal(sign);
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FPProcessException(FPException.Overflow, context);
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error = 1d;
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}
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else
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{
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result = BitConverter.Int32BitsToSingle(
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(int)((sign ? 1u : 0u) << 31 | (biasedExp & 0xFFu) << 23 | (intMant & 0x007FFFFFu)));
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}
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if (error != 0d)
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{
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FPProcessException(FPException.Inexact, context);
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}
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return result;
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}
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private static float FPConvertNaN(ushort valueBits)
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{
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return BitConverter.Int32BitsToSingle(
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(int)(((uint)valueBits & 0x8000u) << 16 | 0x7FC00000u | ((uint)valueBits & 0x01FFu) << 13));
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}
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private static void FPProcessException(FPException exc, ExecutionContext context)
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{
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int enable = (int)exc + 8;
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if ((context.Fpcr & (FPCR)(1 << enable)) != 0)
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{
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throw new NotImplementedException("Floating-point trap handling.");
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}
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else
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{
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context.Fpsr |= (FPSR)(1 << (int)exc);
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}
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}
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}
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static class SoftFloat32_16
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{
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public static ushort FPConvert(float value)
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{
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ExecutionContext context = NativeInterface.GetContext();
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double real = value.FPUnpackCv(out FPType type, out bool sign, out uint valueBits, context);
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bool altHp = (context.Fpcr & FPCR.Ahp) != 0;
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ushort resultBits;
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if (type == FPType.SNaN || type == FPType.QNaN)
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{
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if (altHp)
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{
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resultBits = FPZero(sign);
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}
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else if ((context.Fpcr & FPCR.Dn) != 0)
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{
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resultBits = FPDefaultNaN();
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}
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else
|
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{
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resultBits = FPConvertNaN(valueBits);
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}
|
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if (type == FPType.SNaN || altHp)
|
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{
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FPProcessException(FPException.InvalidOp, context);
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|
|
}
|
|
|
|
}
|
|
|
|
else if (type == FPType.Infinity)
|
|
|
|
{
|
|
|
|
if (altHp)
|
|
|
|
{
|
|
|
|
resultBits = (ushort)((sign ? 1u : 0u) << 15 | 0x7FFFu);
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
resultBits = FPInfinity(sign);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else if (type == FPType.Zero)
|
|
|
|
{
|
|
|
|
resultBits = FPZero(sign);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
resultBits = FPRoundCv(real, context);
|
|
|
|
}
|
|
|
|
|
|
|
|
return resultBits;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static ushort FPDefaultNaN()
|
|
|
|
{
|
|
|
|
return (ushort)0x7E00u;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static ushort FPInfinity(bool sign)
|
|
|
|
{
|
|
|
|
return sign ? (ushort)0xFC00u : (ushort)0x7C00u;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static ushort FPZero(bool sign)
|
|
|
|
{
|
|
|
|
return sign ? (ushort)0x8000u : (ushort)0x0000u;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static ushort FPMaxNormal(bool sign)
|
|
|
|
{
|
|
|
|
return sign ? (ushort)0xFBFFu : (ushort)0x7BFFu;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static double FPUnpackCv(
|
|
|
|
this float value,
|
|
|
|
out FPType type,
|
|
|
|
out bool sign,
|
|
|
|
out uint valueBits,
|
|
|
|
ExecutionContext context)
|
|
|
|
{
|
|
|
|
valueBits = (uint)BitConverter.SingleToInt32Bits(value);
|
|
|
|
|
|
|
|
sign = (~valueBits & 0x80000000u) == 0u;
|
|
|
|
|
|
|
|
uint exp32 = (valueBits & 0x7F800000u) >> 23;
|
|
|
|
uint frac32 = valueBits & 0x007FFFFFu;
|
|
|
|
|
|
|
|
double real;
|
|
|
|
|
|
|
|
if (exp32 == 0u)
|
|
|
|
{
|
|
|
|
if (frac32 == 0u || (context.Fpcr & FPCR.Fz) != 0)
|
|
|
|
{
|
|
|
|
type = FPType.Zero;
|
|
|
|
real = 0d;
|
|
|
|
|
|
|
|
if (frac32 != 0u)
|
|
|
|
{
|
|
|
|
FPProcessException(FPException.InputDenorm, context);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
type = FPType.Nonzero; // Subnormal.
|
|
|
|
real = Math.Pow(2d, -126) * ((double)frac32 * Math.Pow(2d, -23));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else if (exp32 == 0xFFu)
|
|
|
|
{
|
|
|
|
if (frac32 == 0u)
|
|
|
|
{
|
|
|
|
type = FPType.Infinity;
|
|
|
|
real = Math.Pow(2d, 1000);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
type = (~frac32 & 0x00400000u) == 0u ? FPType.QNaN : FPType.SNaN;
|
|
|
|
real = 0d;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
type = FPType.Nonzero; // Normal.
|
|
|
|
real = Math.Pow(2d, (int)exp32 - 127) * (1d + (double)frac32 * Math.Pow(2d, -23));
|
|
|
|
}
|
|
|
|
|
|
|
|
return sign ? -real : real;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static ushort FPRoundCv(double real, ExecutionContext context)
|
|
|
|
{
|
|
|
|
const int minimumExp = -14;
|
|
|
|
|
|
|
|
const int e = 5;
|
|
|
|
const int f = 10;
|
|
|
|
|
|
|
|
bool sign;
|
|
|
|
double mantissa;
|
|
|
|
|
|
|
|
if (real < 0d)
|
|
|
|
{
|
|
|
|
sign = true;
|
|
|
|
mantissa = -real;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
sign = false;
|
|
|
|
mantissa = real;
|
|
|
|
}
|
|
|
|
|
|
|
|
int exponent = 0;
|
|
|
|
|
|
|
|
while (mantissa < 1d)
|
|
|
|
{
|
|
|
|
mantissa *= 2d;
|
|
|
|
exponent--;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (mantissa >= 2d)
|
|
|
|
{
|
|
|
|
mantissa /= 2d;
|
|
|
|
exponent++;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint biasedExp = (uint)Math.Max(exponent - minimumExp + 1, 0);
|
|
|
|
|
|
|
|
if (biasedExp == 0u)
|
|
|
|
{
|
|
|
|
mantissa /= Math.Pow(2d, minimumExp - exponent);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint intMant = (uint)Math.Floor(mantissa * Math.Pow(2d, f));
|
|
|
|
double error = mantissa * Math.Pow(2d, f) - (double)intMant;
|
|
|
|
|
|
|
|
if (biasedExp == 0u && (error != 0d || (context.Fpcr & FPCR.Ufe) != 0))
|
|
|
|
{
|
|
|
|
FPProcessException(FPException.Underflow, context);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool overflowToInf;
|
|
|
|
bool roundUp;
|
|
|
|
|
|
|
|
switch (context.Fpcr.GetRoundingMode())
|
|
|
|
{
|
|
|
|
default:
|
|
|
|
case FPRoundingMode.ToNearest:
|
|
|
|
roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u));
|
|
|
|
overflowToInf = true;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case FPRoundingMode.TowardsPlusInfinity:
|
|
|
|
roundUp = (error != 0d && !sign);
|
|
|
|
overflowToInf = !sign;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case FPRoundingMode.TowardsMinusInfinity:
|
|
|
|
roundUp = (error != 0d && sign);
|
|
|
|
overflowToInf = sign;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case FPRoundingMode.TowardsZero:
|
|
|
|
roundUp = false;
|
|
|
|
overflowToInf = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (roundUp)
|
|
|
|
{
|
|
|
|
intMant++;
|
|
|
|
|
|
|
|
if (intMant == 1u << f)
|
|
|
|
{
|
|
|
|
biasedExp = 1u;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (intMant == 1u << (f + 1))
|
|
|
|
{
|
|
|
|
biasedExp++;
|
|
|
|
intMant >>= 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ushort resultBits;
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Ahp) == 0)
|
|
|
|
{
|
|
|
|
if (biasedExp >= (1u << e) - 1u)
|
|
|
|
{
|
|
|
|
resultBits = overflowToInf ? FPInfinity(sign) : FPMaxNormal(sign);
|
|
|
|
|
|
|
|
FPProcessException(FPException.Overflow, context);
|
|
|
|
|
|
|
|
error = 1d;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
resultBits = (ushort)((sign ? 1u : 0u) << 15 | (biasedExp & 0x1Fu) << 10 | (intMant & 0x03FFu));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (biasedExp >= 1u << e)
|
|
|
|
{
|
|
|
|
resultBits = (ushort)((sign ? 1u : 0u) << 15 | 0x7FFFu);
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
|
|
|
|
error = 0d;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
resultBits = (ushort)((sign ? 1u : 0u) << 15 | (biasedExp & 0x1Fu) << 10 | (intMant & 0x03FFu));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (error != 0d)
|
|
|
|
{
|
|
|
|
FPProcessException(FPException.Inexact, context);
|
|
|
|
}
|
|
|
|
|
|
|
|
return resultBits;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static ushort FPConvertNaN(uint valueBits)
|
|
|
|
{
|
|
|
|
return (ushort)((valueBits & 0x80000000u) >> 16 | 0x7E00u | (valueBits & 0x003FE000u) >> 13);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void FPProcessException(FPException exc, ExecutionContext context)
|
|
|
|
{
|
|
|
|
int enable = (int)exc + 8;
|
|
|
|
|
|
|
|
if ((context.Fpcr & (FPCR)(1 << enable)) != 0)
|
|
|
|
{
|
|
|
|
throw new NotImplementedException("Floating-point trap handling.");
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
context.Fpsr |= (FPSR)(1 << (int)exc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static class SoftFloat32
|
|
|
|
{
|
|
|
|
public static float FPAdd(float value1, float value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context);
|
|
|
|
|
|
|
|
float result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
|
|
|
|
bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
|
|
|
|
|
|
|
|
if (inf1 && inf2 && sign1 == !sign2)
|
|
|
|
{
|
|
|
|
result = FPDefaultNaN();
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else if ((inf1 && !sign1) || (inf2 && !sign2))
|
|
|
|
{
|
|
|
|
result = FPInfinity(false);
|
|
|
|
}
|
|
|
|
else if ((inf1 && sign1) || (inf2 && sign2))
|
|
|
|
{
|
|
|
|
result = FPInfinity(true);
|
|
|
|
}
|
|
|
|
else if (zero1 && zero2 && sign1 == sign2)
|
|
|
|
{
|
|
|
|
result = FPZero(sign1);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = value1 + value2;
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0f);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static int FPCompare(float value1, float value2, bool signalNaNs)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out _, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out _, context);
|
|
|
|
|
|
|
|
int result;
|
|
|
|
|
|
|
|
if (type1 == FPType.SNaN || type1 == FPType.QNaN || type2 == FPType.SNaN || type2 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
result = 0b0011;
|
|
|
|
|
|
|
|
if (type1 == FPType.SNaN || type2 == FPType.SNaN || signalNaNs)
|
|
|
|
{
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (value1 == value2)
|
|
|
|
{
|
|
|
|
result = 0b0110;
|
|
|
|
}
|
|
|
|
else if (value1 < value2)
|
|
|
|
{
|
|
|
|
result = 0b1000;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = 0b0010;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPCompareEQ(float value1, float value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out _, out _, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out _, out _, context);
|
|
|
|
|
|
|
|
float result;
|
|
|
|
|
|
|
|
if (type1 == FPType.SNaN || type1 == FPType.QNaN || type2 == FPType.SNaN || type2 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
result = ZerosOrOnes(false);
|
|
|
|
|
|
|
|
if (type1 == FPType.SNaN || type2 == FPType.SNaN)
|
|
|
|
{
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = ZerosOrOnes(value1 == value2);
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPCompareGE(float value1, float value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out _, out _, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out _, out _, context);
|
|
|
|
|
|
|
|
float result;
|
|
|
|
|
|
|
|
if (type1 == FPType.SNaN || type1 == FPType.QNaN || type2 == FPType.SNaN || type2 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
result = ZerosOrOnes(false);
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = ZerosOrOnes(value1 >= value2);
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPCompareGT(float value1, float value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out _, out _, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out _, out _, context);
|
|
|
|
|
|
|
|
float result;
|
|
|
|
|
|
|
|
if (type1 == FPType.SNaN || type1 == FPType.QNaN || type2 == FPType.SNaN || type2 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
result = ZerosOrOnes(false);
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = ZerosOrOnes(value1 > value2);
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPCompareLE(float value1, float value2)
|
|
|
|
{
|
|
|
|
return FPCompareGE(value2, value1);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPCompareLT(float value1, float value2)
|
|
|
|
{
|
|
|
|
return FPCompareGT(value2, value1);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPDiv(float value1, float value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context);
|
|
|
|
|
|
|
|
float result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
|
|
|
|
bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
|
|
|
|
|
|
|
|
if ((inf1 && inf2) || (zero1 && zero2))
|
|
|
|
{
|
|
|
|
result = FPDefaultNaN();
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else if (inf1 || zero2)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign1 ^ sign2);
|
|
|
|
|
|
|
|
if (!inf1)
|
|
|
|
{
|
|
|
|
FPProcessException(FPException.DivideByZero, context);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else if (zero1 || inf2)
|
|
|
|
{
|
|
|
|
result = FPZero(sign1 ^ sign2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = value1 / value2;
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0f);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPMax(float value1, float value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context);
|
|
|
|
|
|
|
|
float result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
if (value1 > value2)
|
|
|
|
{
|
|
|
|
if (type1 == FPType.Infinity)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign1);
|
|
|
|
}
|
|
|
|
else if (type1 == FPType.Zero)
|
|
|
|
{
|
|
|
|
result = FPZero(sign1 && sign2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = value1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (type2 == FPType.Infinity)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign2);
|
|
|
|
}
|
|
|
|
else if (type2 == FPType.Zero)
|
|
|
|
{
|
|
|
|
result = FPZero(sign1 && sign2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = value2;
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0f);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPMaxNum(float value1, float value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1.FPUnpack(out FPType type1, out _, out _, context);
|
|
|
|
value2.FPUnpack(out FPType type2, out _, out _, context);
|
|
|
|
|
|
|
|
if (type1 == FPType.QNaN && type2 != FPType.QNaN)
|
|
|
|
{
|
|
|
|
value1 = FPInfinity(true);
|
|
|
|
}
|
|
|
|
else if (type1 != FPType.QNaN && type2 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
value2 = FPInfinity(true);
|
|
|
|
}
|
|
|
|
|
|
|
|
return FPMax(value1, value2);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPMin(float value1, float value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context);
|
|
|
|
|
|
|
|
float result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
if (value1 < value2)
|
|
|
|
{
|
|
|
|
if (type1 == FPType.Infinity)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign1);
|
|
|
|
}
|
|
|
|
else if (type1 == FPType.Zero)
|
|
|
|
{
|
|
|
|
result = FPZero(sign1 || sign2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = value1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (type2 == FPType.Infinity)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign2);
|
|
|
|
}
|
|
|
|
else if (type2 == FPType.Zero)
|
|
|
|
{
|
|
|
|
result = FPZero(sign1 || sign2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = value2;
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0f);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPMinNum(float value1, float value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1.FPUnpack(out FPType type1, out _, out _, context);
|
|
|
|
value2.FPUnpack(out FPType type2, out _, out _, context);
|
|
|
|
|
|
|
|
if (type1 == FPType.QNaN && type2 != FPType.QNaN)
|
|
|
|
{
|
|
|
|
value1 = FPInfinity(false);
|
|
|
|
}
|
|
|
|
else if (type1 != FPType.QNaN && type2 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
value2 = FPInfinity(false);
|
|
|
|
}
|
|
|
|
|
|
|
|
return FPMin(value1, value2);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPMul(float value1, float value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context);
|
|
|
|
|
|
|
|
float result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
|
|
|
|
bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
|
|
|
|
|
|
|
|
if ((inf1 && zero2) || (zero1 && inf2))
|
|
|
|
{
|
|
|
|
result = FPDefaultNaN();
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else if (inf1 || inf2)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign1 ^ sign2);
|
|
|
|
}
|
|
|
|
else if (zero1 || zero2)
|
|
|
|
{
|
|
|
|
result = FPZero(sign1 ^ sign2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = value1 * value2;
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0f);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPMulAdd(float valueA, float value1, float value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
valueA = valueA.FPUnpack(out FPType typeA, out bool signA, out uint addend, context);
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context);
|
|
|
|
|
|
|
|
bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
|
|
|
|
bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
|
|
|
|
|
|
|
|
float result = FPProcessNaNs3(typeA, type1, type2, addend, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (typeA == FPType.QNaN && ((inf1 && zero2) || (zero1 && inf2)))
|
|
|
|
{
|
|
|
|
result = FPDefaultNaN();
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
bool infA = typeA == FPType.Infinity; bool zeroA = typeA == FPType.Zero;
|
|
|
|
|
|
|
|
bool signP = sign1 ^ sign2;
|
|
|
|
bool infP = inf1 || inf2;
|
|
|
|
bool zeroP = zero1 || zero2;
|
|
|
|
|
|
|
|
if ((inf1 && zero2) || (zero1 && inf2) || (infA && infP && signA != signP))
|
|
|
|
{
|
|
|
|
result = FPDefaultNaN();
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else if ((infA && !signA) || (infP && !signP))
|
|
|
|
{
|
|
|
|
result = FPInfinity(false);
|
|
|
|
}
|
|
|
|
else if ((infA && signA) || (infP && signP))
|
|
|
|
{
|
|
|
|
result = FPInfinity(true);
|
|
|
|
}
|
|
|
|
else if (zeroA && zeroP && signA == signP)
|
|
|
|
{
|
|
|
|
result = FPZero(signA);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2019-10-31 12:09:03 -06:00
|
|
|
result = MathF.FusedMultiplyAdd(value1, value2, valueA);
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 12:56:22 -06:00
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0f);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPMulSub(float valueA, float value1, float value2)
|
|
|
|
{
|
|
|
|
value1 = value1.FPNeg();
|
|
|
|
|
|
|
|
return FPMulAdd(valueA, value1, value2);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPMulX(float value1, float value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context);
|
|
|
|
|
|
|
|
float result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
|
|
|
|
bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
|
|
|
|
|
|
|
|
if ((inf1 && zero2) || (zero1 && inf2))
|
|
|
|
{
|
|
|
|
result = FPTwo(sign1 ^ sign2);
|
|
|
|
}
|
|
|
|
else if (inf1 || inf2)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign1 ^ sign2);
|
|
|
|
}
|
|
|
|
else if (zero1 || zero2)
|
|
|
|
{
|
|
|
|
result = FPZero(sign1 ^ sign2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = value1 * value2;
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0f);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
2019-12-07 05:45:32 -07:00
|
|
|
public static float FPNegMulAdd(float valueA, float value1, float value2)
|
|
|
|
{
|
|
|
|
valueA = valueA.FPNeg();
|
|
|
|
value1 = value1.FPNeg();
|
|
|
|
|
|
|
|
return FPMulAdd(valueA, value1, value2);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPNegMulSub(float valueA, float value1, float value2)
|
|
|
|
{
|
|
|
|
valueA = valueA.FPNeg();
|
|
|
|
|
|
|
|
return FPMulAdd(valueA, value1, value2);
|
|
|
|
}
|
|
|
|
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 12:56:22 -06:00
|
|
|
public static float FPRecipEstimate(float value)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value.FPUnpack(out FPType type, out bool sign, out uint op, context);
|
|
|
|
|
|
|
|
float result;
|
|
|
|
|
|
|
|
if (type == FPType.SNaN || type == FPType.QNaN)
|
|
|
|
{
|
|
|
|
result = FPProcessNaN(type, op, context);
|
|
|
|
}
|
|
|
|
else if (type == FPType.Infinity)
|
|
|
|
{
|
|
|
|
result = FPZero(sign);
|
|
|
|
}
|
|
|
|
else if (type == FPType.Zero)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign);
|
|
|
|
|
|
|
|
FPProcessException(FPException.DivideByZero, context);
|
|
|
|
}
|
|
|
|
else if (MathF.Abs(value) < MathF.Pow(2f, -128))
|
|
|
|
{
|
|
|
|
bool overflowToInf;
|
|
|
|
|
|
|
|
switch (context.Fpcr.GetRoundingMode())
|
|
|
|
{
|
|
|
|
default:
|
|
|
|
case FPRoundingMode.ToNearest: overflowToInf = true; break;
|
|
|
|
case FPRoundingMode.TowardsPlusInfinity: overflowToInf = !sign; break;
|
|
|
|
case FPRoundingMode.TowardsMinusInfinity: overflowToInf = sign; break;
|
|
|
|
case FPRoundingMode.TowardsZero: overflowToInf = false; break;
|
|
|
|
}
|
|
|
|
|
|
|
|
result = overflowToInf ? FPInfinity(sign) : FPMaxNormal(sign);
|
|
|
|
|
|
|
|
FPProcessException(FPException.Overflow, context);
|
|
|
|
FPProcessException(FPException.Inexact, context);
|
|
|
|
}
|
|
|
|
else if ((context.Fpcr & FPCR.Fz) != 0 && (MathF.Abs(value) >= MathF.Pow(2f, 126)))
|
|
|
|
{
|
|
|
|
result = FPZero(sign);
|
|
|
|
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
ulong fraction = (ulong)(op & 0x007FFFFFu) << 29;
|
|
|
|
uint exp = (op & 0x7F800000u) >> 23;
|
|
|
|
|
|
|
|
if (exp == 0u)
|
|
|
|
{
|
|
|
|
if ((fraction & 0x0008000000000000ul) == 0ul)
|
|
|
|
{
|
|
|
|
fraction = (fraction & 0x0003FFFFFFFFFFFFul) << 2;
|
|
|
|
exp -= 1u;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
fraction = (fraction & 0x0007FFFFFFFFFFFFul) << 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
uint scaled = (uint)(((fraction & 0x000FF00000000000ul) | 0x0010000000000000ul) >> 44);
|
|
|
|
|
|
|
|
uint resultExp = 253u - exp;
|
|
|
|
|
|
|
|
uint estimate = (uint)SoftFloat.RecipEstimateTable[scaled - 256u] + 256u;
|
|
|
|
|
|
|
|
fraction = (ulong)(estimate & 0xFFu) << 44;
|
|
|
|
|
|
|
|
if (resultExp == 0u)
|
|
|
|
{
|
|
|
|
fraction = ((fraction & 0x000FFFFFFFFFFFFEul) | 0x0010000000000000ul) >> 1;
|
|
|
|
}
|
|
|
|
else if (resultExp + 1u == 0u)
|
|
|
|
{
|
|
|
|
fraction = ((fraction & 0x000FFFFFFFFFFFFCul) | 0x0010000000000000ul) >> 2;
|
|
|
|
resultExp = 0u;
|
|
|
|
}
|
|
|
|
|
|
|
|
result = BitConverter.Int32BitsToSingle(
|
|
|
|
(int)((sign ? 1u : 0u) << 31 | (resultExp & 0xFFu) << 23 | (uint)(fraction >> 29) & 0x007FFFFFu));
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPRecipStepFused(float value1, float value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPNeg();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context);
|
|
|
|
|
|
|
|
float result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
|
|
|
|
bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
|
|
|
|
|
|
|
|
if ((inf1 && zero2) || (zero1 && inf2))
|
|
|
|
{
|
|
|
|
result = FPTwo(false);
|
|
|
|
}
|
|
|
|
else if (inf1 || inf2)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign1 ^ sign2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2019-10-31 12:09:03 -06:00
|
|
|
result = MathF.FusedMultiplyAdd(value1, value2, 2f);
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 12:56:22 -06:00
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0f);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPRecpX(float value)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value.FPUnpack(out FPType type, out bool sign, out uint op, context);
|
|
|
|
|
|
|
|
float result;
|
|
|
|
|
|
|
|
if (type == FPType.SNaN || type == FPType.QNaN)
|
|
|
|
{
|
|
|
|
result = FPProcessNaN(type, op, context);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
uint notExp = (~op >> 23) & 0xFFu;
|
|
|
|
uint maxExp = 0xFEu;
|
|
|
|
|
|
|
|
result = BitConverter.Int32BitsToSingle(
|
|
|
|
(int)((sign ? 1u : 0u) << 31 | (notExp == 0xFFu ? maxExp : notExp) << 23));
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPRSqrtEstimate(float value)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value.FPUnpack(out FPType type, out bool sign, out uint op, context);
|
|
|
|
|
|
|
|
float result;
|
|
|
|
|
|
|
|
if (type == FPType.SNaN || type == FPType.QNaN)
|
|
|
|
{
|
|
|
|
result = FPProcessNaN(type, op, context);
|
|
|
|
}
|
|
|
|
else if (type == FPType.Zero)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign);
|
|
|
|
|
|
|
|
FPProcessException(FPException.DivideByZero, context);
|
|
|
|
}
|
|
|
|
else if (sign)
|
|
|
|
{
|
|
|
|
result = FPDefaultNaN();
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else if (type == FPType.Infinity)
|
|
|
|
{
|
|
|
|
result = FPZero(false);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
ulong fraction = (ulong)(op & 0x007FFFFFu) << 29;
|
|
|
|
uint exp = (op & 0x7F800000u) >> 23;
|
|
|
|
|
|
|
|
if (exp == 0u)
|
|
|
|
{
|
|
|
|
while ((fraction & 0x0008000000000000ul) == 0ul)
|
|
|
|
{
|
|
|
|
fraction = (fraction & 0x0007FFFFFFFFFFFFul) << 1;
|
|
|
|
exp -= 1u;
|
|
|
|
}
|
|
|
|
|
|
|
|
fraction = (fraction & 0x0007FFFFFFFFFFFFul) << 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint scaled;
|
|
|
|
|
|
|
|
if ((exp & 1u) == 0u)
|
|
|
|
{
|
|
|
|
scaled = (uint)(((fraction & 0x000FF00000000000ul) | 0x0010000000000000ul) >> 44);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
scaled = (uint)(((fraction & 0x000FE00000000000ul) | 0x0010000000000000ul) >> 45);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint resultExp = (380u - exp) >> 1;
|
|
|
|
|
|
|
|
uint estimate = (uint)SoftFloat.RecipSqrtEstimateTable[scaled - 128u] + 256u;
|
|
|
|
|
|
|
|
result = BitConverter.Int32BitsToSingle((int)((resultExp & 0xFFu) << 23 | (estimate & 0xFFu) << 15));
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPRSqrtStepFused(float value1, float value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPNeg();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context);
|
|
|
|
|
|
|
|
float result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
|
|
|
|
bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
|
|
|
|
|
|
|
|
if ((inf1 && zero2) || (zero1 && inf2))
|
|
|
|
{
|
|
|
|
result = FPOnePointFive(false);
|
|
|
|
}
|
|
|
|
else if (inf1 || inf2)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign1 ^ sign2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2019-10-31 12:09:03 -06:00
|
|
|
result = MathF.FusedMultiplyAdd(value1, value2, 3f) / 2f;
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 12:56:22 -06:00
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0f);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPSqrt(float value)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value = value.FPUnpack(out FPType type, out bool sign, out uint op, context);
|
|
|
|
|
|
|
|
float result;
|
|
|
|
|
|
|
|
if (type == FPType.SNaN || type == FPType.QNaN)
|
|
|
|
{
|
|
|
|
result = FPProcessNaN(type, op, context);
|
|
|
|
}
|
|
|
|
else if (type == FPType.Zero)
|
|
|
|
{
|
|
|
|
result = FPZero(sign);
|
|
|
|
}
|
|
|
|
else if (type == FPType.Infinity && !sign)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign);
|
|
|
|
}
|
|
|
|
else if (sign)
|
|
|
|
{
|
|
|
|
result = FPDefaultNaN();
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = MathF.Sqrt(value);
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0f);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static float FPSub(float value1, float value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context);
|
|
|
|
|
|
|
|
float result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
|
|
|
|
bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
|
|
|
|
|
|
|
|
if (inf1 && inf2 && sign1 == sign2)
|
|
|
|
{
|
|
|
|
result = FPDefaultNaN();
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else if ((inf1 && !sign1) || (inf2 && sign2))
|
|
|
|
{
|
|
|
|
result = FPInfinity(false);
|
|
|
|
}
|
|
|
|
else if ((inf1 && sign1) || (inf2 && !sign2))
|
|
|
|
{
|
|
|
|
result = FPInfinity(true);
|
|
|
|
}
|
|
|
|
else if (zero1 && zero2 && sign1 == !sign2)
|
|
|
|
{
|
|
|
|
result = FPZero(sign1);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = value1 - value2;
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && float.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0f);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static float FPDefaultNaN()
|
|
|
|
{
|
|
|
|
return -float.NaN;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static float FPInfinity(bool sign)
|
|
|
|
{
|
|
|
|
return sign ? float.NegativeInfinity : float.PositiveInfinity;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static float FPZero(bool sign)
|
|
|
|
{
|
|
|
|
return sign ? -0f : +0f;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static float FPMaxNormal(bool sign)
|
|
|
|
{
|
|
|
|
return sign ? float.MinValue : float.MaxValue;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static float FPTwo(bool sign)
|
|
|
|
{
|
|
|
|
return sign ? -2f : +2f;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static float FPOnePointFive(bool sign)
|
|
|
|
{
|
|
|
|
return sign ? -1.5f : +1.5f;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static float FPNeg(this float value)
|
|
|
|
{
|
|
|
|
return -value;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static float ZerosOrOnes(bool ones)
|
|
|
|
{
|
|
|
|
return BitConverter.Int32BitsToSingle(ones ? -1 : 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static float FPUnpack(
|
|
|
|
this float value,
|
|
|
|
out FPType type,
|
|
|
|
out bool sign,
|
|
|
|
out uint valueBits,
|
|
|
|
ExecutionContext context)
|
|
|
|
{
|
|
|
|
valueBits = (uint)BitConverter.SingleToInt32Bits(value);
|
|
|
|
|
|
|
|
sign = (~valueBits & 0x80000000u) == 0u;
|
|
|
|
|
|
|
|
if ((valueBits & 0x7F800000u) == 0u)
|
|
|
|
{
|
|
|
|
if ((valueBits & 0x007FFFFFu) == 0u || (context.Fpcr & FPCR.Fz) != 0)
|
|
|
|
{
|
|
|
|
type = FPType.Zero;
|
|
|
|
value = FPZero(sign);
|
|
|
|
|
|
|
|
if ((valueBits & 0x007FFFFFu) != 0u)
|
|
|
|
{
|
|
|
|
FPProcessException(FPException.InputDenorm, context);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
type = FPType.Nonzero;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else if ((~valueBits & 0x7F800000u) == 0u)
|
|
|
|
{
|
|
|
|
if ((valueBits & 0x007FFFFFu) == 0u)
|
|
|
|
{
|
|
|
|
type = FPType.Infinity;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
type = (~valueBits & 0x00400000u) == 0u ? FPType.QNaN : FPType.SNaN;
|
|
|
|
value = FPZero(sign);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
type = FPType.Nonzero;
|
|
|
|
}
|
|
|
|
|
|
|
|
return value;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static float FPProcessNaNs(
|
|
|
|
FPType type1,
|
|
|
|
FPType type2,
|
|
|
|
uint op1,
|
|
|
|
uint op2,
|
|
|
|
out bool done,
|
|
|
|
ExecutionContext context)
|
|
|
|
{
|
|
|
|
done = true;
|
|
|
|
|
|
|
|
if (type1 == FPType.SNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type1, op1, context);
|
|
|
|
}
|
|
|
|
else if (type2 == FPType.SNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type2, op2, context);
|
|
|
|
}
|
|
|
|
else if (type1 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type1, op1, context);
|
|
|
|
}
|
|
|
|
else if (type2 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type2, op2, context);
|
|
|
|
}
|
|
|
|
|
|
|
|
done = false;
|
|
|
|
|
|
|
|
return FPZero(false);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static float FPProcessNaNs3(
|
|
|
|
FPType type1,
|
|
|
|
FPType type2,
|
|
|
|
FPType type3,
|
|
|
|
uint op1,
|
|
|
|
uint op2,
|
|
|
|
uint op3,
|
|
|
|
out bool done,
|
|
|
|
ExecutionContext context)
|
|
|
|
{
|
|
|
|
done = true;
|
|
|
|
|
|
|
|
if (type1 == FPType.SNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type1, op1, context);
|
|
|
|
}
|
|
|
|
else if (type2 == FPType.SNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type2, op2, context);
|
|
|
|
}
|
|
|
|
else if (type3 == FPType.SNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type3, op3, context);
|
|
|
|
}
|
|
|
|
else if (type1 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type1, op1, context);
|
|
|
|
}
|
|
|
|
else if (type2 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type2, op2, context);
|
|
|
|
}
|
|
|
|
else if (type3 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type3, op3, context);
|
|
|
|
}
|
|
|
|
|
|
|
|
done = false;
|
|
|
|
|
|
|
|
return FPZero(false);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static float FPProcessNaN(FPType type, uint op, ExecutionContext context)
|
|
|
|
{
|
|
|
|
if (type == FPType.SNaN)
|
|
|
|
{
|
|
|
|
op |= 1u << 22;
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Dn) != 0)
|
|
|
|
{
|
|
|
|
return FPDefaultNaN();
|
|
|
|
}
|
|
|
|
|
|
|
|
return BitConverter.Int32BitsToSingle((int)op);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void FPProcessException(FPException exc, ExecutionContext context)
|
|
|
|
{
|
|
|
|
int enable = (int)exc + 8;
|
|
|
|
|
|
|
|
if ((context.Fpcr & (FPCR)(1 << enable)) != 0)
|
|
|
|
{
|
|
|
|
throw new NotImplementedException("Floating-point trap handling.");
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
context.Fpsr |= (FPSR)(1 << (int)exc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static class SoftFloat64
|
|
|
|
{
|
|
|
|
public static double FPAdd(double value1, double value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context);
|
|
|
|
|
|
|
|
double result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
|
|
|
|
bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
|
|
|
|
|
|
|
|
if (inf1 && inf2 && sign1 == !sign2)
|
|
|
|
{
|
|
|
|
result = FPDefaultNaN();
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else if ((inf1 && !sign1) || (inf2 && !sign2))
|
|
|
|
{
|
|
|
|
result = FPInfinity(false);
|
|
|
|
}
|
|
|
|
else if ((inf1 && sign1) || (inf2 && sign2))
|
|
|
|
{
|
|
|
|
result = FPInfinity(true);
|
|
|
|
}
|
|
|
|
else if (zero1 && zero2 && sign1 == sign2)
|
|
|
|
{
|
|
|
|
result = FPZero(sign1);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = value1 + value2;
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && double.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0d);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static int FPCompare(double value1, double value2, bool signalNaNs)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out _, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out _, context);
|
|
|
|
|
|
|
|
int result;
|
|
|
|
|
|
|
|
if (type1 == FPType.SNaN || type1 == FPType.QNaN || type2 == FPType.SNaN || type2 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
result = 0b0011;
|
|
|
|
|
|
|
|
if (type1 == FPType.SNaN || type2 == FPType.SNaN || signalNaNs)
|
|
|
|
{
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (value1 == value2)
|
|
|
|
{
|
|
|
|
result = 0b0110;
|
|
|
|
}
|
|
|
|
else if (value1 < value2)
|
|
|
|
{
|
|
|
|
result = 0b1000;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = 0b0010;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPCompareEQ(double value1, double value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out _, out _, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out _, out _, context);
|
|
|
|
|
|
|
|
double result;
|
|
|
|
|
|
|
|
if (type1 == FPType.SNaN || type1 == FPType.QNaN || type2 == FPType.SNaN || type2 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
result = ZerosOrOnes(false);
|
|
|
|
|
|
|
|
if (type1 == FPType.SNaN || type2 == FPType.SNaN)
|
|
|
|
{
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = ZerosOrOnes(value1 == value2);
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPCompareGE(double value1, double value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out _, out _, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out _, out _, context);
|
|
|
|
|
|
|
|
double result;
|
|
|
|
|
|
|
|
if (type1 == FPType.SNaN || type1 == FPType.QNaN || type2 == FPType.SNaN || type2 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
result = ZerosOrOnes(false);
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = ZerosOrOnes(value1 >= value2);
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPCompareGT(double value1, double value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out _, out _, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out _, out _, context);
|
|
|
|
|
|
|
|
double result;
|
|
|
|
|
|
|
|
if (type1 == FPType.SNaN || type1 == FPType.QNaN || type2 == FPType.SNaN || type2 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
result = ZerosOrOnes(false);
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = ZerosOrOnes(value1 > value2);
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPCompareLE(double value1, double value2)
|
|
|
|
{
|
|
|
|
return FPCompareGE(value2, value1);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPCompareLT(double value1, double value2)
|
|
|
|
{
|
|
|
|
return FPCompareGT(value2, value1);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPDiv(double value1, double value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context);
|
|
|
|
|
|
|
|
double result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
|
|
|
|
bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
|
|
|
|
|
|
|
|
if ((inf1 && inf2) || (zero1 && zero2))
|
|
|
|
{
|
|
|
|
result = FPDefaultNaN();
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else if (inf1 || zero2)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign1 ^ sign2);
|
|
|
|
|
|
|
|
if (!inf1)
|
|
|
|
{
|
|
|
|
FPProcessException(FPException.DivideByZero, context);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else if (zero1 || inf2)
|
|
|
|
{
|
|
|
|
result = FPZero(sign1 ^ sign2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = value1 / value2;
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && double.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0d);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPMax(double value1, double value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context);
|
|
|
|
|
|
|
|
double result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
if (value1 > value2)
|
|
|
|
{
|
|
|
|
if (type1 == FPType.Infinity)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign1);
|
|
|
|
}
|
|
|
|
else if (type1 == FPType.Zero)
|
|
|
|
{
|
|
|
|
result = FPZero(sign1 && sign2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = value1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (type2 == FPType.Infinity)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign2);
|
|
|
|
}
|
|
|
|
else if (type2 == FPType.Zero)
|
|
|
|
{
|
|
|
|
result = FPZero(sign1 && sign2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = value2;
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && double.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0d);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPMaxNum(double value1, double value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1.FPUnpack(out FPType type1, out _, out _, context);
|
|
|
|
value2.FPUnpack(out FPType type2, out _, out _, context);
|
|
|
|
|
|
|
|
if (type1 == FPType.QNaN && type2 != FPType.QNaN)
|
|
|
|
{
|
|
|
|
value1 = FPInfinity(true);
|
|
|
|
}
|
|
|
|
else if (type1 != FPType.QNaN && type2 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
value2 = FPInfinity(true);
|
|
|
|
}
|
|
|
|
|
|
|
|
return FPMax(value1, value2);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPMin(double value1, double value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context);
|
|
|
|
|
|
|
|
double result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
if (value1 < value2)
|
|
|
|
{
|
|
|
|
if (type1 == FPType.Infinity)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign1);
|
|
|
|
}
|
|
|
|
else if (type1 == FPType.Zero)
|
|
|
|
{
|
|
|
|
result = FPZero(sign1 || sign2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = value1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (type2 == FPType.Infinity)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign2);
|
|
|
|
}
|
|
|
|
else if (type2 == FPType.Zero)
|
|
|
|
{
|
|
|
|
result = FPZero(sign1 || sign2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = value2;
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && double.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0d);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPMinNum(double value1, double value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1.FPUnpack(out FPType type1, out _, out _, context);
|
|
|
|
value2.FPUnpack(out FPType type2, out _, out _, context);
|
|
|
|
|
|
|
|
if (type1 == FPType.QNaN && type2 != FPType.QNaN)
|
|
|
|
{
|
|
|
|
value1 = FPInfinity(false);
|
|
|
|
}
|
|
|
|
else if (type1 != FPType.QNaN && type2 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
value2 = FPInfinity(false);
|
|
|
|
}
|
|
|
|
|
|
|
|
return FPMin(value1, value2);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPMul(double value1, double value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context);
|
|
|
|
|
|
|
|
double result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
|
|
|
|
bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
|
|
|
|
|
|
|
|
if ((inf1 && zero2) || (zero1 && inf2))
|
|
|
|
{
|
|
|
|
result = FPDefaultNaN();
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else if (inf1 || inf2)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign1 ^ sign2);
|
|
|
|
}
|
|
|
|
else if (zero1 || zero2)
|
|
|
|
{
|
|
|
|
result = FPZero(sign1 ^ sign2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = value1 * value2;
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && double.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0d);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPMulAdd(double valueA, double value1, double value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
valueA = valueA.FPUnpack(out FPType typeA, out bool signA, out ulong addend, context);
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context);
|
|
|
|
|
|
|
|
bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
|
|
|
|
bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
|
|
|
|
|
|
|
|
double result = FPProcessNaNs3(typeA, type1, type2, addend, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (typeA == FPType.QNaN && ((inf1 && zero2) || (zero1 && inf2)))
|
|
|
|
{
|
|
|
|
result = FPDefaultNaN();
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
bool infA = typeA == FPType.Infinity; bool zeroA = typeA == FPType.Zero;
|
|
|
|
|
|
|
|
bool signP = sign1 ^ sign2;
|
|
|
|
bool infP = inf1 || inf2;
|
|
|
|
bool zeroP = zero1 || zero2;
|
|
|
|
|
|
|
|
if ((inf1 && zero2) || (zero1 && inf2) || (infA && infP && signA != signP))
|
|
|
|
{
|
|
|
|
result = FPDefaultNaN();
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else if ((infA && !signA) || (infP && !signP))
|
|
|
|
{
|
|
|
|
result = FPInfinity(false);
|
|
|
|
}
|
|
|
|
else if ((infA && signA) || (infP && signP))
|
|
|
|
{
|
|
|
|
result = FPInfinity(true);
|
|
|
|
}
|
|
|
|
else if (zeroA && zeroP && signA == signP)
|
|
|
|
{
|
|
|
|
result = FPZero(signA);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2019-10-31 12:09:03 -06:00
|
|
|
result = Math.FusedMultiplyAdd(value1, value2, valueA);
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 12:56:22 -06:00
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && double.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0d);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPMulSub(double valueA, double value1, double value2)
|
|
|
|
{
|
|
|
|
value1 = value1.FPNeg();
|
|
|
|
|
|
|
|
return FPMulAdd(valueA, value1, value2);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPMulX(double value1, double value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context);
|
|
|
|
|
|
|
|
double result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
|
|
|
|
bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
|
|
|
|
|
|
|
|
if ((inf1 && zero2) || (zero1 && inf2))
|
|
|
|
{
|
|
|
|
result = FPTwo(sign1 ^ sign2);
|
|
|
|
}
|
|
|
|
else if (inf1 || inf2)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign1 ^ sign2);
|
|
|
|
}
|
|
|
|
else if (zero1 || zero2)
|
|
|
|
{
|
|
|
|
result = FPZero(sign1 ^ sign2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = value1 * value2;
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && double.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0d);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
2019-12-07 05:45:32 -07:00
|
|
|
public static double FPNegMulAdd(double valueA, double value1, double value2)
|
|
|
|
{
|
|
|
|
valueA = valueA.FPNeg();
|
|
|
|
value1 = value1.FPNeg();
|
|
|
|
|
|
|
|
return FPMulAdd(valueA, value1, value2);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPNegMulSub(double valueA, double value1, double value2)
|
|
|
|
{
|
|
|
|
valueA = valueA.FPNeg();
|
|
|
|
|
|
|
|
return FPMulAdd(valueA, value1, value2);
|
|
|
|
}
|
|
|
|
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 12:56:22 -06:00
|
|
|
public static double FPRecipEstimate(double value)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value.FPUnpack(out FPType type, out bool sign, out ulong op, context);
|
|
|
|
|
|
|
|
double result;
|
|
|
|
|
|
|
|
if (type == FPType.SNaN || type == FPType.QNaN)
|
|
|
|
{
|
|
|
|
result = FPProcessNaN(type, op, context);
|
|
|
|
}
|
|
|
|
else if (type == FPType.Infinity)
|
|
|
|
{
|
|
|
|
result = FPZero(sign);
|
|
|
|
}
|
|
|
|
else if (type == FPType.Zero)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign);
|
|
|
|
|
|
|
|
FPProcessException(FPException.DivideByZero, context);
|
|
|
|
}
|
|
|
|
else if (Math.Abs(value) < Math.Pow(2d, -1024))
|
|
|
|
{
|
|
|
|
bool overflowToInf;
|
|
|
|
|
|
|
|
switch (context.Fpcr.GetRoundingMode())
|
|
|
|
{
|
|
|
|
default:
|
|
|
|
case FPRoundingMode.ToNearest: overflowToInf = true; break;
|
|
|
|
case FPRoundingMode.TowardsPlusInfinity: overflowToInf = !sign; break;
|
|
|
|
case FPRoundingMode.TowardsMinusInfinity: overflowToInf = sign; break;
|
|
|
|
case FPRoundingMode.TowardsZero: overflowToInf = false; break;
|
|
|
|
}
|
|
|
|
|
|
|
|
result = overflowToInf ? FPInfinity(sign) : FPMaxNormal(sign);
|
|
|
|
|
|
|
|
FPProcessException(FPException.Overflow, context);
|
|
|
|
FPProcessException(FPException.Inexact, context);
|
|
|
|
}
|
|
|
|
else if ((context.Fpcr & FPCR.Fz) != 0 && (Math.Abs(value) >= Math.Pow(2d, 1022)))
|
|
|
|
{
|
|
|
|
result = FPZero(sign);
|
|
|
|
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
ulong fraction = op & 0x000FFFFFFFFFFFFFul;
|
|
|
|
uint exp = (uint)((op & 0x7FF0000000000000ul) >> 52);
|
|
|
|
|
|
|
|
if (exp == 0u)
|
|
|
|
{
|
|
|
|
if ((fraction & 0x0008000000000000ul) == 0ul)
|
|
|
|
{
|
|
|
|
fraction = (fraction & 0x0003FFFFFFFFFFFFul) << 2;
|
|
|
|
exp -= 1u;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
fraction = (fraction & 0x0007FFFFFFFFFFFFul) << 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
uint scaled = (uint)(((fraction & 0x000FF00000000000ul) | 0x0010000000000000ul) >> 44);
|
|
|
|
|
|
|
|
uint resultExp = 2045u - exp;
|
|
|
|
|
|
|
|
uint estimate = (uint)SoftFloat.RecipEstimateTable[scaled - 256u] + 256u;
|
|
|
|
|
|
|
|
fraction = (ulong)(estimate & 0xFFu) << 44;
|
|
|
|
|
|
|
|
if (resultExp == 0u)
|
|
|
|
{
|
|
|
|
fraction = ((fraction & 0x000FFFFFFFFFFFFEul) | 0x0010000000000000ul) >> 1;
|
|
|
|
}
|
|
|
|
else if (resultExp + 1u == 0u)
|
|
|
|
{
|
|
|
|
fraction = ((fraction & 0x000FFFFFFFFFFFFCul) | 0x0010000000000000ul) >> 2;
|
|
|
|
resultExp = 0u;
|
|
|
|
}
|
|
|
|
|
|
|
|
result = BitConverter.Int64BitsToDouble(
|
|
|
|
(long)((sign ? 1ul : 0ul) << 63 | (resultExp & 0x7FFul) << 52 | (fraction & 0x000FFFFFFFFFFFFFul)));
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPRecipStepFused(double value1, double value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPNeg();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context);
|
|
|
|
|
|
|
|
double result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
|
|
|
|
bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
|
|
|
|
|
|
|
|
if ((inf1 && zero2) || (zero1 && inf2))
|
|
|
|
{
|
|
|
|
result = FPTwo(false);
|
|
|
|
}
|
|
|
|
else if (inf1 || inf2)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign1 ^ sign2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2019-10-31 12:09:03 -06:00
|
|
|
result = Math.FusedMultiplyAdd(value1, value2, 2d);
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 12:56:22 -06:00
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && double.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0d);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPRecpX(double value)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value.FPUnpack(out FPType type, out bool sign, out ulong op, context);
|
|
|
|
|
|
|
|
double result;
|
|
|
|
|
|
|
|
if (type == FPType.SNaN || type == FPType.QNaN)
|
|
|
|
{
|
|
|
|
result = FPProcessNaN(type, op, context);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
ulong notExp = (~op >> 52) & 0x7FFul;
|
|
|
|
ulong maxExp = 0x7FEul;
|
|
|
|
|
|
|
|
result = BitConverter.Int64BitsToDouble(
|
|
|
|
(long)((sign ? 1ul : 0ul) << 63 | (notExp == 0x7FFul ? maxExp : notExp) << 52));
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPRSqrtEstimate(double value)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value.FPUnpack(out FPType type, out bool sign, out ulong op, context);
|
|
|
|
|
|
|
|
double result;
|
|
|
|
|
|
|
|
if (type == FPType.SNaN || type == FPType.QNaN)
|
|
|
|
{
|
|
|
|
result = FPProcessNaN(type, op, context);
|
|
|
|
}
|
|
|
|
else if (type == FPType.Zero)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign);
|
|
|
|
|
|
|
|
FPProcessException(FPException.DivideByZero, context);
|
|
|
|
}
|
|
|
|
else if (sign)
|
|
|
|
{
|
|
|
|
result = FPDefaultNaN();
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else if (type == FPType.Infinity)
|
|
|
|
{
|
|
|
|
result = FPZero(false);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
ulong fraction = op & 0x000FFFFFFFFFFFFFul;
|
|
|
|
uint exp = (uint)((op & 0x7FF0000000000000ul) >> 52);
|
|
|
|
|
|
|
|
if (exp == 0u)
|
|
|
|
{
|
|
|
|
while ((fraction & 0x0008000000000000ul) == 0ul)
|
|
|
|
{
|
|
|
|
fraction = (fraction & 0x0007FFFFFFFFFFFFul) << 1;
|
|
|
|
exp -= 1u;
|
|
|
|
}
|
|
|
|
|
|
|
|
fraction = (fraction & 0x0007FFFFFFFFFFFFul) << 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint scaled;
|
|
|
|
|
|
|
|
if ((exp & 1u) == 0u)
|
|
|
|
{
|
|
|
|
scaled = (uint)(((fraction & 0x000FF00000000000ul) | 0x0010000000000000ul) >> 44);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
scaled = (uint)(((fraction & 0x000FE00000000000ul) | 0x0010000000000000ul) >> 45);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint resultExp = (3068u - exp) >> 1;
|
|
|
|
|
|
|
|
uint estimate = (uint)SoftFloat.RecipSqrtEstimateTable[scaled - 128u] + 256u;
|
|
|
|
|
|
|
|
result = BitConverter.Int64BitsToDouble((long)((resultExp & 0x7FFul) << 52 | (estimate & 0xFFul) << 44));
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPRSqrtStepFused(double value1, double value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPNeg();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context);
|
|
|
|
|
|
|
|
double result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
|
|
|
|
bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
|
|
|
|
|
|
|
|
if ((inf1 && zero2) || (zero1 && inf2))
|
|
|
|
{
|
|
|
|
result = FPOnePointFive(false);
|
|
|
|
}
|
|
|
|
else if (inf1 || inf2)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign1 ^ sign2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2019-10-31 12:09:03 -06:00
|
|
|
result = Math.FusedMultiplyAdd(value1, value2, 3d) / 2d;
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 12:56:22 -06:00
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && double.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0d);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPSqrt(double value)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value = value.FPUnpack(out FPType type, out bool sign, out ulong op, context);
|
|
|
|
|
|
|
|
double result;
|
|
|
|
|
|
|
|
if (type == FPType.SNaN || type == FPType.QNaN)
|
|
|
|
{
|
|
|
|
result = FPProcessNaN(type, op, context);
|
|
|
|
}
|
|
|
|
else if (type == FPType.Zero)
|
|
|
|
{
|
|
|
|
result = FPZero(sign);
|
|
|
|
}
|
|
|
|
else if (type == FPType.Infinity && !sign)
|
|
|
|
{
|
|
|
|
result = FPInfinity(sign);
|
|
|
|
}
|
|
|
|
else if (sign)
|
|
|
|
{
|
|
|
|
result = FPDefaultNaN();
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = Math.Sqrt(value);
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && double.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0d);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
public static double FPSub(double value1, double value2)
|
|
|
|
{
|
|
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
|
|
|
|
value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context);
|
|
|
|
value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context);
|
|
|
|
|
|
|
|
double result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context);
|
|
|
|
|
|
|
|
if (!done)
|
|
|
|
{
|
|
|
|
bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
|
|
|
|
bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
|
|
|
|
|
|
|
|
if (inf1 && inf2 && sign1 == sign2)
|
|
|
|
{
|
|
|
|
result = FPDefaultNaN();
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
else if ((inf1 && !sign1) || (inf2 && sign2))
|
|
|
|
{
|
|
|
|
result = FPInfinity(false);
|
|
|
|
}
|
|
|
|
else if ((inf1 && sign1) || (inf2 && !sign2))
|
|
|
|
{
|
|
|
|
result = FPInfinity(true);
|
|
|
|
}
|
|
|
|
else if (zero1 && zero2 && sign1 == !sign2)
|
|
|
|
{
|
|
|
|
result = FPZero(sign1);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
result = value1 - value2;
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Fz) != 0 && double.IsSubnormal(result))
|
|
|
|
{
|
|
|
|
context.Fpsr |= FPSR.Ufc;
|
|
|
|
|
|
|
|
result = FPZero(result < 0d);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static double FPDefaultNaN()
|
|
|
|
{
|
|
|
|
return -double.NaN;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static double FPInfinity(bool sign)
|
|
|
|
{
|
|
|
|
return sign ? double.NegativeInfinity : double.PositiveInfinity;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static double FPZero(bool sign)
|
|
|
|
{
|
|
|
|
return sign ? -0d : +0d;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static double FPMaxNormal(bool sign)
|
|
|
|
{
|
|
|
|
return sign ? double.MinValue : double.MaxValue;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static double FPTwo(bool sign)
|
|
|
|
{
|
|
|
|
return sign ? -2d : +2d;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static double FPOnePointFive(bool sign)
|
|
|
|
{
|
|
|
|
return sign ? -1.5d : +1.5d;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static double FPNeg(this double value)
|
|
|
|
{
|
|
|
|
return -value;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static double ZerosOrOnes(bool ones)
|
|
|
|
{
|
|
|
|
return BitConverter.Int64BitsToDouble(ones ? -1L : 0L);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static double FPUnpack(
|
|
|
|
this double value,
|
|
|
|
out FPType type,
|
|
|
|
out bool sign,
|
|
|
|
out ulong valueBits,
|
|
|
|
ExecutionContext context)
|
|
|
|
{
|
|
|
|
valueBits = (ulong)BitConverter.DoubleToInt64Bits(value);
|
|
|
|
|
|
|
|
sign = (~valueBits & 0x8000000000000000ul) == 0ul;
|
|
|
|
|
|
|
|
if ((valueBits & 0x7FF0000000000000ul) == 0ul)
|
|
|
|
{
|
|
|
|
if ((valueBits & 0x000FFFFFFFFFFFFFul) == 0ul || (context.Fpcr & FPCR.Fz) != 0)
|
|
|
|
{
|
|
|
|
type = FPType.Zero;
|
|
|
|
value = FPZero(sign);
|
|
|
|
|
|
|
|
if ((valueBits & 0x000FFFFFFFFFFFFFul) != 0ul)
|
|
|
|
{
|
|
|
|
FPProcessException(FPException.InputDenorm, context);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
type = FPType.Nonzero;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else if ((~valueBits & 0x7FF0000000000000ul) == 0ul)
|
|
|
|
{
|
|
|
|
if ((valueBits & 0x000FFFFFFFFFFFFFul) == 0ul)
|
|
|
|
{
|
|
|
|
type = FPType.Infinity;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
type = (~valueBits & 0x0008000000000000ul) == 0ul ? FPType.QNaN : FPType.SNaN;
|
|
|
|
value = FPZero(sign);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
type = FPType.Nonzero;
|
|
|
|
}
|
|
|
|
|
|
|
|
return value;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static double FPProcessNaNs(
|
|
|
|
FPType type1,
|
|
|
|
FPType type2,
|
|
|
|
ulong op1,
|
|
|
|
ulong op2,
|
|
|
|
out bool done,
|
|
|
|
ExecutionContext context)
|
|
|
|
{
|
|
|
|
done = true;
|
|
|
|
|
|
|
|
if (type1 == FPType.SNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type1, op1, context);
|
|
|
|
}
|
|
|
|
else if (type2 == FPType.SNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type2, op2, context);
|
|
|
|
}
|
|
|
|
else if (type1 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type1, op1, context);
|
|
|
|
}
|
|
|
|
else if (type2 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type2, op2, context);
|
|
|
|
}
|
|
|
|
|
|
|
|
done = false;
|
|
|
|
|
|
|
|
return FPZero(false);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static double FPProcessNaNs3(
|
|
|
|
FPType type1,
|
|
|
|
FPType type2,
|
|
|
|
FPType type3,
|
|
|
|
ulong op1,
|
|
|
|
ulong op2,
|
|
|
|
ulong op3,
|
|
|
|
out bool done,
|
|
|
|
ExecutionContext context)
|
|
|
|
{
|
|
|
|
done = true;
|
|
|
|
|
|
|
|
if (type1 == FPType.SNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type1, op1, context);
|
|
|
|
}
|
|
|
|
else if (type2 == FPType.SNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type2, op2, context);
|
|
|
|
}
|
|
|
|
else if (type3 == FPType.SNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type3, op3, context);
|
|
|
|
}
|
|
|
|
else if (type1 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type1, op1, context);
|
|
|
|
}
|
|
|
|
else if (type2 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type2, op2, context);
|
|
|
|
}
|
|
|
|
else if (type3 == FPType.QNaN)
|
|
|
|
{
|
|
|
|
return FPProcessNaN(type3, op3, context);
|
|
|
|
}
|
|
|
|
|
|
|
|
done = false;
|
|
|
|
|
|
|
|
return FPZero(false);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static double FPProcessNaN(FPType type, ulong op, ExecutionContext context)
|
|
|
|
{
|
|
|
|
if (type == FPType.SNaN)
|
|
|
|
{
|
|
|
|
op |= 1ul << 51;
|
|
|
|
|
|
|
|
FPProcessException(FPException.InvalidOp, context);
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((context.Fpcr & FPCR.Dn) != 0)
|
|
|
|
{
|
|
|
|
return FPDefaultNaN();
|
|
|
|
}
|
|
|
|
|
|
|
|
return BitConverter.Int64BitsToDouble((long)op);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void FPProcessException(FPException exc, ExecutionContext context)
|
|
|
|
{
|
|
|
|
int enable = (int)exc + 8;
|
|
|
|
|
|
|
|
if ((context.Fpcr & (FPCR)(1 << enable)) != 0)
|
|
|
|
{
|
|
|
|
throw new NotImplementedException("Floating-point trap handling.");
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
context.Fpsr |= (FPSR)(1 << (int)exc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|