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https://github.com/Ryujinx-NX/Ryujinx.git
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Implement CSDB instruction (#2927)
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267b248c13
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@ -661,6 +661,7 @@ namespace ARMeilleure.Decoders
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SetA32("<<<<00010100xxxxxxxx00100100xxxx", InstName.Crc32cw, InstEmit32.Crc32cw, OpCode32AluReg.Create);
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SetA32("<<<<00010010xxxxxxxx00000100xxxx", InstName.Crc32h, InstEmit32.Crc32h, OpCode32AluReg.Create);
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SetA32("<<<<00010100xxxxxxxx00000100xxxx", InstName.Crc32w, InstEmit32.Crc32w, OpCode32AluReg.Create);
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SetA32("<<<<0011001000001111000000010100", InstName.Csdb, InstEmit32.Csdb, OpCode32.Create);
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SetA32("1111010101111111111100000101xxxx", InstName.Dmb, InstEmit32.Dmb, OpCode32.Create);
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SetA32("1111010101111111111100000100xxxx", InstName.Dsb, InstEmit32.Dsb, OpCode32.Create);
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SetA32("<<<<0010001xxxxxxxxxxxxxxxxxxxxx", InstName.Eor, InstEmit32.Eor, OpCode32AluImm.Create);
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@ -16,6 +16,11 @@ namespace ARMeilleure.Instructions
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EmitClearExclusive(context);
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}
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public static void Csdb(ArmEmitterContext context)
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{
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// Execute as no-op.
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}
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public static void Dmb(ArmEmitterContext context) => EmitBarrier(context);
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public static void Dsb(ArmEmitterContext context) => EmitBarrier(context);
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@ -99,7 +99,7 @@ namespace ARMeilleure.Instructions
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EmitLoadSimd(context, address, GetVecA32(dreg >> 1), dreg >> 1, rIndex++, op.Size);
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}
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}
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}
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}
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else
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{
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EmitLoadSimd(context, address, GetVecA32(d >> 1), d >> 1, index, op.Size);
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@ -120,13 +120,13 @@ namespace ARMeilleure.Instructions
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{
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Operand m = GetIntA32(context, op.Rm);
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SetIntA32(context, op.Rn, context.Add(n, m));
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}
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}
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else
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{
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SetIntA32(context, op.Rn, context.Add(n, Const(count * eBytes)));
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}
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}
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}
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}
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else
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{
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OpCode32SimdMemPair op = (OpCode32SimdMemPair)context.CurrOp;
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@ -161,7 +161,7 @@ namespace ARMeilleure.Instructions
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}
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else
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{
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if (load)
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{
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EmitLoadSimd(context, address, GetVecA32(elemD >> 1), elemD >> 1, index, op.Size);
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@ -213,7 +213,7 @@ namespace ARMeilleure.Instructions
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int sReg = (op.DoubleWidth) ? (op.Vd << 1) : op.Vd;
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int offset = 0;
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int byteSize = 4;
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for (int num = 0; num < range; num++, sReg++)
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{
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Operand address = context.Add(baseAddress, Const(offset));
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@ -36,6 +36,7 @@ namespace ARMeilleure.Instructions
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Crc32ch,
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Crc32cw,
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Crc32cx,
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Csdb,
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Csel,
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Csinc,
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Csinv,
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