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DSPLLE: sort of semi-working breakpoints and stepping, if you flip an #ifdef. more work to do, for some reason it gets very slow when you enable it atm

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git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3573 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
hrydgard
2009-06-28 16:23:40 +00:00
parent b406203794
commit 04105baf4e
19 changed files with 841 additions and 774 deletions
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60
Source/Core/DSPCore/Src/DSPCore.cpp
View File

@ -24,7 +24,9 @@
====================================================================*/
#include "Common.h"
#include "Thread.h"
#include "DSPCore.h"
#include "DSPHost.h"
#include "DSPAnalyzer.h"
#include "MemoryUtil.h"
@ -33,6 +35,8 @@
SDSP g_dsp;
BreakPoints dsp_breakpoints;
DSPCoreState core_state = DSPCORE_RUNNING;
Common::Event step_event;
static bool LoadRom(const char *fname, int size_in_words, u16 *rom)
{
@ -118,11 +122,13 @@ bool DSPCore_Init(const char *irom_filename, const char *coef_filename)
WriteProtectMemory(g_dsp.iram, DSP_IRAM_BYTE_SIZE, false);
DSPAnalyzer::Analyze();
step_event.Init();
return true;
}
void DSPCore_Shutdown()
{
step_event.Shutdown();
FreeMemoryPages(g_dsp.irom, DSP_IROM_BYTE_SIZE);
FreeMemoryPages(g_dsp.iram, DSP_IRAM_BYTE_SIZE);
FreeMemoryPages(g_dsp.dram, DSP_DRAM_BYTE_SIZE);
@ -184,3 +190,57 @@ void DSPCore_CheckExceptions()
}
}
}
// Delegate to JIT (when it is written) or interpreter as appropriate.
// Handle state changes and stepping.
int DSPCore_RunCycles(int cycles)
{
while (cycles > 0) {
reswitch:
switch (core_state)
{
case DSPCORE_RUNNING:
#if 0 // Set to 1 to enable stepping
// Enable breakpoints
cycles = DSPInterpreter::RunCyclesDebug(cycles);
#else
//1: enter a fast runloop
cycles = DSPInterpreter::RunCycles(cycles);
#endif
break;
case DSPCORE_STEPPING:
step_event.Wait();
if (core_state != DSPCORE_STEPPING)
goto reswitch;
DSPInterpreter::Step();
cycles--;
DSPHost_UpdateDebugger();
break;
}
}
return cycles;
}
void DSPCore_SetState(DSPCoreState new_state)
{
core_state = new_state;
// kick the event, in case we are waiting
if (new_state == DSPCORE_RUNNING)
step_event.Set();
// Sleep(10);
DSPHost_UpdateDebugger();
}
DSPCoreState DSPCore_GetState()
{
return core_state;
}
void DSPCore_Step()
{
if (core_state == DSPCORE_STEPPING)
step_event.Set();
}

53
Source/Core/DSPCore/Src/DSPCore.h
View File

@ -101,17 +101,35 @@
// Hardware registers address
#define DSP_REG_DSCR 0xffc9 // DSP DMA Control Reg
#define DSP_REG_DSBL 0xffcb // DSP DMA Block Length
#define DSP_REG_DSPA 0xffcd // DSP DMA DMEM Address
#define DSP_REG_DSMAH 0xffce // DSP DMA Mem Address H
#define DSP_REG_DSMAL 0xffcf // DSP DMA Mem Address L
#define DSP_COEF_A1_0 0xa0
#define DSP_REG_DIRQ 0xfffb // DSP Irq Rest
#define DSP_REG_DMBH 0xfffc // DSP Mailbox H
#define DSP_REG_DMBL 0xfffd // DSP Mailbox L
#define DSP_REG_CMBH 0xfffe // CPU Mailbox H
#define DSP_REG_CMBL 0xffff // CPU Mailbox L
#define DSP_DSMAH 0xce
#define DSP_DSMAL 0xcf
#define DSP_DSCR 0xc9 // DSP DMA Control Reg
#define DSP_DSPA 0xcd // DSP DMA Block Length
#define DSP_DSBL 0xcb // DSP DMA DMEM Address
#define DSP_DSMAH 0xce // DSP DMA Mem Address H
#define DSP_DSMAL 0xcf // DSP DMA Mem Address L
#define DSP_FORMAT 0xd1
#define DSP_ACDATA1 0xd3 // used only by Zelda ucodes
#define DSP_ACSAH 0xd4
#define DSP_ACSAL 0xd5
#define DSP_ACEAH 0xd6
#define DSP_ACEAL 0xd7
#define DSP_ACCAH 0xd8
#define DSP_ACCAL 0xd9
#define DSP_PRED_SCALE 0xda
#define DSP_YN1 0xdb
#define DSP_YN2 0xdc
#define DSP_ACCELERATOR 0xdd // ADPCM accelerator read. Used by AX.
#define DSP_GAIN 0xde
#define DSP_DIRQ 0xfb // DSP Irq Rest
#define DSP_DMBH 0xfc // DSP Mailbox H
#define DSP_DMBL 0xfd // DSP Mailbox L
#define DSP_CMBH 0xfe // CPU Mailbox H
#define DSP_CMBL 0xff // CPU Mailbox L
#define DMA_TO_DSP 0
#define DMA_TO_CPU 1
@ -125,6 +143,7 @@
#define CR_HALT 0x0004
#define CR_EXTERNAL_INT 0x0002
// SR bits
#define SR_CARRY 0x0001
#define SR_2 0x0002 // overflow???
@ -194,4 +213,18 @@ void DSPCore_CheckExceptions();
// sets a flag in the pending exception register.
void DSPCore_SetException(u8 level);
enum DSPCoreState
{
DSPCORE_RUNNING = 0,
DSPCORE_STEPPING = 1,
};
int DSPCore_RunCycles(int cycles);
// These are meant to be called from the UI thread.
void DSPCore_SetState(DSPCoreState new_state);
DSPCoreState DSPCore_GetState();
void DSPCore_Step();
#endif // _DSPCORE_H

6
Source/Core/DSPCore/Src/DSPHWInterface.cpp
View File

@ -36,7 +36,7 @@
#include "DSPInterpreter.h"
#include "DSPHWInterface.h"
void gdsp_dma();
void gdsp_do_dma();
Common::CriticalSection g_CriticalSection;
@ -137,7 +137,7 @@ void gdsp_ifx_write(u16 addr, u16 val)
case 0xcb: // DSBL
gdsp_ifx_regs[addr & 0xFF] = val;
gdsp_dma();
gdsp_do_dma();
gdsp_ifx_regs[DSP_DSCR] &= ~0x0004;
break;
@ -274,7 +274,7 @@ void gdsp_ddma_out(u16 dsp_addr, u32 addr, u32 size)
INFO_LOG(DSPLLE, "*** ddma_out DRAM_DSP (0x%04x) -> RAM (0x%08x) : size (0x%08x)\n", dsp_addr / 2, addr, size);
}
void gdsp_dma()
void gdsp_do_dma()
{
u16 ctl;
u32 addr;

20
Source/Core/DSPCore/Src/DSPHWInterface.h
View File

@ -30,26 +30,6 @@
#define GDSP_MBOX_CPU 0
#define GDSP_MBOX_DSP 1
#define DSP_DSMAH 0xce
#define DSP_DSMAL 0xcf
#define DSP_DSCR 0xc9
#define DSP_DSPA 0xcd
#define DSP_DSBL 0xcb
#define DSP_ACSAH 0xd4
#define DSP_ACSAL 0xd5
#define DSP_ACEAH 0xd6
#define DSP_ACEAL 0xd7
#define DSP_ACCAH 0xd8
#define DSP_ACCAL 0xd9
#define DSP_COEF_A1_0 0xa0
#define DSP_FORMAT 0xd1
#define DSP_PRED_SCALE 0xda
#define DSP_YN1 0xdb
#define DSP_YN2 0xdc
#define DSP_ARAM 0xdd
#define DSP_GAIN 0xde
extern u16 gdsp_ifx_regs[256];
u32 gdsp_mbox_peek(u8 mbx);

1
Source/Core/DSPCore/Src/DSPHost.h
View File

@ -29,5 +29,6 @@ bool DSPHost_OnThread();
bool DSPHost_Running();
void DSPHost_InterruptRequest();
u32 DSPHost_CodeLoaded(const u8 *ptr, int size);
void DSPHost_UpdateDebugger();
#endif

81
Source/Core/DSPCore/Src/DSPIntCCUtil.cpp
View File

@ -32,12 +32,12 @@ void Update_SR_Register64(s64 _Value)
if (_Value < 0)
{
g_dsp.r[DSP_REG_SR] |= 0x8;
g_dsp.r[DSP_REG_SR] |= SR_SIGN;
}
if (_Value == 0)
{
g_dsp.r[DSP_REG_SR] |= 0x4;
g_dsp.r[DSP_REG_SR] |= SR_ARITH_ZERO;
}
// weird
@ -53,12 +53,12 @@ void Update_SR_Register16(s16 _Value)
if (_Value < 0)
{
g_dsp.r[DSP_REG_SR] |= 0x8;
g_dsp.r[DSP_REG_SR] |= SR_SIGN;
}
if (_Value == 0)
{
g_dsp.r[DSP_REG_SR] |= 0x4;
g_dsp.r[DSP_REG_SR] |= SR_ARITH_ZERO;
}
// weird
@ -90,92 +90,51 @@ int GetMultiplyModifier()
}
inline bool isCarry() {
return (g_dsp.r[DSP_REG_SR] & 0x01) ? true : false;
return (g_dsp.r[DSP_REG_SR] & SR_CARRY) ? true : false;
}
inline bool isSign() {
return ((g_dsp.r[DSP_REG_SR] & 0x02) != (g_dsp.r[DSP_REG_SR] & 0x08));
return ((g_dsp.r[DSP_REG_SR] & SR_2) != (g_dsp.r[DSP_REG_SR] & SR_SIGN));
}
inline bool isZero() {
return (g_dsp.r[DSP_REG_SR] & 0x04) ? true : false;
return (g_dsp.r[DSP_REG_SR] & SR_ARITH_ZERO) ? true : false;
}
//see gdsp_registers.h for flags
bool CheckCondition(u8 _Condition)
{
bool taken = false;
switch (_Condition & 0xf)
{
case 0x0: //NS - NOT SIGN
if (! isSign())
taken = true;
break;
return !isSign();
case 0x1: // S - SIGN
if (isSign())
taken = true;
break;
return isSign();
case 0x2: // G - GREATER
if (! isSign() && !isZero())
taken = true;
break;
return !isSign() && !isZero();
case 0x3: // LE - LESS EQUAL
if (isSign() || isZero())
taken = true;
break;
return isSign() || isZero();
case 0x4: // NZ - NOT ZERO
if (!isZero())
taken = true;
break;
return !isZero();
case 0x5: // Z - ZERO
if (isZero())
taken = true;
break;
return isZero();
case 0x6: // L - LESS
// Should be that once we set 0x01
if (!isCarry())
return !isCarry();
// if (isSign())
taken = true;
break;
case 0x7: // GE - GREATER EQUAL
// Should be that once we set 0x01
if (isCarry())
return isCarry();
// if (! isSign() || isZero())
taken = true;
break;
case 0xc: // LNZ - LOGIC NOT ZERO
if (!(g_dsp.r[DSP_REG_SR] & SR_LOGIC_ZERO))
taken = true;
break;
return !(g_dsp.r[DSP_REG_SR] & SR_LOGIC_ZERO);
case 0xd: // LZ - LOGIC ZERO
return (g_dsp.r[DSP_REG_SR] & SR_LOGIC_ZERO) != 0;
if (g_dsp.r[DSP_REG_SR] & SR_LOGIC_ZERO)
taken = true;
break;
case 0xf: // Empty
taken = true;
break;
case 0xf: // Empty - always true.
return true;
default:
ERROR_LOG(DSPLLE, "Unknown condition check: 0x%04x\n", _Condition & 0xf);
break;
return false;
}
return taken;
}
} // namespace

1
Source/Core/DSPCore/Src/DSPIntUtil.h
View File

@ -32,7 +32,6 @@
#include "DSPCore.h"
#include "DSPMemoryMap.h"
#include "DSPStacks.h"
// #include "DSPIntExtOps.h"
// ---------------------------------------------------------------------------------------
// --- SR

54
Source/Core/DSPCore/Src/DSPInterpreter.cpp
View File

@ -71,8 +71,6 @@ u16 ReadCR()
return g_dsp.cr;
}
void HandleLoop()
{
// Handle looping hardware.
@ -85,6 +83,7 @@ void HandleLoop()
// This does not always work correctly!
// The loop end tends to point to the second part of
// two-byte instructions!
// 0179 1104 019f bloopi #0x04, 0x019f in zelda, for example
if (g_dsp.pc == (rLoopAddress + 1))
{
rLoopCounter--;
@ -150,31 +149,62 @@ void Run()
gdsp_running = false;
}
// Used by non-thread mode.
void RunCycles(int cycles)
// This one has basic idle skipping, and checks breakpoints.
int RunCyclesDebug(int cycles)
{
// First, let's run a few cycles with no idle skipping so that things can progress a bit.
for (int i = 0; i < 8; i++)
{
if (g_dsp.cr & CR_HALT)
return 0;
Step();
cycles--;
}
while (cycles > 0)
{
if (g_dsp.cr & CR_HALT) {
return 0;
}
if (dsp_breakpoints.IsAddressBreakPoint(g_dsp.pc))
{
DSPCore_SetState(DSPCORE_STEPPING);
return cycles;
}
DSPCore_CheckExternalInterrupt();
Step();
cycles--;
// Idle skipping.
if (DSPAnalyzer::code_flags[g_dsp.pc] & DSPAnalyzer::CODE_IDLE_SKIP)
return 0;
}
}
// Used by non-thread mode. Meant to be efficient.
int RunCycles(int cycles)
{
if (cycles < 18)
{
for (int i = 0; i < cycles; i++)
{
if (g_dsp.cr & CR_HALT)
return;
return 0;
if (DSPAnalyzer::code_flags[g_dsp.pc] & DSPAnalyzer::CODE_IDLE_SKIP)
return;
return 0;
Step();
cycles--;
}
return;
return cycles;
}
DSPCore_CheckExternalInterrupt();
// First, let's run a few cycles with no idle skipping so that things can progress a bit.
for (int i = 0; i < 8; i++)
{
if (g_dsp.cr & CR_HALT)
return;
return 0;
Step();
cycles--;
}
@ -183,9 +213,9 @@ void RunCycles(int cycles)
for (int i = 0; i < 8; i++)
{
if (g_dsp.cr & CR_HALT)
return;
return 0;
if (DSPAnalyzer::code_flags[g_dsp.pc] & DSPAnalyzer::CODE_IDLE_SKIP)
return;
return 0;
Step();
cycles--;
}
@ -199,6 +229,8 @@ void RunCycles(int cycles)
// We don't bother directly supporting pause - if the main emu pauses,
// it just won't call this function anymore.
}
return cycles;
}
void Stop()

8
Source/Core/DSPCore/Src/DSPInterpreter.h
View File

@ -27,7 +27,13 @@ namespace DSPInterpreter {
void Step();
void Run();
void RunCycles(int cycles);
// If these simply return the same number of cycles as was passed into them,
// chances are that the DSP is halted.
// The difference between them is that the debug one obeys breakpoints.
int RunCycles(int cycles);
int RunCyclesDebug(int cycles);
void Stop();
void WriteCR(u16 val);

8
Source/Core/DSPCore/Src/DSPStacks.cpp
View File

@ -30,27 +30,27 @@
// Stacks. The stacks are outside the DSP RAM, in dedicated hardware.
void dsp_reg_stack_push(u8 stack_reg)
void dsp_reg_stack_push(int stack_reg)
{
g_dsp.reg_stack_ptr[stack_reg]++;
g_dsp.reg_stack_ptr[stack_reg] &= DSP_STACK_MASK;
g_dsp.reg_stack[stack_reg][g_dsp.reg_stack_ptr[stack_reg]] = g_dsp.r[DSP_REG_ST0 + stack_reg];
}
void dsp_reg_stack_pop(u8 stack_reg)
void dsp_reg_stack_pop(int stack_reg)
{
g_dsp.r[DSP_REG_ST0 + stack_reg] = g_dsp.reg_stack[stack_reg][g_dsp.reg_stack_ptr[stack_reg]];
g_dsp.reg_stack_ptr[stack_reg]--;
g_dsp.reg_stack_ptr[stack_reg] &= DSP_STACK_MASK;
}
void dsp_reg_store_stack(u8 stack_reg, u16 val)
void dsp_reg_store_stack(int stack_reg, u16 val)
{
dsp_reg_stack_push(stack_reg);
g_dsp.r[DSP_REG_ST0 + stack_reg] = val;
}
u16 dsp_reg_load_stack(u8 stack_reg)
u16 dsp_reg_load_stack(int stack_reg)
{
u16 val = g_dsp.r[DSP_REG_ST0 + stack_reg];
dsp_reg_stack_pop(stack_reg);

4
Source/Core/DSPCore/Src/DSPStacks.h
View File

@ -28,7 +28,7 @@
#include "Common.h"
void dsp_reg_store_stack(u8 stack_reg, u16 val);
u16 dsp_reg_load_stack(u8 stack_reg);
void dsp_reg_store_stack(int stack_reg, u16 val);
u16 dsp_reg_load_stack(int stack_reg);
#endif

8
Source/Core/DSPCore/Src/DSPTables.cpp
View File

@ -252,8 +252,7 @@ const DSPOPCTemplate opcodes[] =
{"CLRL", 0xfc00, 0xffff, DSPInterpreter::clrl, nop, 1 | P_EXT, 1, {{P_ACCL, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acl0
{"CLR", 0x8100, 0xf7ff, DSPInterpreter::clr, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acc0
{"CLRP", 0x8400, 0xffff, DSPInterpreter::clrp, nop, 1 | P_EXT, 0, {}, },
{"MOV", 0x6c00, 0xfeff, DSPInterpreter::mov, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"MOVAX", 0x6800, 0xfcff, DSPInterpreter::movax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"MOVR", 0x6000, 0xf8ff, DSPInterpreter::movr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
@ -368,6 +367,7 @@ const pdlabel_t pdlabels[] =
{0xffad, "COEF_A2_6", "COEF_A2_6",},
{0xffae, "COEF_A1_7", "COEF_A1_7",},
{0xffaf, "COEF_A2_7", "COEF_A2_7",},
{0xffb0, 0, 0,},
{0xffb1, 0, 0,},
{0xffb2, 0, 0,},
@ -384,6 +384,7 @@ const pdlabel_t pdlabels[] =
{0xffbd, 0, 0,},
{0xffbe, 0, 0,},
{0xffbf, 0, 0,},
{0xffc0, 0, 0,},
{0xffc1, 0, 0,},
{0xffc2, 0, 0,},
@ -400,6 +401,7 @@ const pdlabel_t pdlabels[] =
{0xffcd, "DSPA", "DSP DMA DMEM Address",},
{0xffce, "DSMAH", "DSP DMA Mem Address H",},
{0xffcf, "DSMAL", "DSP DMA Mem Address L",},
{0xffd0, 0,0,},
{0xffd1, "SampleFormat", "SampleFormat",},
{0xffd2, 0,0,},
@ -416,6 +418,7 @@ const pdlabel_t pdlabels[] =
{0xffdd, "ARAM", "Direct Read from ARAM (uses ADPCM)",},
{0xffde, "GAIN", "Gain",},
{0xffdf, 0,0,},
{0xffe0, 0,0,},
{0xffe1, 0,0,},
{0xffe2, 0,0,},
@ -432,6 +435,7 @@ const pdlabel_t pdlabels[] =
{0xffed, 0,0,},
{0xffee, 0,0,},
{0xffef, "AMDM", "ARAM DMA Request Mask",},
{0xfff0, 0,0,},
{0xfff1, 0,0,},
{0xfff2, 0,0,},