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Rename accelerator accesses to 'raw' and 'sample'

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This commit is contained in:
xperia64
2022-06-18 16:46:51 -04:00
committed by Tillmann Karras
parent 256d9f8702
commit 04c7c1a4a1
6 changed files with 24 additions and 24 deletions
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14
Source/Core/Core/DSP/DSPAccelerator.cpp
View File

@ -11,7 +11,7 @@
namespace DSP namespace DSP
{ {
u16 Accelerator::ReadD3() u16 Accelerator::ReadRaw()
{ {
u16 val = 0; u16 val = 0;
@ -35,7 +35,7 @@ u16 Accelerator::ReadD3()
m_current_address++; m_current_address++;
break; break;
case 0x3: // produces garbage, but affects the current address case 0x3: // produces garbage, but affects the current address
ERROR_LOG_FMT(DSPLLE, "dsp_read_aram_d3() - bad format {:#x}", m_sample_format); ERROR_LOG_FMT(DSPLLE, "dsp_read_aram_raw() - bad format {:#x}", m_sample_format);
m_current_address = (m_current_address & ~3) | ((m_current_address + 1) & 3); m_current_address = (m_current_address & ~3) | ((m_current_address + 1) & 3);
break; break;
} }
@ -79,7 +79,7 @@ u16 Accelerator::ReadD3()
return val; return val;
} }
void Accelerator::WriteD3(u16 value) void Accelerator::WriteRaw(u16 value)
{ {
// Zelda ucode writes a bunch of zeros to ARAM through d3 during // Zelda ucode writes a bunch of zeros to ARAM through d3 during
// initialization. Don't know if it ever does it later, too. // initialization. Don't know if it ever does it later, too.
@ -89,7 +89,7 @@ void Accelerator::WriteD3(u16 value)
// Writes only seem to be accepted when the upper most bit of the address is set // Writes only seem to be accepted when the upper most bit of the address is set
if (m_current_address & 0x80000000) if (m_current_address & 0x80000000)
{ {
// The format doesn't matter for D3 writes, all writes are u16 and the address is treated as if // The format doesn't matter for raw writes, all writes are u16 and the address is treated as if
// we are in a 16-bit format // we are in a 16-bit format
WriteMemory(m_current_address * 2, value >> 8); WriteMemory(m_current_address * 2, value >> 8);
WriteMemory(m_current_address * 2 + 1, value & 0xFF); WriteMemory(m_current_address * 2 + 1, value & 0xFF);
@ -98,12 +98,12 @@ void Accelerator::WriteD3(u16 value)
else else
{ {
ERROR_LOG_FMT(DSPLLE, ERROR_LOG_FMT(DSPLLE,
"dsp_write_aram_d3() - tried to write to address {:#x} without high bit set", "dsp_write_aram_raw() - tried to write to address {:#x} without high bit set",
m_current_address); m_current_address);
} }
} }
u16 Accelerator::Read(const s16* coefs) u16 Accelerator::ReadSample(const s16* coefs)
{ {
if (m_reads_stopped) if (m_reads_stopped)
return 0x0000; return 0x0000;
@ -177,7 +177,7 @@ u16 Accelerator::Read(const s16* coefs)
m_current_address += 1; m_current_address += 1;
break; break;
default: default:
ERROR_LOG_FMT(DSPLLE, "dsp_read_accelerator() - unknown format {:#x}", m_sample_format); ERROR_LOG_FMT(DSPLLE, "dsp_read_accelerator_sample() - unknown format {:#x}", m_sample_format);
step_size_bytes = 2; step_size_bytes = 2;
m_current_address += 1; m_current_address += 1;
val = 0; val = 0;

6
Source/Core/Core/DSP/DSPAccelerator.h
View File

@ -14,10 +14,10 @@ class Accelerator
public: public:
virtual ~Accelerator() = default; virtual ~Accelerator() = default;
u16 Read(const s16* coefs); u16 ReadSample(const s16* coefs);
// Zelda ucode reads ARAM through 0xffd3. // Zelda ucode reads ARAM through 0xffd3.
u16 ReadD3(); u16 ReadRaw();
void WriteD3(u16 value); void WriteRaw(u16 value);
u32 GetStartAddress() const { return m_start_address; } u32 GetStartAddress() const { return m_start_address; }
u32 GetEndAddress() const { return m_end_address; } u32 GetEndAddress() const { return m_end_address; }

10
Source/Core/Core/DSP/DSPCore.h
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@ -152,10 +152,10 @@ enum : u32
DSP_DSMAH = 0xce, // DSP DMA Address High (External) DSP_DSMAH = 0xce, // DSP DMA Address High (External)
DSP_DSMAL = 0xcf, // DSP DMA Address Low (External) DSP_DSMAL = 0xcf, // DSP DMA Address Low (External)
DSP_FORMAT = 0xd1, // Sample format DSP_FORMAT = 0xd1, // Sample format
DSP_ACUNK = 0xd2, // Set to 3 on my dumps DSP_ACUNK = 0xd2, // Set to 3 on my dumps
DSP_ACDATA1 = 0xd3, // Used only by Zelda ucodes DSP_ACDRAW = 0xd3, // Raw accelerator accesses
DSP_ACSAH = 0xd4, // Start of loop DSP_ACSAH = 0xd4, // Start of loop
DSP_ACSAL = 0xd5, DSP_ACSAL = 0xd5,
DSP_ACEAH = 0xd6, // End of sample (and loop) DSP_ACEAH = 0xd6, // End of sample (and loop)
DSP_ACEAL = 0xd7, DSP_ACEAL = 0xd7,
@ -164,7 +164,7 @@ enum : u32
DSP_PRED_SCALE = 0xda, // ADPCM predictor and scale DSP_PRED_SCALE = 0xda, // ADPCM predictor and scale
DSP_YN1 = 0xdb, DSP_YN1 = 0xdb,
DSP_YN2 = 0xdc, DSP_YN2 = 0xdc,
DSP_ACCELERATOR = 0xdd, // ADPCM accelerator read. Used by AX. DSP_ACDSAMP = 0xdd, // Accelerator sample reads, processed differently depending on FORMAT
DSP_GAIN = 0xde, DSP_GAIN = 0xde,
DSP_ACUNK2 = 0xdf, // Set to 0xc on my dumps DSP_ACUNK2 = 0xdf, // Set to 0xc on my dumps

12
Source/Core/Core/DSP/DSPHWInterface.cpp
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@ -170,8 +170,8 @@ void SDSP::WriteIFX(u32 address, u16 value)
case DSP_PRED_SCALE: case DSP_PRED_SCALE:
m_accelerator->SetPredScale(value); m_accelerator->SetPredScale(value);
break; break;
case DSP_ACDATA1: // Accelerator write (Zelda type) - "UnkZelda" case DSP_ACDRAW: // Raw accelerator write
m_accelerator->WriteD3(value); m_accelerator->WriteRaw(value);
break; break;
default: default:
@ -237,10 +237,10 @@ u16 SDSP::ReadIFXImpl(u16 address)
return m_accelerator->GetYn2(); return m_accelerator->GetYn2();
case DSP_PRED_SCALE: case DSP_PRED_SCALE:
return m_accelerator->GetPredScale(); return m_accelerator->GetPredScale();
case DSP_ACCELERATOR: // ADPCM Accelerator reads case DSP_ACDSAMP: // Processed sample accelerator read
return m_accelerator->Read(reinterpret_cast<s16*>(&m_ifx_regs[DSP_COEF_A1_0])); return m_accelerator->ReadSample(reinterpret_cast<s16*>(&m_ifx_regs[DSP_COEF_A1_0]));
case DSP_ACDATA1: // Accelerator reads (Zelda type) - "UnkZelda" case DSP_ACDRAW: // Raw accelerator read
return m_accelerator->ReadD3(); return m_accelerator->ReadRaw();
default: default:
{ {

2
Source/Core/Core/HW/DSPHLE/UCodes/AXVoice.h
View File

@ -189,7 +189,7 @@ void AcceleratorSetup(HLEAccelerator* accelerator, PB_TYPE* pb)
// by the accelerator on real hardware). // by the accelerator on real hardware).
u16 AcceleratorGetSample(HLEAccelerator* accelerator) u16 AcceleratorGetSample(HLEAccelerator* accelerator)
{ {
return accelerator->Read(accelerator->acc_pb->adpcm.coefs); return accelerator->ReadSample(accelerator->acc_pb->adpcm.coefs);
} }
// Reads samples from the input callback, resamples them to <count> samples at // Reads samples from the input callback, resamples them to <count> samples at

4
docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex
View File

@ -695,7 +695,7 @@ Hardware registers (IFX) occupy the address space at \Address{0xFFxx} in the Dat
\multicolumn{3}{|l|}{\textit{Accelerator}} \\ \hline \multicolumn{3}{|l|}{\textit{Accelerator}} \\ \hline
\Address{0xFFD1} & \Register{FORMAT} & Accelerator sample format \\ \hline \Address{0xFFD1} & \Register{FORMAT} & Accelerator sample format \\ \hline
\Address{0xFFD2} & \Register{ACUNK1} & Unknown, usually 3 \\ \hline \Address{0xFFD2} & \Register{ACUNK1} & Unknown, usually 3 \\ \hline
\Address{0xFFD3} & \Register{ACDATA1} & Alternative ARAM interface \\ \hline \Address{0xFFD3} & \Register{ACDRAW} & Accelerator raw data \\ \hline
\Address{0xFFD4} & \Register{ACSAH} & Accelerator start address H \\ \hline \Address{0xFFD4} & \Register{ACSAH} & Accelerator start address H \\ \hline
\Address{0xFFD5} & \Register{ACSAL} & Accelerator start address L \\ \hline \Address{0xFFD5} & \Register{ACSAL} & Accelerator start address L \\ \hline
\Address{0xFFD6} & \Register{ACEAH} & Accelerator end address H \\ \hline \Address{0xFFD6} & \Register{ACEAH} & Accelerator end address H \\ \hline
@ -705,7 +705,7 @@ Hardware registers (IFX) occupy the address space at \Address{0xFFxx} in the Dat
\Address{0xFFDA} & \Register{SCALE} & ADPCM predictor and scale \\ \hline \Address{0xFFDA} & \Register{SCALE} & ADPCM predictor and scale \\ \hline
\Address{0xFFDB} & \Register{YN1} & ADPCM YN1 \\ \hline \Address{0xFFDB} & \Register{YN1} & ADPCM YN1 \\ \hline
\Address{0xFFDC} & \Register{YN2} & ADPCM YN2 \\ \hline \Address{0xFFDC} & \Register{YN2} & ADPCM YN2 \\ \hline
\Address{0xFFDD} & \Register{ACDAT} & Accelerator data \\ \hline \Address{0xFFDD} & \Register{ACDSAMP} & Accelerator processed sample \\ \hline
\Address{0xFFDE} & \Register{GAIN} & Gain \\ \hline \Address{0xFFDE} & \Register{GAIN} & Gain \\ \hline
\Address{0xFFDF} & \Register{ACUNK2} & Unknown, usually \Value{0x0C} \\ \hline \Address{0xFFDF} & \Register{ACUNK2} & Unknown, usually \Value{0x0C} \\ \hline
\Address{0xFFED} & \Register{AMDM} & ARAM DMA Request Mask \\ \hline \Address{0xFFED} & \Register{AMDM} & ARAM DMA Request Mask \\ \hline