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UnitTests: Fix misplaced braces in the x64Emitter tests
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@ -471,7 +471,7 @@ SHIFT_TEST(SAR)
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}; \
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for (const auto& regset : regsets) \
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for (const auto& r : regset.regs) \
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{ \
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{ \
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emitter->Name(regset.bits, R(r.reg), R(RAX)); \
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emitter->Name(regset.bits, R(RAX), R(r.reg)); \
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emitter->Name(regset.bits, R(r.reg), Imm8(0x42)); \
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@ -480,7 +480,7 @@ SHIFT_TEST(SAR)
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#Name " " + regset.out_name + ", " + r.name + " " \
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#Name " " + r.name + ", 0x42 " \
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#Name " " + regset.size + " ptr ds:[r12], " + r.name); \
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} \
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} \
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}
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BT_TEST(BT)
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@ -506,14 +506,14 @@ BT_TEST(BTC)
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}; \
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for (const auto& regset : regsets) \
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for (const auto& r : regset.regs) \
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{ \
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{ \
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emitter->Name(regset.bits, R(r.reg)); \
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emitter->Name(regset.bits, MatR(RAX)); \
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emitter->Name(regset.bits, MatR(R12)); \
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ExpectDisassembly(#Name " " + r.name + " " \
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#Name " " + regset.size + " ptr ds:[rax] " \
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#Name " " + regset.size + " ptr ds:[r12]"); \
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} \
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} \
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}
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ONE_OP_ARITH_TEST(NOT)
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@ -942,14 +942,14 @@ VEX_RM_TEST(BLSI)
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}; \
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for (const auto& regset : regsets) \
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for (const auto& r : regset.regs) \
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{ \
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{ \
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emitter->Name(regset.bits, r.reg, R(RAX), 4); \
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emitter->Name(regset.bits, RAX, R(r.reg), 4); \
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emitter->Name(regset.bits, r.reg, MatR(R12), 4); \
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ExpectDisassembly(#Name " " + r.name+ ", " + regset.out_name + ", 0x04 " \
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#Name " " + regset.out_name + ", " + r.name + ", 0x04 " \
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#Name " " + r.name + ", " + regset.size + " ptr ds:[r12], 0x04 "); \
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} \
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} \
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}
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VEX_RMI_TEST(RORX)
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