mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2025-07-21 05:09:34 -06:00
Since we have been employing the FIFO BP hack for so long time, at least let's make it a decent hack.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@4699 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
ayuanx
@ -77,6 +77,7 @@
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#include "ChunkFile.h"
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#include "CommandProcessor.h"
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namespace CommandProcessor
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{
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@ -99,12 +100,23 @@ u16 m_tokenReg;
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static u32 fake_GPWatchdogLastToken = 0;
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static Common::Event s_fifoIdleEvent;
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static Common::CriticalSection sFifoCritical;
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void FifoCriticalEnter()
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{
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sFifoCritical.Enter();
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}
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void FifoCriticalLeave()
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{
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sFifoCritical.Leave();
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}
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void DoState(PointerWrap &p)
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{
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p.Do(m_CPStatusReg);
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p.Do(m_CPCtrlReg);
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p.Do(m_CPClearReg);
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//p.Do(m_CPClearReg);
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p.Do(m_bboxleft);
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p.Do(m_bboxtop);
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p.Do(m_bboxright);
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@ -121,27 +133,6 @@ inline void WriteHigh(volatile u32& _reg, u16 highbits) {Common::AtomicStore(_re
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inline u16 ReadLow (u32 _reg) {return (u16)(_reg & 0xFFFF);}
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inline u16 ReadHigh (u32 _reg) {return (u16)(_reg >> 16);}
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// for GP watchdog hack
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void IncrementGPWDToken()
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{
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Common::AtomicIncrement(fifo.Fake_GPWDToken);
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}
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// Check every FAKE_GP_WATCHDOG_PERIOD if a PE-frame-finish occured
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// if not then lock CPUThread until GP finish a frame.
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void WaitForFrameFinish()
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{
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while ((fake_GPWatchdogLastToken == fifo.Fake_GPWDToken) && fifo.bFF_GPReadEnable && (fifo.CPReadWriteDistance > 0) && !(fifo.bFF_BPEnable && fifo.bFF_Breakpoint))
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s_fifoIdleEvent.MsgWait();
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fake_GPWatchdogLastToken = fifo.Fake_GPWDToken;
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}
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bool AllowIdleSkipping()
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{
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return !g_VideoInitialize.bOnThread || (!m_CPCtrlReg.CPIntEnable && !m_CPCtrlReg.BPEnable);
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}
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void UpdateInterrupts_Wrapper(u64 userdata, int cyclesLate)
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{
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UpdateInterrupts();
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@ -150,7 +141,7 @@ void UpdateInterrupts_Wrapper(u64 userdata, int cyclesLate)
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void Init()
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{
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m_CPStatusReg.Hex = 0;
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m_CPStatusReg.CommandIdle = 1;
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m_CPStatusReg.CommandIdle = 1; // Seems not used
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m_CPStatusReg.ReadIdle = 1;
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m_CPCtrlReg.Hex = 0;
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@ -165,7 +156,7 @@ void Init()
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fake_GPWatchdogLastToken = 0;
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memset(&fifo,0,sizeof(fifo));
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fifo.CPCmdIdle = 1 ;
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//fifo.CPCmdIdle = 1 ;
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fifo.CPReadIdle = 1;
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s_fifoIdleEvent.Init();
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@ -186,16 +177,21 @@ void Read16(u16& _rReturnValue, const u32 _Address)
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case STATUS_REGISTER:
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//TODO?: if really needed
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//m_CPStatusReg.CommandIdle = fifo.CPCmdIdle;
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// uncomment: change a bit the behaviour MP1. Not very useful though
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m_CPStatusReg.ReadIdle = fifo.CPReadIdle;
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//m_CPStatusReg.CommandIdle = fifo.CPReadIdle;
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// uncomment: change a bit the behaviour MP1. Not very useful though
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// hack: CPU will always believe fifo is empty and on idle
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//m_CPStatusReg.ReadIdle = 1;
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//m_CPStatusReg.CommandIdle = 1;
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m_CPStatusReg.ReadIdle = fifo.CPReadIdle; // This seems not necessary though
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m_CPStatusReg.Breakpoint = fifo.bFF_Breakpoint;
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// Clear on Read
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g_VideoInitialize.pSetInterrupt(INT_CAUSE_CP, false);
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_rReturnValue = m_CPStatusReg.Hex;
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INFO_LOG(COMMANDPROCESSOR, "\t iBP %s | fREADIDLE %s | fCMDIDLE %s | iOvF %s | iUndF %s"
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DEBUG_LOG(COMMANDPROCESSOR, "\t iBP %s | fREADIDLE %s | fCMDIDLE %s | iOvF %s | iUndF %s"
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, m_CPStatusReg.Breakpoint ? "ON" : "OFF"
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, m_CPStatusReg.ReadIdle ? "ON" : "OFF"
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, m_CPStatusReg.CommandIdle ? "ON" : "OFF"
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@ -224,17 +220,20 @@ void Read16(u16& _rReturnValue, const u32 _Address)
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// TODO: cases cleanup
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case FIFO_RW_DISTANCE_LO:
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//_rReturnValue = ReadLow (fifo.CPReadWriteDistance);
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// hack: CPU will always believe fifo is empty and on idle
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// But even if you return the true value, most games just don't care
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//_rReturnValue = ReadLow (fifo.CPReadWriteDistance);
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_rReturnValue = 0;
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DEBUG_LOG(COMMANDPROCESSOR, "read FIFO_RW_DISTANCE_LO : %04x", _rReturnValue);
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return;
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case FIFO_RW_DISTANCE_HI:
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//_rReturnValue = ReadHigh(fifo.CPReadWriteDistance);
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// hack: CPU will always believe fifo is empty and on idle
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// But even if you return the true value, most games just don't care
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//_rReturnValue = ReadHigh(fifo.CPReadWriteDistance);
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_rReturnValue = 0;
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DEBUG_LOG(COMMANDPROCESSOR, "read FIFO_RW_DISTANCE_HI : %04x", _rReturnValue);
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return;
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case FIFO_WRITE_POINTER_LO:
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_rReturnValue = ReadLow (fifo.CPWritePointer);
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DEBUG_LOG(COMMANDPROCESSOR, "read FIFO_WRITE_POINTER_LO : %04x", _rReturnValue);
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@ -243,15 +242,18 @@ void Read16(u16& _rReturnValue, const u32 _Address)
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_rReturnValue = ReadHigh(fifo.CPWritePointer);
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DEBUG_LOG(COMMANDPROCESSOR, "read FIFO_WRITE_POINTER_HI : %04x", _rReturnValue);
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return;
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case FIFO_READ_POINTER_LO:
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//_rReturnValue = ReadLow (fifo.CPReadPointer);
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// hack: CPU will always believe fifo is empty and on idle
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// But even if you return the true value, most games just don't care
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//_rReturnValue = ReadLow (fifo.CPReadPointer);
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_rReturnValue = ReadLow (fifo.CPWritePointer);
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DEBUG_LOG(COMMANDPROCESSOR, "read FIFO_READ_POINTER_LO : %04x", _rReturnValue);
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return;
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case FIFO_READ_POINTER_HI:
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//_rReturnValue = ReadHigh(fifo.CPReadPointer);
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// hack: CPU will always believe fifo is empty and on idle
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// But even if you return the true value, most games just don't care
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//_rReturnValue = ReadHigh(fifo.CPReadPointer);
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_rReturnValue = ReadHigh(fifo.CPWritePointer);
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DEBUG_LOG(COMMANDPROCESSOR, "read FIFO_READ_POINTER_HI : %04x", _rReturnValue);
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return;
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@ -271,15 +273,16 @@ void Read16(u16& _rReturnValue, const u32 _Address)
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case CP_PERF3_L: _rReturnValue = 0; WARN_LOG(COMMANDPROCESSOR, "Read from PERF3_L: %04x", _rReturnValue); break;
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case CP_PERF3_H: _rReturnValue = 0; WARN_LOG(COMMANDPROCESSOR, "Read from PERF3_H: %04x", _rReturnValue); break;
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// case 0x64:
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// return 4; //Number of clocks per vertex.. todo: calculate properly
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case CLKS_PER_VTX_OUT:
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_rReturnValue = 4; //Number of clocks per vertex.. TODO: Calculate properly
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WARN_LOG(COMMANDPROCESSOR, "Read from CLKS_PER_VTX_OUT: %04x", _rReturnValue);
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break;
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//add all the other regs here? are they ever read?
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default:
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WARN_LOG(COMMANDPROCESSOR, "(r16) unknown CP reg @ %08x", _Address);
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_rReturnValue = 0;
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return;
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WARN_LOG(COMMANDPROCESSOR, "(r16) unknown CP reg @ %08x", _Address);
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}
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return;
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}
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void Write16(const u16 _Value, const u32 _Address)
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@ -320,7 +323,7 @@ void Write16(const u16 _Value, const u32 _Address)
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DEBUG_LOG(COMMANDPROCESSOR, "*********************** GXSetGPFifo very soon? ***********************");
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// (mb2) We don't sleep here since it could be a perf issue for super monkey ball (yup only this game IIRC)
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// Touching that game is a no-go so I don't want to take the risk :p
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while (fifo.bFF_GPReadEnable && fifo.CPReadWriteDistance > 0 && !(fifo.bFF_BPEnable && fifo.bFF_Breakpoint) )
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while (fifo.bFF_GPReadEnable && fifo.CPReadWriteDistance && !fifo.bFF_Breakpoint)
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s_fifoIdleEvent.MsgWait();
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}
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}
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@ -329,35 +332,14 @@ void Write16(const u16 _Value, const u32 _Address)
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{
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case STATUS_REGISTER:
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{
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UCPStatusReg tmpStatus(_Value);
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// set the flags to "all is okay"
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m_CPStatusReg.OverflowHiWatermark = 0;
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m_CPStatusReg.UnderflowLoWatermark = 0;
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// TOCHECK (mb2): could BP irq be cleared here too?
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//if (tmpStatus.Breakpoint!=m_CPStatusReg.Breakpoint) _asm int 3
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// breakpoint
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/*if (tmpStatus.Breakpoint)
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{
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m_CPStatusReg.Breakpoint = 0;
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}
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//fifo.bFF_Breakpoint = m_CPStatusReg.Breakpoint;
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fifo.bFF_Breakpoint = m_CPStatusReg.Breakpoint ? true : false;
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//LOG(COMMANDPROCESSOR,"fifo.bFF_Breakpoint : %i",fifo.bFF_Breakpoint);
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*/
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// update interrupts
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UpdateInterrupts();
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INFO_LOG(COMMANDPROCESSOR,"\t write to STATUS_REGISTER : %04x", _Value);
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// This should be Read-Only
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ERROR_LOG(COMMANDPROCESSOR,"\t write to STATUS_REGISTER : %04x", _Value);
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PanicAlert("CommandProcessor:: CPU writes to STATUS_REGISTER!");
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}
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break;
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case CTRL_REGISTER:
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{
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UCPCtrlReg tmpCtrl(_Value);
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// TOCHECK (mb2): could BP irq be cleared with w16 to STATUS_REGISTER?
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// funny hack: eg in MP1 if we disable the clear breakpoint ability by commenting this block
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// the game is of course faster but looks stable too.
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@ -365,32 +347,30 @@ void Write16(const u16 _Value, const u32 _Address)
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// So I let the hack for now.
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// Checkmate re-enabled it, so please test
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// TODO (mb2): fix this!
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// BP interrupt is cleared here
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// Why do we need the rising edge? Making it falling egde fixes Silent Hill Shattered Memories
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// It seems the clear on rising edge makes a dead lock between CPU & GPU
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// Don't we need a Thread Synchronization Mechanism here?
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// Otherwise how do we guarantee the fifo access (on a whole entry) is atomic?
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//
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if (m_CPCtrlReg.CPIntEnable && !tmpCtrl.Hex) // falling edge
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// raising edge or falling egde
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//if ((!m_CPCtrlReg.CPIntEnable && tmpCtrl.CPIntEnable) || (m_CPCtrlReg.CPIntEnable && !tmpCtrl.Hex))
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{
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m_CPStatusReg.Breakpoint = 0;
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Common::AtomicStore(fifo.bFF_Breakpoint, 0);
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}
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Common::AtomicStore(fifo.bFF_GPReadEnable, tmpCtrl.GPReadEnable);
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Common::AtomicStore(fifo.bFF_GPLinkEnable, tmpCtrl.GPLinkEnable);
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Common::AtomicStore(fifo.bFF_BPEnable, tmpCtrl.BPEnable);
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UCPCtrlReg tmpCtrl(_Value);
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m_CPCtrlReg.Hex = tmpCtrl.Hex;
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UpdateInterrupts();
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Common::AtomicStore(fifo.bFF_GPLinkEnable, tmpCtrl.GPLinkEnable);
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Common::AtomicStore(fifo.bFF_GPReadEnable, tmpCtrl.GPReadEnable);
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if (g_VideoInitialize.bOnThread)
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{
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// Instant Breakpoint and Interrupt, since we haven't implemented accurate BP on dual core
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// Most likely the Read thread has already exceeded BP here, but it seems we are still cool
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Common::AtomicStore(fifo.bFF_Breakpoint, tmpCtrl.BPEnable && tmpCtrl.CPIntEnable && tmpCtrl.GPReadEnable);
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UpdateInterrupts();
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}
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else
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{
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// fifo.bFF_BPEnable is only used in single core
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Common::AtomicStore(fifo.bFF_BPEnable, tmpCtrl.BPEnable && tmpCtrl.CPIntEnable && tmpCtrl.GPReadEnable);
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if (!tmpCtrl.BPEnable || !tmpCtrl.CPIntEnable || !tmpCtrl.GPReadEnable)
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Common::AtomicStore(fifo.bFF_Breakpoint, 0);
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}
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to CTRL_REGISTER : %04x", _Value);
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DEBUG_LOG(COMMANDPROCESSOR, "\t GPREAD %s | CPULINK %s | BP %s || CPIntEnable %s | OvF %s | UndF %s"
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DEBUG_LOG(COMMANDPROCESSOR, "\t GPREAD %s | LINK %s | BP %s || Int %s | OvF %s | UndF %s"
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, fifo.bFF_GPReadEnable ? "ON" : "OFF"
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, fifo.bFF_GPLinkEnable ? "ON" : "OFF"
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, fifo.bFF_BPEnable ? "ON" : "OFF"
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@ -402,19 +382,16 @@ void Write16(const u16 _Value, const u32 _Address)
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break;
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case PERF_SELECT:
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{
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WARN_LOG(COMMANDPROCESSOR, "write to PERF_SELECT: %04x", _Value);
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// Seems to select which set of perf counters should be exposed.
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}
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// Seems to select which set of perf counters should be exposed.
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WARN_LOG(COMMANDPROCESSOR, "write to PERF_SELECT: %04x", _Value);
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break;
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case CLEAR_REGISTER:
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{
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// ????
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UCPClearReg tmpClearReg(_Value);
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m_CPClearReg.Hex = 0;
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INFO_LOG(COMMANDPROCESSOR,"\t write to CLEAR_REGISTER : %04x",_Value);
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}
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// We don't care since we don't implement Watermark
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//m_CPClearReg.Hex = 0;
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//m_CPStatusReg.OverflowHiWatermark = 0;
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//m_CPStatusReg.UnderflowHiWatermark = 0;
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to CLEAR_REGISTER : %04x", _Value);
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break;
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// Fifo Registers
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@ -423,44 +400,40 @@ void Write16(const u16 _Value, const u32 _Address)
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_TOKEN_REGISTER : %04x", _Value);
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break;
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case FIFO_BASE_LO:
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WriteLow ((u32 &)fifo.CPBase, _Value);
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fifo.CPBase &= 0xFFFFFFE0;
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case FIFO_BASE_LO:
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// Oh hell, somtimes this value is not aligned with 32B, like New Super Mario Bros. Wii
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WriteLow ((u32 &)fifo.CPBase, _Value & 0xFFE0);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_BASE_LO : %04x", _Value);
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break;
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case FIFO_BASE_HI:
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case FIFO_BASE_HI:
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WriteHigh((u32 &)fifo.CPBase, _Value);
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fifo.CPBase &= 0xFFFFFFE0;
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_BASE_HI : %04x", _Value);
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break;
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case FIFO_END_LO:
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WriteLow ((u32 &)fifo.CPEnd, _Value);
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fifo.CPEnd &= 0xFFFFFFE0;
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case FIFO_END_LO:
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WriteLow ((u32 &)fifo.CPEnd, _Value & 0xFFE0);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_END_LO : %04x", _Value);
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break;
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case FIFO_END_HI:
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case FIFO_END_HI:
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WriteHigh((u32 &)fifo.CPEnd, _Value);
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fifo.CPEnd &= 0xFFFFFFE0;
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_END_HI : %04x", _Value);
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break;
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// Hm. Should we really & these with FFFFFFE0?
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// (mb2): never seen 32B not aligned values for those following regs.
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// fifo.CPEnd is the only value that could be not 32B aligned so far.
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case FIFO_WRITE_POINTER_LO:
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WriteLow ((u32 &)fifo.CPWritePointer, _Value); fifo.CPWritePointer &= 0xFFFFFFE0;
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WriteLow ((u32 &)fifo.CPWritePointer, _Value & 0xFFE0);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_WRITE_POINTER_LO : %04x", _Value);
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break;
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case FIFO_WRITE_POINTER_HI:
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WriteHigh((u32 &)fifo.CPWritePointer, _Value); fifo.CPWritePointer &= 0xFFFFFFE0;
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WriteHigh((u32 &)fifo.CPWritePointer, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_WRITE_POINTER_HI : %04x", _Value);
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break;
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case FIFO_READ_POINTER_LO:
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WriteLow ((u32 &)fifo.CPReadPointer, _Value); fifo.CPReadPointer &= 0xFFFFFFE0;
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WriteLow ((u32 &)fifo.CPReadPointer, _Value & 0xFFE0);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_READ_POINTER_LO : %04x", _Value);
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break;
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case FIFO_READ_POINTER_HI:
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WriteHigh((u32 &)fifo.CPReadPointer, _Value); fifo.CPReadPointer &= 0xFFFFFFE0;
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WriteHigh((u32 &)fifo.CPReadPointer, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_READ_POINTER_HI : %04x", _Value);
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break;
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@ -472,6 +445,7 @@ void Write16(const u16 _Value, const u32 _Address)
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WriteHigh((u32 &)fifo.CPHiWatermark, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_HI_WATERMARK_HI : %04x", _Value);
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break;
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case FIFO_LO_WATERMARK_LO:
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WriteLow ((u32 &)fifo.CPLoWatermark, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_LO_WATERMARK_LO : %04x", _Value);
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@ -502,13 +476,18 @@ void Write16(const u16 _Value, const u32 _Address)
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//WriteLow((u32 &)fifo.CPReadWriteDistance, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"try to write to FIFO_RW_DISTANCE_LO : %04x", _Value);
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break;
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default:
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WARN_LOG(COMMANDPROCESSOR, "(w16) unknown CP reg write %04x @ %08x", _Value, _Address);
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}
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// TODO(mb2): better. Check if it help: avoid CPReadPointer overwrites when stupidly done like in Super Monkey Ball
|
||||
if ((!fifo.bFF_GPReadEnable && fifo.CPReadIdle) || !g_VideoInitialize.bOnThread) // TOCHECK(mb2): check again if thread safe?
|
||||
{
|
||||
if (g_VideoInitialize.bOnThread) FifoCriticalEnter(); // This may not be necessary, just for safety
|
||||
UpdateFifoRegister();
|
||||
if (g_VideoInitialize.bOnThread) FifoCriticalLeave();
|
||||
}
|
||||
}
|
||||
|
||||
void Read32(u32& _rReturnValue, const u32 _Address)
|
||||
@ -522,6 +501,27 @@ void Write32(const u32 _Data, const u32 _Address)
|
||||
_dbg_assert_msg_(COMMANDPROCESSOR, 0, "Write32 at CommandProccessor at 0x%08x", _Address);
|
||||
}
|
||||
|
||||
// for GP watchdog hack
|
||||
void IncrementGPWDToken()
|
||||
{
|
||||
Common::AtomicIncrement(fifo.Fake_GPWDToken);
|
||||
}
|
||||
|
||||
bool AllowIdleSkipping()
|
||||
{
|
||||
return !g_VideoInitialize.bOnThread || (!m_CPCtrlReg.CPIntEnable && !m_CPCtrlReg.BPEnable);
|
||||
}
|
||||
|
||||
// Check every FAKE_GP_WATCHDOG_PERIOD if a PE-frame-finish occured
|
||||
// if not then lock CPUThread until GP finish a frame.
|
||||
void WaitForFrameFinish()
|
||||
{
|
||||
while ((fake_GPWatchdogLastToken == fifo.Fake_GPWDToken) && fifo.bFF_GPReadEnable && fifo.CPReadWriteDistance && !fifo.bFF_Breakpoint)
|
||||
s_fifoIdleEvent.MsgWait();
|
||||
|
||||
fake_GPWatchdogLastToken = fifo.Fake_GPWDToken;
|
||||
}
|
||||
|
||||
void STACKALIGN GatherPipeBursted()
|
||||
{
|
||||
// if we aren't linked, we don't care about gather pipe data
|
||||
@ -535,8 +535,10 @@ void STACKALIGN GatherPipeBursted()
|
||||
fifo.CPWritePointer = fifo.CPBase;
|
||||
else
|
||||
fifo.CPWritePointer += GATHER_PIPE_SIZE;
|
||||
|
||||
|
||||
FifoCriticalEnter(); // This may not be necessary, just for safety
|
||||
Common::AtomicAdd(fifo.CPReadWriteDistance, GATHER_PIPE_SIZE);
|
||||
FifoCriticalLeave();
|
||||
|
||||
// High watermark overflow handling (hacked way)
|
||||
if (fifo.CPReadWriteDistance > fifo.CPHiWatermark)
|
||||
@ -559,7 +561,7 @@ void STACKALIGN GatherPipeBursted()
|
||||
|
||||
INFO_LOG(COMMANDPROCESSOR, "(GatherPipeBursted): CPHiWatermark reached");
|
||||
// Wait for GPU to catch up
|
||||
while (!(fifo.bFF_BPEnable && fifo.bFF_Breakpoint) && fifo.CPReadWriteDistance > fifo.CPLoWatermark)
|
||||
while (fifo.CPReadWriteDistance > fifo.CPLoWatermark && !fifo.bFF_Breakpoint)
|
||||
s_fifoIdleEvent.MsgWait();
|
||||
}
|
||||
// check if we are in sync
|
||||
@ -582,27 +584,30 @@ void STACKALIGN GatherPipeBursted()
|
||||
}
|
||||
}
|
||||
|
||||
// This is mostly used in single core mode
|
||||
// This is only used in single core mode
|
||||
void CatchUpGPU()
|
||||
{
|
||||
// check if we are able to run this buffer
|
||||
if ((fifo.bFF_GPReadEnable) && !(fifo.bFF_BPEnable && fifo.bFF_Breakpoint))
|
||||
if (fifo.bFF_GPReadEnable && !fifo.bFF_Breakpoint)
|
||||
{
|
||||
// HyperIris: Memory_GetPtr is an expensive call, call it less, run faster
|
||||
u8 *ptr = Memory_GetPtr(fifo.CPReadPointer);
|
||||
|
||||
while (fifo.CPReadWriteDistance > 0)
|
||||
// Sometimes we have already exceeded the BP even before it is set
|
||||
// so careful check is required
|
||||
while (fifo.CPReadWriteDistance || (fifo.bFF_BPEnable && !fifo.bFF_Breakpoint))
|
||||
{
|
||||
// check if we are on a breakpoint
|
||||
if (fifo.bFF_BPEnable)
|
||||
{
|
||||
//MessageBox(0,"Breakpoint enabled",0,0);
|
||||
if ((fifo.CPReadPointer & ~0x1F) == (fifo.CPBreakpoint & ~0x1F))
|
||||
if (
|
||||
(fifo.CPReadPointer == fifo.CPBreakpoint) ||
|
||||
(fifo.CPReadPointer == fifo.CPWritePointer) ||
|
||||
(fifo.CPWritePointer < fifo.CPBreakpoint)
|
||||
)
|
||||
{
|
||||
//_assert_msg_(POWERPC,0,"BP: %08x",fifo.CPBreakpoint);
|
||||
//LOG(COMMANDPROCESSOR,"!!! BP irq raised");
|
||||
fifo.bFF_Breakpoint = 1;
|
||||
m_CPStatusReg.Breakpoint = 1;
|
||||
UpdateInterrupts();
|
||||
break;
|
||||
}
|
||||
@ -616,14 +621,13 @@ void CatchUpGPU()
|
||||
LoadSSEState();
|
||||
|
||||
fifo.CPReadWriteDistance -= 32;
|
||||
|
||||
// increase the ReadPtr
|
||||
if (fifo.CPReadPointer >= fifo.CPEnd)
|
||||
{
|
||||
fifo.CPReadPointer = fifo.CPBase;
|
||||
// adjust, take care
|
||||
ptr = Memory_GetPtr(fifo.CPReadPointer);
|
||||
INFO_LOG(COMMANDPROCESSOR, "BUFFER LOOP");
|
||||
DEBUG_LOG(COMMANDPROCESSOR, "Fifo Loop");
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -667,21 +671,12 @@ void UpdateFifoRegister()
|
||||
|
||||
void UpdateInterrupts()
|
||||
{
|
||||
if (m_CPCtrlReg.CPIntEnable &&
|
||||
(fifo.bFF_BPEnable && fifo.bFF_Breakpoint))
|
||||
{
|
||||
g_VideoInitialize.pSetInterrupt(INT_CAUSE_CP, true);
|
||||
}
|
||||
else
|
||||
{
|
||||
g_VideoInitialize.pSetInterrupt(INT_CAUSE_CP, false);
|
||||
}
|
||||
DEBUG_LOG(COMMANDPROCESSOR, "Fifo Breakpoint Interrupt triggered");
|
||||
g_VideoInitialize.pSetInterrupt(INT_CAUSE_CP, true);
|
||||
}
|
||||
|
||||
void UpdateInterruptsFromVideoPlugin()
|
||||
{
|
||||
if (fifo.bFF_Breakpoint) // implicit since only BP trigger (see fifo.cpp) can call this
|
||||
m_CPStatusReg.Breakpoint = 1;
|
||||
g_VideoInitialize.pScheduleEvent_Threadsafe(0, et_UpdateInterrupts, 0);
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user