From 0dcf228aafc60b8d4dc404e112e3a8b9241100cf Mon Sep 17 00:00:00 2001 From: "Admiral H. Curtiss" Date: Tue, 10 Jan 2023 01:49:07 +0100 Subject: [PATCH] PowerPC: Parametrize TU macro. --- .../Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp | 2 +- Source/Core/Core/PowerPC/PowerPC.cpp | 2 +- Source/Core/Core/PowerPC/PowerPC.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp b/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp index 455b224202..c5206d5b7a 100644 --- a/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp +++ b/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp @@ -314,7 +314,7 @@ void Interpreter::mtspr(UGeckoInstruction inst) break; case SPR_TU_W: - TU = PowerPC::ppcState.gpr[inst.RD]; + TU(PowerPC::ppcState) = PowerPC::ppcState.gpr[inst.RD]; SystemTimers::TimeBaseSet(); break; diff --git a/Source/Core/Core/PowerPC/PowerPC.cpp b/Source/Core/Core/PowerPC/PowerPC.cpp index 6df289eb47..7d12b90a9e 100644 --- a/Source/Core/Core/PowerPC/PowerPC.cpp +++ b/Source/Core/Core/PowerPC/PowerPC.cpp @@ -207,7 +207,7 @@ static void ResetRegisters() IBATUpdated(); TL(PowerPC::ppcState) = 0; - TU = 0; + TU(PowerPC::ppcState) = 0; SystemTimers::TimeBaseSet(); // MSR should be 0x40, but we don't emulate BS1, so it would never be turned off :} diff --git a/Source/Core/Core/PowerPC/PowerPC.h b/Source/Core/Core/PowerPC/PowerPC.h index e751e4aef7..33229fffa5 100644 --- a/Source/Core/Core/PowerPC/PowerPC.h +++ b/Source/Core/Core/PowerPC/PowerPC.h @@ -252,7 +252,7 @@ void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst); #define SRR1(ppc_state) (ppc_state).spr[SPR_SRR1] #define GQR(ppc_state, x) (ppc_state).spr[SPR_GQR0 + (x)] #define TL(ppc_state) (ppc_state).spr[SPR_TL] -#define TU PowerPC::ppcState.spr[SPR_TU] +#define TU(ppc_state) (ppc_state).spr[SPR_TU] inline void SetCarry(u32 ca) {