From 215e014515cc6517da3f0627835f353a19bfb599 Mon Sep 17 00:00:00 2001 From: nakeee Date: Mon, 6 Apr 2009 19:03:53 +0000 Subject: [PATCH] splitting shifti to lsr/lsr/asl/asr please review git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2905 8ced0084-cf51-0410-be5f-012b33b47a6e --- .../Src/DSPInterpreter.cpp | 101 +++++++++++------- .../Src/DSPInterpreter.h | 5 +- .../Plugin_DSP_LLE-testing/Src/DSPTables.cpp | 8 +- 3 files changed, 72 insertions(+), 42 deletions(-) diff --git a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.cpp b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.cpp index 4156b587c5..c648acf0af 100644 --- a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.cpp +++ b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.cpp @@ -130,7 +130,6 @@ void rti(const UDSPInstruction& opc) // HALT // 0000 0000 0020 0001 // Stops execution of DSP code. Sets bit DSP_CR_HALT in register DREG_CR. - void halt(const UDSPInstruction& opc) { g_dsp.cr |= 0x4; @@ -207,6 +206,10 @@ void bloopi(const UDSPInstruction& opc) //------------------------------------------------------------- +// MRR $D, $S +// 0001 11dd ddds ssss +// Move value from register $S to register $D. +// FIXME: Perform additional operation depending on destination register. void mrr(const UDSPInstruction& opc) { u8 sreg = opc.hex & 0x1f; @@ -1020,6 +1023,9 @@ void addi(const UDSPInstruction& opc) Update_SR_Register64(acc); } +// LSL16 $acR +// 1111 000r xxxx xxxx +// Logically shifts left accumulator $acR by 16. void lsl16(const UDSPInstruction& opc) { u8 areg = (opc.hex >> 8) & 0x1; @@ -1049,72 +1055,93 @@ void msub(const UDSPInstruction& opc) dsp_set_long_prod(prod); } +// LSR16 $acR +// 1111 010r xxxx xxxx +// Logically shifts right accumulator $acR by 16. void lsr16(const UDSPInstruction& opc) { u8 areg = (opc.hex >> 8) & 0x1; s64 acc = dsp_get_long_acc(areg); + acc >>= 16; dsp_set_long_acc(areg, acc); Update_SR_Register64(acc); } +// ASR16 $acR +// 1001 r001 xxxx xxxx +// Arithmetically shifts right accumulator $acR by 16. void asr16(const UDSPInstruction& opc) { u8 areg = (opc.hex >> 11) & 0x1; s64 acc = dsp_get_long_acc(areg); + acc >>= 16; dsp_set_long_acc(areg, acc); Update_SR_Register64(acc); } -void shifti(const UDSPInstruction& opc) +// LSL $acR, #I +// 0001 010r 00ii iiii +// Logically shifts left accumulator $acR by number specified by value I. +void lsl(const UDSPInstruction& opc) +{ + u16 shift = opc.ushift; + s64 acc = dsp_get_long_acc(opc.areg); + + acc <<= shift; + dsp_set_long_acc(opc.areg, acc); + + Update_SR_Register64(acc); +} + +// LSR $acR, #I +// 0001 010r 01ii iiii +// Logically shifts left accumulator $acR by number specified by value +// calculated by negating sign extended bits 0-6. +void lsr(const UDSPInstruction& opc) +{ + u16 shift = -opc.ushift; + s64 acc = dsp_get_long_acc(opc.areg); + + acc >>= shift; + dsp_set_long_acc(opc.areg, acc); + + Update_SR_Register64(acc); +} + +// ASL $acR, #I +// 0001 010r 10ii iiii +// Logically shifts left accumulator $acR by number specified by value I. +void asl(const UDSPInstruction& opc) { - // direction: left - bool ShiftLeft = true; u16 shift = opc.ushift; - if ((opc.negating) && (opc.shift < 0)) - { - ShiftLeft = false; - shift = -opc.shift; - } + // arithmetic shift + s64 acc = dsp_get_long_acc(opc.areg); + acc <<= shift; - s64 acc; - u64 uacc; + dsp_set_long_acc(opc.areg, acc); - if (opc.arithmetic) - { - // arithmetic shift - uacc = dsp_get_long_acc(opc.areg); + Update_SR_Register64(acc); +} - if (!ShiftLeft) - { - uacc >>= shift; - } - else - { - uacc <<= shift; - } +// ASR $acR, #I +// 0001 010r 11ii iiii +// Arithmetically shifts left accumulator $acR by number specified by +// value calculated by negating sign extended bits 0-6. - acc = uacc; - } - else - { - acc = dsp_get_long_acc(opc.areg); +void asr(const UDSPInstruction& opc) +{ + u16 shift = -opc.ushift; - if (!ShiftLeft) - { - acc >>= shift; - } - else - { - acc <<= shift; - } - } + // arithmetic shift + s64 acc = dsp_get_long_acc(opc.areg); + acc >>= shift; dsp_set_long_acc(opc.areg, acc); diff --git a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.h b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.h index 3241736403..d59731e7c0 100644 --- a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.h +++ b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.h @@ -88,7 +88,10 @@ void madd(const UDSPInstruction& opc); void msub(const UDSPInstruction& opc); void lsr16(const UDSPInstruction& opc); void asr16(const UDSPInstruction& opc); -void shifti(const UDSPInstruction& opc); +void lsl(const UDSPInstruction& opc); +void lsr(const UDSPInstruction& opc); +void asl(const UDSPInstruction& opc); +void asr(const UDSPInstruction& opc); void dar(const UDSPInstruction& opc); void iar(const UDSPInstruction& opc); void sbclr(const UDSPInstruction& opc); diff --git a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPTables.cpp b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPTables.cpp index dbc3729fa6..ed8e1af607 100644 --- a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPTables.cpp +++ b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPTables.cpp @@ -147,10 +147,10 @@ DSPOPCTemplate opcodes[] = {"SBCLR", 0x1200, 0xfff8, DSPInterpreter::sbclr, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, NULL, NULL}, {"SBSET", 0x1300, 0xfff8, DSPInterpreter::sbset, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, NULL, NULL}, - {"LSL", 0x1400, 0xfec0, DSPInterpreter::shifti, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, NULL, NULL}, // 0x007f? - {"LSR", 0x1440, 0xfec0, DSPInterpreter::shifti, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, NULL, NULL}, // 0x007f? - {"ASL", 0x1480, 0xfec0, DSPInterpreter::shifti, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x007f}}, NULL, NULL}, - {"ASR", 0x14c0, 0xfec0, DSPInterpreter::shifti, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x007f}}, NULL, NULL}, + {"LSL", 0x1400, 0xfec0, DSPInterpreter::lsl, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, NULL, NULL}, // 0x007f? + {"LSR", 0x1440, 0xfec0, DSPInterpreter::lsr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, NULL, NULL}, // 0x007f? + {"ASL", 0x1480, 0xfec0, DSPInterpreter::asl, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x007f}}, NULL, NULL}, + {"ASR", 0x14c0, 0xfec0, DSPInterpreter::asr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x007f}}, NULL, NULL}, {"LRI", 0x0080, 0xffe0, DSPInterpreter::lri, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_IMM, 2, 1, 0, 0xffff}}, NULL, NULL},