diff --git a/Source/DSPSpy/tests/accelerator_loop_test.ds b/Source/DSPSpy/tests/accelerator_loop_test.ds
index 82ec2c1283..d3c37e92d1 100644
--- a/Source/DSPSpy/tests/accelerator_loop_test.ds
+++ b/Source/DSPSpy/tests/accelerator_loop_test.ds
@@ -9,12 +9,6 @@ lri $AC0.L, #0x0000 ; start
 lri $AC1.M, #0x0000 ; end
 lri $AC1.L, #0x0011 ; end
 
-; Reset some registers
-lri $AC0.H, #0xffff
-sr @0xffda, $AC0.H ; pred scale
-sr @0xffdb, $AC0.H ; yn1
-sr @0xffdc, $AC0.H ; yn2
-
 ; Set the sample format
 lri $AC0.H, #0x0
 sr @0xffd1, $AC0.H
@@ -27,6 +21,12 @@ srs @ACCAL, $AC0.L
 srs @ACEAH, $AC1.M
 srs @ACEAL, $AC1.L
 
+; Reset some registers (these must be reset after setting FORMAT)
+lri $AC0.H, #0xffff
+sr @0xffda, $AC0.H ; pred scale
+sr @0xffdb, $AC0.H ; yn1
+sr @0xffdc, $AC0.H ; yn2
+
 call load_hw_reg_to_regs
 call send_back ; check the accelerator regs before a read
 
@@ -34,6 +34,7 @@ bloopi #40, end_of_loop
   lr $IX3, @ACDSAMP
   call load_hw_reg_to_regs
   call send_back ; after a read
+  nop ; Loops that end at a return of a call are buggy on hw
 end_of_loop:
   nop
 
diff --git a/Source/DSPSpy/tests/accelerator_pcm_test.ds b/Source/DSPSpy/tests/accelerator_pcm_test.ds
new file mode 100644
index 0000000000..24b4eae873
--- /dev/null
+++ b/Source/DSPSpy/tests/accelerator_pcm_test.ds
@@ -0,0 +1,79 @@
+incdir  "tests"
+include "dsp_base.inc"
+
+test_main:
+
+; Test parameters
+lri $AC0.M, #0x0000 ; start
+lri $AC0.L, #0x0000 ; start
+lri $AC1.M, #0x0000 ; end
+lri $AC1.L, #0x0011 ; end
+
+; Set the sample format
+lri $AC0.H, #0x08 ; 4-bit PCM, gain scaling = x / 2048
+sr @0xffd1, $AC0.H
+; Set the starting and current address
+srs @ACSAH, $AC0.M
+srs @ACCAH, $AC0.M
+srs @ACSAL, $AC0.L
+srs @ACCAL, $AC0.L
+; Set the ending address
+srs @ACEAH, $AC1.M
+srs @ACEAL, $AC1.L
+
+; Set the gains
+si @GAIN, #0x0800 ; 2048 / 2048 = 1.0
+si @COEF_A1_0, #0x0400 ; 1024 / 2048 = 0.5
+si @COEF_A2_0, #0x0200 ; 512 / 2048 = 0.25
+
+; Reset some registers (these must be reset after setting FORMAT)
+lri $AC0.H, #0x0000
+sr @0xffda, $AC0.H ; pred scale, use 0th coefficients
+sr @0xffdb, $AC0.H ; yn1
+sr @0xffdc, $AC0.H ; yn2
+
+call load_hw_reg_to_regs
+call send_back ; check the accelerator regs before a read
+
+; Expected read sequence
+; r[0] = (data[0] >> 4) + (0/2) + (0/4)
+; r[1] = (data[0] & 0xf) + (r[0]/2) + (0/4)
+; r[2] = (data[1] >> 4) + (r[1]/2) + (r[0]/4)
+; r[3] = (data[1] & 0xf) + (r[2]/2) + (r[1]/4)
+; ...
+
+bloopi #40, end_of_loop
+  lr $IX3, @ACDSAMP
+  call load_hw_reg_to_regs
+  call send_back ; after a read
+  nop ; Loops that end at a return of a call are buggy on hw
+end_of_loop:
+  nop
+
+jmp end_of_test
+
+load_hw_reg_to_regs:
+  lr $AR0, @0xffd1 ; format
+  lr $AR1, @0xffd2 ; unknown
+  lr $AR2, @0xffda ; pred scale
+  lr $AR3, @0xffdb ; yn1
+  lr $IX0, @0xffdc ; yn2
+  lr $IX1, @0xffdf ; unknown accelerator register
+
+  lri $AC0.H, #0
+  lrs $AC0.M, @ACSAH
+  lrs $AC0.L, @ACSAL
+
+  lri $AC1.H, #0
+  lrs $AC1.M, @ACEAH
+  lrs $AC1.L, @ACEAL
+
+  lrs $AX0.H, @ACCAH
+  lrs $AX0.L, @ACCAL
+  lrs $AX1.H, @ACCAH
+  lrs $AX1.L, @ACCAL
+
+  lrs $AX1.H, @ACCAH
+  lrs $AX1.L, @ACCAL
+
+  ret