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Merge pull request #10828 from JosJuice/jitarm64-32-bit-exception
JitArm64: Pass 32-bit temp GPR to WriteConditionalExceptionExit
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@ -109,7 +109,7 @@ void JitArm64::psq_lXX(UGeckoInstruction inst)
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LDR(EncodeRegTo64(type_reg), ARM64Reg::X30, ArithOption(EncodeRegTo64(type_reg), true));
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LDR(EncodeRegTo64(type_reg), ARM64Reg::X30, ArithOption(EncodeRegTo64(type_reg), true));
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BLR(EncodeRegTo64(type_reg));
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BLR(EncodeRegTo64(type_reg));
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WriteConditionalExceptionExit(EXCEPTION_DSI, ARM64Reg::X30, ARM64Reg::Q1);
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WriteConditionalExceptionExit(EXCEPTION_DSI, ARM64Reg::W30, ARM64Reg::Q1);
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m_float_emit.ORR(EncodeRegToDouble(VS), ARM64Reg::D0, ARM64Reg::D0);
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m_float_emit.ORR(EncodeRegToDouble(VS), ARM64Reg::D0, ARM64Reg::D0);
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}
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}
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@ -261,7 +261,7 @@ void JitArm64::psq_stXX(UGeckoInstruction inst)
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LDR(EncodeRegTo64(type_reg), ARM64Reg::X30, ArithOption(EncodeRegTo64(type_reg), true));
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LDR(EncodeRegTo64(type_reg), ARM64Reg::X30, ArithOption(EncodeRegTo64(type_reg), true));
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BLR(EncodeRegTo64(type_reg));
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BLR(EncodeRegTo64(type_reg));
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WriteConditionalExceptionExit(EXCEPTION_DSI, ARM64Reg::X30, ARM64Reg::Q1);
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WriteConditionalExceptionExit(EXCEPTION_DSI, ARM64Reg::W30, ARM64Reg::Q1);
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}
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}
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if (update && !early_update)
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if (update && !early_update)
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