mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2025-07-23 14:19:46 -06:00
LLE JIT: Added another 9 DSP Load/Store instructions to the JIT. Fixed a couple bugs in the 32bit and Linux builds.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6599 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
skidau
@ -36,7 +36,7 @@ void DSPEmitter::srs(const UDSPInstruction opc)
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//u16 addr = (g_dsp.r[DSP_REG_CR] << 8) | (opc & 0xFF);
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
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MOV(32, R(EAX), M(&g_dsp.r[DSP_REG_CR]));
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MOVZX(32, 8, EAX, M(&g_dsp.r[DSP_REG_CR]));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOVZX(64, 16, RCX, MDisp(R11,reg*2));
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@ -57,7 +57,7 @@ void DSPEmitter::lrs(const UDSPInstruction opc)
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u8 reg = ((opc >> 8) & 0x7) + 0x18;
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//u16 addr = (g_dsp.r[DSP_REG_CR] << 8) | (opc & 0xFF);
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#ifdef _M_IX86 // All32
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MOV(32, R(ECX), M(&g_dsp.r[DSP_REG_CR]));
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MOVZX(32, 8, ECX, M(&g_dsp.r[DSP_REG_CR]));
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SHL(16, R(ECX), Imm8(8));
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OR(8, R(ECX), Imm8(opc & 0xFF));
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dmem_read();
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@ -118,47 +118,65 @@ void DSPEmitter::si(const UDSPInstruction opc)
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// 0001 1000 0ssd dddd
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// Move value from data memory pointed by addressing register $S to register $D.
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// FIXME: Perform additional operation depending on destination register.
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//void DSPEmitter::lrr(const UDSPInstruction opc)
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//{
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// u8 sreg = (opc >> 5) & 0x3;
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// u8 dreg = opc & 0x1f;
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void DSPEmitter::lrr(const UDSPInstruction opc)
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{
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u8 sreg = (opc >> 5) & 0x3;
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u8 dreg = opc & 0x1f;
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// u16 val = dsp_dmem_read(dsp_op_read_reg(sreg));
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// dsp_op_write_reg(dreg, val);
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// dsp_conditional_extend_accum(dreg);
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//}
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dsp_op_read_reg(sreg, ECX);
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, ECX, R(ECX));
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#else
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MOVZX(64, 16, ECX, R(ECX));
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#endif
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dmem_read();
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dsp_op_write_reg(dreg, EAX);
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dsp_conditional_extend_accum(dreg);
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}
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// LRRD $D, @$S
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// 0001 1000 1ssd dddd
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// Move value from data memory pointed by addressing register $S toregister $D.
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// Decrement register $S.
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// FIXME: Perform additional operation depending on destination register.
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//void DSPEmitter::lrrd(const UDSPInstruction opc)
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//{
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// u8 sreg = (opc >> 5) & 0x3;
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// u8 dreg = opc & 0x1f;
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void DSPEmitter::lrrd(const UDSPInstruction opc)
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{
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u8 sreg = (opc >> 5) & 0x3;
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u8 dreg = opc & 0x1f;
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// u16 val = dsp_dmem_read(dsp_op_read_reg(sreg));
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// dsp_op_write_reg(dreg, val);
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// dsp_conditional_extend_accum(dreg);
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// g_dsp.r[sreg] = dsp_decrement_addr_reg(sreg);
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//}
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dsp_op_read_reg(sreg, ECX);
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, ECX, R(ECX));
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#else
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MOVZX(64, 16, ECX, R(ECX));
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#endif
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dmem_read();
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dsp_op_write_reg(dreg, EAX);
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dsp_conditional_extend_accum(dreg);
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decrement_addr_reg(sreg);
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}
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// LRRI $D, @$S
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// 0001 1001 0ssd dddd
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// Move value from data memory pointed by addressing register $S to register $D.
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// Increment register $S.
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// FIXME: Perform additional operation depending on destination register.
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//void DSPEmitter::lrri(const UDSPInstruction opc)
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//{
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// u8 sreg = (opc >> 5) & 0x3;
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// u8 dreg = opc & 0x1f;
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void DSPEmitter::lrri(const UDSPInstruction opc)
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{
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u8 sreg = (opc >> 5) & 0x3;
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u8 dreg = opc & 0x1f;
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// u16 val = dsp_dmem_read(dsp_op_read_reg(sreg));
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// dsp_op_write_reg(dreg, val);
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// dsp_conditional_extend_accum(dreg);
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// g_dsp.r[sreg] = dsp_increment_addr_reg(sreg);
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//}
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dsp_op_read_reg(sreg, ECX);
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, ECX, R(ECX));
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#else
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MOVZX(64, 16, ECX, R(ECX));
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#endif
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dmem_read();
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dsp_op_write_reg(dreg, EAX);
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dsp_conditional_extend_accum(dreg);
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increment_addr_reg(sreg);
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}
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// LRRN $D, @$S
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// 0001 1001 1ssd dddd
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@ -181,45 +199,62 @@ void DSPEmitter::si(const UDSPInstruction opc)
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// Store value from source register $S to a memory location pointed by
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// addressing register $D.
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// FIXME: Perform additional operation depending on source register.
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//void DSPEmitter::srr(const UDSPInstruction opc)
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//{
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// u8 dreg = (opc >> 5) & 0x3;
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// u8 sreg = opc & 0x1f;
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void DSPEmitter::srr(const UDSPInstruction opc)
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{
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u8 dreg = (opc >> 5) & 0x3;
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u8 sreg = opc & 0x1f;
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// u16 val = dsp_op_read_reg(sreg);
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// dsp_dmem_write(g_dsp.r[dreg], val);
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//}
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dsp_op_read_reg(sreg, ECX);
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, EAX, M(&g_dsp.r[dreg]));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOVZX(64, 16, RAX, MDisp(R11,dreg*2));
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#endif
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dmem_write();
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}
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// SRRD @$D, $S
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// 0001 1010 1dds ssss
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// Store value from source register $S to a memory location pointed by
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// addressing register $D. Decrement register $D.
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// FIXME: Perform additional operation depending on source register.
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//void DSPEmitter::srrd(const UDSPInstruction opc)
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//{
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// u8 dreg = (opc >> 5) & 0x3;
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// u8 sreg = opc & 0x1f;
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void DSPEmitter::srrd(const UDSPInstruction opc)
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{
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u8 dreg = (opc >> 5) & 0x3;
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u8 sreg = opc & 0x1f;
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// u16 val = dsp_op_read_reg(sreg);
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// dsp_dmem_write(g_dsp.r[dreg], val);
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// g_dsp.r[dreg] = dsp_decrement_addr_reg(dreg);
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//}
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dsp_op_read_reg(sreg, ECX);
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, EAX, M(&g_dsp.r[dreg]));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOVZX(64, 16, RAX, MDisp(R11,dreg*2));
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#endif
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dmem_write();
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decrement_addr_reg(dreg);
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}
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// SRRI @$D, $S
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// 0001 1011 0dds ssss
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// Store value from source register $S to a memory location pointed by
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// addressing register $D. Increment register $D.
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// FIXME: Perform additional operation depending on source register.
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//void DSPEmitter::srri(const UDSPInstruction opc)
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//{
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// u8 dreg = (opc >> 5) & 0x3;
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// u8 sreg = opc & 0x1f;
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void DSPEmitter::srri(const UDSPInstruction opc)
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{
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u8 dreg = (opc >> 5) & 0x3;
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u8 sreg = opc & 0x1f;
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// u16 val = dsp_op_read_reg(sreg);
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// dsp_dmem_write(g_dsp.r[dreg], val);
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// g_dsp.r[dreg] = dsp_increment_addr_reg(dreg);
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//}
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dsp_op_read_reg(sreg, ECX);
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, EAX, M(&g_dsp.r[dreg]));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOVZX(64, 16, RAX, MDisp(R11,dreg*2));
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#endif
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dmem_write();
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increment_addr_reg(dreg);
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}
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// SRRN @$D, $S
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// 0001 1011 1dds ssss
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@ -240,42 +275,78 @@ void DSPEmitter::si(const UDSPInstruction opc)
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// 0000 001d 0001 00ss
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// Move value from instruction memory pointed by addressing register
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// $arS to mid accumulator register $acD.m.
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//void DSPEmitter::ilrr(const UDSPInstruction opc)
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//{
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// u16 reg = opc & 0x3;
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// u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
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void DSPEmitter::ilrr(const UDSPInstruction opc)
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{
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u16 reg = opc & 0x3;
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u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
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// g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]);
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// dsp_conditional_extend_accum(dreg);
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//}
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOVZX(64, 16, RCX, MDisp(R11,reg*2));
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#endif
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imem_read();
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.r[dreg]), R(EAX));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOV(16, MDisp(R11,dreg*2), R(RAX));
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#endif
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dsp_conditional_extend_accum(dreg);
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}
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// ILRRD $acD.m, @$arS
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// 0000 001d 0001 01ss
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// Move value from instruction memory pointed by addressing register
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// $arS to mid accumulator register $acD.m. Decrement addressing register $arS.
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//void DSPEmitter::ilrrd(const UDSPInstruction opc)
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//{
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// u16 reg = opc & 0x3;
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// u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
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void DSPEmitter::ilrrd(const UDSPInstruction opc)
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{
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u16 reg = opc & 0x3;
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u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
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// g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]);
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// dsp_conditional_extend_accum(dreg);
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// g_dsp.r[reg] = dsp_decrement_addr_reg(reg);
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//}
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOVZX(64, 16, RCX, MDisp(R11,reg*2));
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#endif
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imem_read();
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.r[dreg]), R(EAX));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOV(16, MDisp(R11,dreg*2), R(RAX));
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#endif
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dsp_conditional_extend_accum(dreg);
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dsp_decrement_addr_reg(reg);
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}
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// ILRRI $acD.m, @$S
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// 0000 001d 0001 10ss
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// Move value from instruction memory pointed by addressing register
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// $arS to mid accumulator register $acD.m. Increment addressing register $arS.
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//void DSPEmitter::ilrri(const UDSPInstruction opc)
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//{
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// u16 reg = opc & 0x3;
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// u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
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void DSPEmitter::ilrri(const UDSPInstruction opc)
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{
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u16 reg = opc & 0x3;
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u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
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// g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]);
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// dsp_conditional_extend_accum(dreg);
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// g_dsp.r[reg] = dsp_increment_addr_reg(reg);
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//}
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOVZX(64, 16, RCX, MDisp(R11,reg*2));
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#endif
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imem_read();
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.r[dreg]), R(EAX));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOV(16, MDisp(R11,dreg*2), R(RAX));
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#endif
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dsp_conditional_extend_accum(dreg);
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dsp_increment_addr_reg(reg);
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}
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// ILRRN $acD.m, @$arS
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// 0000 001d 0001 11ss
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@ -338,7 +338,12 @@ void DSPEmitter::dmem_write_imm(u16 addr)
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switch (addr >> 12)
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{
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case 0x0: // 0xxx DRAM
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.dram[addr & DSP_DRAM_MASK]), R(ECX));
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#else
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MOV(64, R(RDX), ImmPtr(g_dsp.dram));
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MOV(16, MDisp(RDX,(addr & DSP_DRAM_MASK)*2), R(ECX));
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#endif
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break;
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case 0xf: // Fxxx HW regs
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@ -352,8 +357,40 @@ void DSPEmitter::dmem_write_imm(u16 addr)
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}
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}
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// EAX - the result of the read (used by caller)
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// ECX - the address to read
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// In: ECX - the address to read
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// Out: EAX - the result of the read (used by caller)
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// ESI - Base
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void DSPEmitter::imem_read()
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{
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// if (addr == 0)
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CMP(16, R(ECX), Imm16(0x0fff));
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FixupBranch irom = J_CC(CC_A);
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// return g_dsp.iram[addr & DSP_IRAM_MASK];
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AND(16, R(ECX), Imm16(DSP_IRAM_MASK));
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#ifdef _M_X64
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MOV(64, R(ESI), ImmPtr(g_dsp.iram));
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#else
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MOV(32, R(ESI), ImmPtr(g_dsp.iram));
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#endif
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MOV(16, R(EAX), MComplex(ESI, ECX, 2, 0));
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FixupBranch end = J();
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SetJumpTarget(irom);
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// else if (addr == 0x8)
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// return g_dsp.irom[addr & DSP_IROM_MASK];
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AND(16, R(ECX), Imm16(DSP_IROM_MASK));
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#ifdef _M_X64
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MOV(64, R(ESI), ImmPtr(g_dsp.irom));
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#else
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MOV(32, R(ESI), ImmPtr(g_dsp.irom));
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#endif
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MOV(16, R(EAX), MComplex(ESI,ECX,2,0));
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SetJumpTarget(end);
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}
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// In: ECX - the address to read
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// Out: EAX - the result of the read (used by caller)
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// ESI - Base
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// Trashes R11 on gdsp_ifx_read
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void DSPEmitter::dmem_read()
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@ -399,11 +436,21 @@ void DSPEmitter::dmem_read_imm(u16 addr)
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switch (addr >> 12)
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{
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case 0x0: // 0xxx DRAM
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#ifdef _M_IX86 // All32
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MOV(16, R(EAX), M(&g_dsp.dram[addr & DSP_DRAM_MASK]));
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#else
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MOV(64, R(RDX), ImmPtr(g_dsp.dram));
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MOV(16, R(EAX), MDisp(RDX,(addr & DSP_DRAM_MASK)*2));
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#endif
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break;
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case 0x1: // 1xxx COEF
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#ifdef _M_IX86 // All32
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MOV(16, R(EAX), Imm16(g_dsp.coef[addr & DSP_COEF_MASK]));
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#else
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MOV(64, R(RDX), ImmPtr(g_dsp.coef));
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MOV(16, R(EAX), MDisp(RDX,(addr & DSP_COEF_MASK)*2));
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#endif
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break;
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case 0xf: // Fxxx HW regs
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