mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2025-07-21 05:09:34 -06:00
space changes, merge #defines, language fix, and code reorder/cleanup :P
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@5614 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
luisr142004
@ -17,6 +17,7 @@
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#include <cmath>
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#include "VideoConfig.h"
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#include "Profiler.h"
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#include "Statistics.h"
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#include "Render.h"
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@ -35,8 +36,8 @@ using namespace BPFunctions;
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void BPInit()
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{
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memset(&bpmem, 0, sizeof(bpmem));
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bpmem.bpMask = 0xFFFFFF;
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memset(&bpmem, 0, sizeof(bpmem));
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bpmem.bpMask = 0xFFFFFF;
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}
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void RenderToXFB(const BPCmd &bp, const EFBRectangle &rc, float yScale, float xfbLines, u32 xfbAddr, const u32 dstWidth, const u32 dstHeight)
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@ -46,22 +47,22 @@ void RenderToXFB(const BPCmd &bp, const EFBRectangle &rc, float yScale, float xf
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void BPWritten(const BPCmd& bp)
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{
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/*
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----------------------------------------------------------------------------------------------------------------
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Purpose: Writes to the BP registers
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Called: At the end of every: OpcodeDecoding.cpp ExecuteDisplayList > Decode() > LoadBPReg
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How It Works: First the pipeline is flushed then update the bpmem with the new value.
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Some of the BP cases have to call certain functions while others just update the bpmem.
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some bp cases check the changes variable, because they might not have to be updated all the time
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NOTE: it seems not all bp cases like checking changes, so calling if (bp.changes == 0 ? false : true)
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had to be ditched and the games seem to work fine with out it.
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NOTE2: Yet Another Gamecube Documentation calls them Bypass Raster State Registers but possibly completely wrong
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NOTE3: This controls the register groups: RAS1/2, SU, TF, TEV, C/Z, PEC
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TODO: Turn into function table. The (future) DisplayList (DL) jit can then call the functions directly,
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getting rid of dynamic dispatch. Unfortunately, few games use DLs properly - most\
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just stuff geometry in them and don't put state changes there.
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----------------------------------------------------------------------------------------------------------------
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*/
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/*
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----------------------------------------------------------------------------------------------------------------
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Purpose: Writes to the BP registers
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Called: At the end of every: OpcodeDecoding.cpp ExecuteDisplayList > Decode() > LoadBPReg
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How It Works: First the pipeline is flushed then update the bpmem with the new value.
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Some of the BP cases have to call certain functions while others just update the bpmem.
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some bp cases check the changes variable, because they might not have to be updated all the time
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NOTE: it seems not all bp cases like checking changes, so calling if (bp.changes == 0 ? false : true)
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had to be ditched and the games seem to work fine with out it.
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NOTE2: Yet Another Gamecube Documentation calls them Bypass Raster State Registers but possibly completely wrong
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NOTE3: This controls the register groups: RAS1/2, SU, TF, TEV, C/Z, PEC
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TODO: Turn into function table. The (future) DisplayList (DL) jit can then call the functions directly,
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getting rid of dynamic dispatch. Unfortunately, few games use DLs properly - most\
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just stuff geometry in them and don't put state changes there
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----------------------------------------------------------------------------------------------------------------
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*/
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// Debugging only, this lets you skip a bp update
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//static int times = 0;
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@ -83,13 +84,13 @@ void BPWritten(const BPCmd& bp)
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//s_bpCritical.Enter();
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FlushPipeline();
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((u32*)&bpmem)[bp.address] = bp.newvalue;
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((u32*)&bpmem)[bp.address] = bp.newvalue;
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switch (bp.address)
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{
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case BPMEM_GENMODE: // Set the Generation Mode
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{
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PRIM_LOG("genmode: texgen=%d, col=%d, ms_en=%d, tev=%d, culmode=%d, ind=%d, zfeeze=%d",
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PRIM_LOG("genmode: texgen=%d, col=%d, ms_en=%d, tev=%d, cullmode=%d, ind=%d, zfeeze=%d",
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bpmem.genMode.numtexgens, bpmem.genMode.numcolchans,
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bpmem.genMode.ms_en, bpmem.genMode.numtevstages+1, bpmem.genMode.cullmode,
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bpmem.genMode.numindstages, bpmem.genMode.zfreeze);
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@ -108,9 +109,9 @@ void BPWritten(const BPCmd& bp)
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PixelShaderManager::SetIndMatrixChanged((bp.address - BPMEM_IND_MTXA) / 3);
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break;
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case BPMEM_RAS1_SS0: // Index Texture Coordinate Scale 0
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PixelShaderManager::SetIndTexScaleChanged(0x03);
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PixelShaderManager::SetIndTexScaleChanged(0x03);
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case BPMEM_RAS1_SS1: // Index Texture Coordinate Scale 1
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PixelShaderManager::SetIndTexScaleChanged(0x0c);
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PixelShaderManager::SetIndTexScaleChanged(0x0c);
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break;
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// ----------------
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// Scissor Control
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@ -159,31 +160,31 @@ void BPWritten(const BPCmd& bp)
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// This is called when the game is done drawing the new frame (eg: like in DX: Begin(); Draw(); End();)
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// Triggers an interrupt on the PPC side so that the game knows when the GPU has finished drawing.
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// Tokens are similar.
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case BPMEM_SETDRAWDONE:
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case BPMEM_SETDRAWDONE:
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switch (bp.newvalue & 0xFF)
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{
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case 0x02:
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PixelEngine::SetFinish(); // may generate interrupt
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DEBUG_LOG(VIDEO, "GXSetDrawDone SetPEFinish (value: 0x%02X)", (bp.newvalue & 0xFFFF));
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break;
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{
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case 0x02:
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PixelEngine::SetFinish(); // may generate interrupt
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DEBUG_LOG(VIDEO, "GXSetDrawDone SetPEFinish (value: 0x%02X)", (bp.newvalue & 0xFFFF));
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break;
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default:
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WARN_LOG(VIDEO, "GXSetDrawDone ??? (value 0x%02X)", (bp.newvalue & 0xFFFF));
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break;
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}
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break;
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default:
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WARN_LOG(VIDEO, "GXSetDrawDone ??? (value 0x%02X)", (bp.newvalue & 0xFFFF));
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break;
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}
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break;
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case BPMEM_PE_TOKEN_ID: // Pixel Engine Token ID
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PixelEngine::SetToken(static_cast<u16>(bp.newvalue & 0xFFFF), FALSE);
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DEBUG_LOG(VIDEO, "SetPEToken 0x%04x", (bp.newvalue & 0xFFFF));
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break;
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case BPMEM_PE_TOKEN_INT_ID: // Pixel Engine Interrupt Token ID
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PixelEngine::SetToken(static_cast<u16>(bp.newvalue & 0xFFFF), TRUE);
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DEBUG_LOG(VIDEO, "SetPEToken + INT 0x%04x", (bp.newvalue & 0xFFFF));
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break;
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PixelEngine::SetToken(static_cast<u16>(bp.newvalue & 0xFFFF), FALSE);
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DEBUG_LOG(VIDEO, "SetPEToken 0x%04x", (bp.newvalue & 0xFFFF));
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break;
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case BPMEM_PE_TOKEN_INT_ID: // Pixel Engine Interrupt Token ID
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PixelEngine::SetToken(static_cast<u16>(bp.newvalue & 0xFFFF), TRUE);
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DEBUG_LOG(VIDEO, "SetPEToken + INT 0x%04x", (bp.newvalue & 0xFFFF));
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break;
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// ------------------------
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// EFB copy command. This copies a rectangle from the EFB to either RAM in a texture format or to XFB as YUYV.
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// It can also optionally clear the EFB while copying from it. To emulate this, we of course copy first and clear afterwards.
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case BPMEM_TRIGGER_EFB_COPY: // Copy EFB Region or Render to the XFB or Clear the screen.
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case BPMEM_TRIGGER_EFB_COPY: // Copy EFB Region or Render to the XFB or Clear the screen.
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{
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DVSTARTSUBPROFILE("LoadBPReg:swap");
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// The bottom right is within the rectangle
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@ -200,7 +201,7 @@ void BPWritten(const BPCmd& bp)
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// Check if we are to copy from the EFB or draw to the XFB
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if (PE_copy.copy_to_xfb == 0)
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{
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if (GetConfig(CONFIG_SHOWEFBREGIONS))
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if (GetConfig(CONFIG_SHOWEFBREGIONS))
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stats.efb_regions.push_back(rc);
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CopyEFB(bp, rc, bpmem.copyTexDest << 5,
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@ -244,21 +245,21 @@ void BPWritten(const BPCmd& bp)
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}
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RestoreRenderState(bp);
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break;
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}
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case BPMEM_LOADTLUT0: // This one updates bpmem.tlutXferSrc, no need to do anything here.
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break;
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case BPMEM_LOADTLUT1: // Load a Texture Look Up Table
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{
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DVSTARTSUBPROFILE("LoadBPReg:GXLoadTlut");
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{
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DVSTARTSUBPROFILE("LoadBPReg:GXLoadTlut");
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u32 tlutTMemAddr = (bp.newvalue & 0x3FF) << 9;
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u32 tlutXferCount = (bp.newvalue & 0x1FFC00) >> 5;
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u32 tlutTMemAddr = (bp.newvalue & 0x3FF) << 9;
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u32 tlutXferCount = (bp.newvalue & 0x1FFC00) >> 5;
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u8 *ptr = 0;
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// TODO - figure out a cleaner way.
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// TODO - figure out a cleaner way.
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if (GetConfig(CONFIG_ISWII))
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ptr = GetPointer(bpmem.tlutXferSrc << 5);
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else
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@ -269,10 +270,10 @@ void BPWritten(const BPCmd& bp)
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else
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PanicAlert("Invalid palette pointer %08x %08x %08x", bpmem.tlutXferSrc, bpmem.tlutXferSrc << 5, (bpmem.tlutXferSrc & 0xFFFFF)<< 5);
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// TODO(ector) : kill all textures that use this palette
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// Not sure if it's a good idea, though. For now, we hash texture palettes
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// TODO(ector) : kill all textures that use this palette
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// Not sure if it's a good idea, though. For now, we hash texture palettes
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break;
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}
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}
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case BPMEM_FOGRANGE: // Fog Settings Control
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case BPMEM_FOGRANGE+1:
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case BPMEM_FOGRANGE+2:
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@ -293,15 +294,15 @@ void BPWritten(const BPCmd& bp)
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case BPMEM_ALPHACOMPARE: // Compare Alpha Values
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PRIM_LOG("alphacmp: ref0=%d, ref1=%d, comp0=%d, comp1=%d, logic=%d", bpmem.alphaFunc.ref0,
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bpmem.alphaFunc.ref1, bpmem.alphaFunc.comp0, bpmem.alphaFunc.comp1, bpmem.alphaFunc.logic);
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PixelShaderManager::SetAlpha(bpmem.alphaFunc);
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PixelShaderManager::SetAlpha(bpmem.alphaFunc);
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break;
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case BPMEM_BIAS: // BIAS
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PRIM_LOG("ztex bias=0x%x", bpmem.ztex1.bias);
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PixelShaderManager::SetZTextureBias(bpmem.ztex1.bias);
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PixelShaderManager::SetZTextureBias(bpmem.ztex1.bias);
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break;
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case BPMEM_ZTEX2: // Z Texture type
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{
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if (bp.changes & 3)
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if (bp.changes & 3)
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PixelShaderManager::SetZTextureTypeChanged();
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#if defined(_DEBUG) || defined(DEBUGFAST)
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const char* pzop[] = {"DISABLE", "ADD", "REPLACE", "?"};
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@ -381,8 +382,8 @@ void BPWritten(const BPCmd& bp)
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}
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#endif
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break;
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}
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case BPMEM_TEXINVALIDATE: // Used, if game has manual control the Texture Cache, which we don't allow
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}
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case BPMEM_TEXINVALIDATE: // Used, if game has manual control the Texture Cache, which we don't allow
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DEBUG_LOG(VIDEO, "BP Texture Invalid: %08x", bp.newvalue);
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case BPMEM_ZCOMPARE: // Set the Z-Compare and EFB pixel format
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case BPMEM_MIPMAP_STRIDE: // MipMap Stride Channel
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@ -395,7 +396,7 @@ void BPWritten(const BPCmd& bp)
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9 BC1 - Ind. Tex Stage 1 NTexCoord
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6 BI1 - Ind. Tex Stage 1 NTexMap
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3 BC0 - Ind. Tex Stage 0 NTexCoord
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0 BI0 - Ind. Tex Stage 0 NTexMap */
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0 BI0 - Ind. Tex Stage 0 NTexMap*/
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case BPMEM_TEV_KSEL: // Texture Environment Swap Mode Table 0
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case BPMEM_TEV_KSEL+1:// Texture Environment Swap Mode Table 1
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case BPMEM_TEV_KSEL+2:// Texture Environment Swap Mode Table 2
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@ -405,7 +406,7 @@ void BPWritten(const BPCmd& bp)
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case BPMEM_TEV_KSEL+6:// Texture Environment Swap Mode Table 6
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case BPMEM_TEV_KSEL+7:// Texture Environment Swap Mode Table 7
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case BPMEM_BP_MASK: // This Register can be used to limit to which bits of BP registers is actually written to. the mask is
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// only valid for the next BP command, and will reset itself.
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// only valid for the next BP command, and will reset itself.
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case BPMEM_IND_IMASK: // Index Mask ?
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case BPMEM_REVBITS: // Always set to 0x0F when GX_InitRevBits() is called.
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break;
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@ -439,7 +440,7 @@ void BPWritten(const BPCmd& bp)
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break;
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// ----------------------
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// Set wrap size
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// ----------------------
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// ----------------------
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case BPMEM_SU_SSIZE:
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case BPMEM_SU_TSIZE:
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case BPMEM_SU_SSIZE+2:
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@ -456,12 +457,12 @@ void BPWritten(const BPCmd& bp)
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case BPMEM_SU_TSIZE+12:
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case BPMEM_SU_SSIZE+14:
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case BPMEM_SU_TSIZE+14:
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PixelShaderManager::SetTexCoordChanged((bp.address - BPMEM_SU_SSIZE) >> 1);
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PixelShaderManager::SetTexCoordChanged((bp.address - BPMEM_SU_SSIZE) >> 1);
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break;
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// ------------------------
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// BPMEM_TX_SETMODE0 - (Texture lookup and filtering mode) LOD/BIAS Clamp, MaxAnsio, LODBIAS, DiagLoad, Min Filter, Mag Filter, Wrap T, S
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// BPMEM_TX_SETMODE1 - (LOD Stuff) - Max LOD, Min LOD
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// ------------------------
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// ------------------------
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case BPMEM_TX_SETMODE0: // (0x90 for linear)
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case BPMEM_TX_SETMODE0_4:
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// Shouldn't need to call this here, we call it for each active texture right before rendering
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@ -476,7 +477,7 @@ void BPWritten(const BPCmd& bp)
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// BPMEM_TX_SETIMAGE1 - even LOD address in TMEM - Image Type, Cache Height, Cache Width, TMEM Offset
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// BPMEM_TX_SETIMAGE2 - odd LOD address in TMEM - Cache Height, Cache Width, TMEM Offset
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// BPMEM_TX_SETIMAGE3 - Address of Texture in main memory
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// --------------------------------------------
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// --------------------------------------------
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case BPMEM_TX_SETIMAGE0:
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case BPMEM_TX_SETIMAGE0_4:
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case BPMEM_TX_SETIMAGE1:
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@ -489,14 +490,14 @@ void BPWritten(const BPCmd& bp)
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// -------------------------------
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// Set a TLUT
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// BPMEM_TX_SETTLUT - Format, TMEM Offset (offset of TLUT from start of TMEM high bank > > 5)
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// -------------------------------
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// -------------------------------
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case BPMEM_TX_SETTLUT:
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case BPMEM_TX_SETLUT_4:
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break;
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// ---------------------------------------------------
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// Set the TEV Color
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// ---------------------------------------------------
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// ---------------------------------------------------
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case BPMEM_TEV_REGISTER_L: // Reg 1
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case BPMEM_TEV_REGISTER_H:
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case BPMEM_TEV_REGISTER_L+2: // Reg 2
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