diff --git a/Source/Core/Core/HW/GPFifo.cpp b/Source/Core/Core/HW/GPFifo.cpp index 564295ecf3..7c0e4d2805 100644 --- a/Source/Core/Core/HW/GPFifo.cpp +++ b/Source/Core/Core/HW/GPFifo.cpp @@ -89,7 +89,7 @@ void UpdateGatherPipe() size_t pipe_count = GetGatherPipeCount(); size_t processed; - u8* cur_mem = memory.GetPointer(processor_interface.Fifo_CPUWritePointer); + u8* cur_mem = memory.GetPointer(processor_interface.m_fifo_cpu_write_pointer); for (processed = 0; pipe_count >= GATHER_PIPE_SIZE; processed += GATHER_PIPE_SIZE) { // copy the GatherPipe @@ -97,15 +97,15 @@ void UpdateGatherPipe() pipe_count -= GATHER_PIPE_SIZE; // increase the CPUWritePointer - if (processor_interface.Fifo_CPUWritePointer == processor_interface.Fifo_CPUEnd) + if (processor_interface.m_fifo_cpu_write_pointer == processor_interface.m_fifo_cpu_end) { - processor_interface.Fifo_CPUWritePointer = processor_interface.Fifo_CPUBase; - cur_mem = memory.GetPointer(processor_interface.Fifo_CPUWritePointer); + processor_interface.m_fifo_cpu_write_pointer = processor_interface.m_fifo_cpu_base; + cur_mem = memory.GetPointer(processor_interface.m_fifo_cpu_write_pointer); } else { cur_mem += GATHER_PIPE_SIZE; - processor_interface.Fifo_CPUWritePointer += GATHER_PIPE_SIZE; + processor_interface.m_fifo_cpu_write_pointer += GATHER_PIPE_SIZE; } system.GetCommandProcessor().GatherPipeBursted(system); diff --git a/Source/Core/Core/HW/ProcessorInterface.cpp b/Source/Core/Core/HW/ProcessorInterface.cpp index 165487a0a5..ebb7a9620f 100644 --- a/Source/Core/Core/HW/ProcessorInterface.cpp +++ b/Source/Core/Core/HW/ProcessorInterface.cpp @@ -29,59 +29,60 @@ constexpr u32 FLIPPER_REV_C = 0x246500B1; void ProcessorInterfaceManager::DoState(PointerWrap& p) { - p.Do(m_InterruptMask); - p.Do(m_InterruptCause); - p.Do(Fifo_CPUBase); - p.Do(Fifo_CPUEnd); - p.Do(Fifo_CPUWritePointer); - p.Do(m_ResetCode); + p.Do(m_interrupt_mask); + p.Do(m_interrupt_cause); + p.Do(m_fifo_cpu_base); + p.Do(m_fifo_cpu_end); + p.Do(m_fifo_cpu_write_pointer); + p.Do(m_reset_code); } void ProcessorInterfaceManager::Init() { - m_InterruptMask = 0; - m_InterruptCause = 0; + m_interrupt_mask = 0; + m_interrupt_cause = 0; - Fifo_CPUBase = 0; - Fifo_CPUEnd = 0; - Fifo_CPUWritePointer = 0; + m_fifo_cpu_base = 0; + m_fifo_cpu_end = 0; + m_fifo_cpu_write_pointer = 0; - m_ResetCode = 0; // Cold reset - m_InterruptCause = INT_CAUSE_RST_BUTTON | INT_CAUSE_VI; + m_reset_code = 0; // Cold reset + m_interrupt_cause = INT_CAUSE_RST_BUTTON | INT_CAUSE_VI; auto& system = Core::System::GetInstance(); auto& core_timing = system.GetCoreTiming(); - toggleResetButton = core_timing.RegisterEvent("ToggleResetButton", ToggleResetButtonCallback); - iosNotifyResetButton = + m_event_type_toggle_reset_button = + core_timing.RegisterEvent("ToggleResetButton", ToggleResetButtonCallback); + m_event_type_ios_notify_reset_button = core_timing.RegisterEvent("IOSNotifyResetButton", IOSNotifyResetButtonCallback); - iosNotifyPowerButton = + m_event_type_ios_notify_power_button = core_timing.RegisterEvent("IOSNotifyPowerButton", IOSNotifyPowerButtonCallback); } void ProcessorInterfaceManager::RegisterMMIO(MMIO::Mapping* mmio, u32 base) { - mmio->Register(base | PI_INTERRUPT_CAUSE, MMIO::DirectRead(&m_InterruptCause), + mmio->Register(base | PI_INTERRUPT_CAUSE, MMIO::DirectRead(&m_interrupt_cause), MMIO::ComplexWrite([](Core::System& system, u32, u32 val) { auto& processor_interface = system.GetProcessorInterface(); - processor_interface.m_InterruptCause &= ~val; + processor_interface.m_interrupt_cause &= ~val; processor_interface.UpdateException(); })); - mmio->Register(base | PI_INTERRUPT_MASK, MMIO::DirectRead(&m_InterruptMask), + mmio->Register(base | PI_INTERRUPT_MASK, MMIO::DirectRead(&m_interrupt_mask), MMIO::ComplexWrite([](Core::System& system, u32, u32 val) { auto& processor_interface = system.GetProcessorInterface(); - processor_interface.m_InterruptMask = val; + processor_interface.m_interrupt_mask = val; processor_interface.UpdateException(); })); - mmio->Register(base | PI_FIFO_BASE, MMIO::DirectRead(&Fifo_CPUBase), - MMIO::DirectWrite(&Fifo_CPUBase, 0xFFFFFFE0)); + mmio->Register(base | PI_FIFO_BASE, MMIO::DirectRead(&m_fifo_cpu_base), + MMIO::DirectWrite(&m_fifo_cpu_base, 0xFFFFFFE0)); - mmio->Register(base | PI_FIFO_END, MMIO::DirectRead(&Fifo_CPUEnd), - MMIO::DirectWrite(&Fifo_CPUEnd, 0xFFFFFFE0)); + mmio->Register(base | PI_FIFO_END, MMIO::DirectRead(&m_fifo_cpu_end), + MMIO::DirectWrite(&m_fifo_cpu_end, 0xFFFFFFE0)); - mmio->Register(base | PI_FIFO_WPTR, MMIO::DirectRead(&Fifo_CPUWritePointer), - MMIO::DirectWrite(&Fifo_CPUWritePointer, 0xFFFFFFE0)); + mmio->Register(base | PI_FIFO_WPTR, MMIO::DirectRead(&m_fifo_cpu_write_pointer), + MMIO::DirectWrite(&m_fifo_cpu_write_pointer, 0xFFFFFFE0)); mmio->Register(base | PI_FIFO_RESET, MMIO::InvalidRead(), MMIO::ComplexWrite([](Core::System&, u32, u32 val) { @@ -109,15 +110,15 @@ void ProcessorInterfaceManager::RegisterMMIO(MMIO::Mapping* mmio, u32 base) mmio->Register(base | PI_RESET_CODE, MMIO::ComplexRead([](Core::System& system, u32) { auto& processor_interface = system.GetProcessorInterface(); DEBUG_LOG_FMT(PROCESSORINTERFACE, "Read PI_RESET_CODE: {:08x}", - processor_interface.m_ResetCode); - return processor_interface.m_ResetCode; + processor_interface.m_reset_code); + return processor_interface.m_reset_code; }), MMIO::ComplexWrite([](Core::System& system, u32, u32 val) { auto& processor_interface = system.GetProcessorInterface(); - processor_interface.m_ResetCode = val; + processor_interface.m_reset_code = val; INFO_LOG_FMT(PROCESSORINTERFACE, "Wrote PI_RESET_CODE: {:08x}", - processor_interface.m_ResetCode); - if (!SConfig::GetInstance().bWii && ~processor_interface.m_ResetCode & 0x4) + processor_interface.m_reset_code); + if (!SConfig::GetInstance().bWii && ~processor_interface.m_reset_code & 0x4) { DVDInterface::ResetDrive(true); } @@ -138,7 +139,7 @@ void ProcessorInterfaceManager::RegisterMMIO(MMIO::Mapping* mmio, u32 base) void ProcessorInterfaceManager::UpdateException() { - if ((m_InterruptCause & m_InterruptMask) != 0) + if ((m_interrupt_cause & m_interrupt_mask) != 0) PowerPC::ppcState.Exceptions |= EXCEPTION_EXTERNAL_INT; else PowerPC::ppcState.Exceptions &= ~EXCEPTION_EXTERNAL_INT; @@ -189,22 +190,22 @@ void ProcessorInterfaceManager::SetInterrupt(u32 cause_mask, bool set) { DEBUG_ASSERT_MSG(POWERPC, Core::IsCPUThread(), "SetInterrupt from wrong thread"); - if (set && !(m_InterruptCause & cause_mask)) + if (set && !(m_interrupt_cause & cause_mask)) { DEBUG_LOG_FMT(PROCESSORINTERFACE, "Setting Interrupt {} (set)", Debug_GetInterruptName(cause_mask)); } - if (!set && (m_InterruptCause & cause_mask)) + if (!set && (m_interrupt_cause & cause_mask)) { DEBUG_LOG_FMT(PROCESSORINTERFACE, "Setting Interrupt {} (clear)", Debug_GetInterruptName(cause_mask)); } if (set) - m_InterruptCause |= cause_mask; + m_interrupt_cause |= cause_mask; else - m_InterruptCause &= ~cause_mask; // is there any reason to have this possibility? + m_interrupt_cause &= ~cause_mask; // is there any reason to have this possibility? // F|RES: i think the hw devices reset the interrupt in the PI to 0 // if the interrupt cause is eliminated. that isn't done by software (afaik) UpdateException(); @@ -252,10 +253,11 @@ void ProcessorInterfaceManager::ResetButton_Tap() auto& system = Core::System::GetInstance(); auto& core_timing = system.GetCoreTiming(); - core_timing.ScheduleEvent(0, toggleResetButton, true, CoreTiming::FromThread::ANY); - core_timing.ScheduleEvent(0, iosNotifyResetButton, 0, CoreTiming::FromThread::ANY); - core_timing.ScheduleEvent(SystemTimers::GetTicksPerSecond() / 2, toggleResetButton, false, + core_timing.ScheduleEvent(0, m_event_type_toggle_reset_button, true, CoreTiming::FromThread::ANY); + core_timing.ScheduleEvent(0, m_event_type_ios_notify_reset_button, 0, CoreTiming::FromThread::ANY); + core_timing.ScheduleEvent(SystemTimers::GetTicksPerSecond() / 2, m_event_type_toggle_reset_button, + false, CoreTiming::FromThread::ANY); } void ProcessorInterfaceManager::PowerButton_Tap() @@ -265,7 +267,8 @@ void ProcessorInterfaceManager::PowerButton_Tap() auto& system = Core::System::GetInstance(); auto& core_timing = system.GetCoreTiming(); - core_timing.ScheduleEvent(0, iosNotifyPowerButton, 0, CoreTiming::FromThread::ANY); + core_timing.ScheduleEvent(0, m_event_type_ios_notify_power_button, 0, + CoreTiming::FromThread::ANY); } } // namespace ProcessorInterface diff --git a/Source/Core/Core/HW/ProcessorInterface.h b/Source/Core/Core/HW/ProcessorInterface.h index 8655b80cc5..a0994ddf54 100644 --- a/Source/Core/Core/HW/ProcessorInterface.h +++ b/Source/Core/Core/HW/ProcessorInterface.h @@ -68,8 +68,8 @@ public: void RegisterMMIO(MMIO::Mapping* mmio, u32 base); - u32 GetMask() const { return m_InterruptMask; } - u32 GetCause() const { return m_InterruptCause; } + u32 GetMask() const { return m_interrupt_mask; } + u32 GetCause() const { return m_interrupt_cause; } void SetInterrupt(u32 cause_mask, bool set = true); @@ -77,13 +77,13 @@ public: void ResetButton_Tap(); void PowerButton_Tap(); - u32 m_InterruptCause = 0; - u32 m_InterruptMask = 0; + u32 m_interrupt_cause = 0; + u32 m_interrupt_mask = 0; // addresses for CPU fifo accesses - u32 Fifo_CPUBase = 0; - u32 Fifo_CPUEnd = 0; - u32 Fifo_CPUWritePointer = 0; + u32 m_fifo_cpu_base = 0; + u32 m_fifo_cpu_end = 0; + u32 m_fifo_cpu_write_pointer = 0; private: // Let the PPC know that an external exception is set/cleared @@ -96,10 +96,10 @@ private: static void IOSNotifyResetButtonCallback(Core::System& system, u64 userdata, s64 cyclesLate); static void IOSNotifyPowerButtonCallback(Core::System& system, u64 userdata, s64 cyclesLate); - CoreTiming::EventType* toggleResetButton = nullptr; - CoreTiming::EventType* iosNotifyResetButton = nullptr; - CoreTiming::EventType* iosNotifyPowerButton = nullptr; + CoreTiming::EventType* m_event_type_toggle_reset_button = nullptr; + CoreTiming::EventType* m_event_type_ios_notify_reset_button = nullptr; + CoreTiming::EventType* m_event_type_ios_notify_power_button = nullptr; - u32 m_ResetCode = 0; + u32 m_reset_code = 0; }; } // namespace ProcessorInterface diff --git a/Source/Core/Core/PowerPC/Jit64/Jit.cpp b/Source/Core/Core/PowerPC/Jit64/Jit.cpp index 1caaac3b52..2c7aeee92b 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit.cpp @@ -1045,7 +1045,7 @@ bool Jit64::DoJit(u32 em_address, JitBlock* b, u32 nextPC) TEST(32, PPCSTATE(msr), Imm32(0x0008000)); FixupBranch noExtIntEnable = J_CC(CC_Z, true); auto& system = Core::System::GetInstance(); - MOV(64, R(RSCRATCH), ImmPtr(&system.GetProcessorInterface().m_InterruptCause)); + MOV(64, R(RSCRATCH), ImmPtr(&system.GetProcessorInterface().m_interrupt_cause)); TEST(32, MatR(RSCRATCH), Imm32(ProcessorInterface::INT_CAUSE_CP | ProcessorInterface::INT_CAUSE_PE_TOKEN | ProcessorInterface::INT_CAUSE_PE_FINISH)); diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp index cd19603601..912bb6e603 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp @@ -453,7 +453,7 @@ void Jit64::mtmsr(UGeckoInstruction inst) // Check if a CP interrupt is waiting and keep the GPU emulation in sync (issue 4336) auto& system = Core::System::GetInstance(); - MOV(64, R(RSCRATCH), ImmPtr(&system.GetProcessorInterface().m_InterruptCause)); + MOV(64, R(RSCRATCH), ImmPtr(&system.GetProcessorInterface().m_interrupt_cause)); TEST(32, MatR(RSCRATCH), Imm32(ProcessorInterface::INT_CAUSE_CP)); FixupBranch cpInt = J_CC(CC_NZ); diff --git a/Source/Core/Core/PowerPC/JitArm64/Jit.cpp b/Source/Core/Core/PowerPC/JitArm64/Jit.cpp index 036c63af74..3ed46c1482 100644 --- a/Source/Core/Core/PowerPC/JitArm64/Jit.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/Jit.cpp @@ -981,7 +981,7 @@ bool JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC) TBZ(ARM64Reg::W30, 15, done_here); // MSR.EE auto& system = Core::System::GetInstance(); LDR(IndexType::Unsigned, ARM64Reg::W30, ARM64Reg::X30, - MOVPage2R(ARM64Reg::X30, &system.GetProcessorInterface().m_InterruptCause)); + MOVPage2R(ARM64Reg::X30, &system.GetProcessorInterface().m_interrupt_cause)); constexpr u32 cause_mask = ProcessorInterface::INT_CAUSE_CP | ProcessorInterface::INT_CAUSE_PE_TOKEN | ProcessorInterface::INT_CAUSE_PE_FINISH; @@ -1018,7 +1018,7 @@ bool JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC) TBZ(WA, 15, done_here); // MSR.EE auto& system = Core::System::GetInstance(); LDR(IndexType::Unsigned, WA, XA, - MOVPage2R(XA, &system.GetProcessorInterface().m_InterruptCause)); + MOVPage2R(XA, &system.GetProcessorInterface().m_interrupt_cause)); constexpr u32 cause_mask = ProcessorInterface::INT_CAUSE_CP | ProcessorInterface::INT_CAUSE_PE_TOKEN | ProcessorInterface::INT_CAUSE_PE_FINISH; diff --git a/Source/Core/VideoCommon/CommandProcessor.cpp b/Source/Core/VideoCommon/CommandProcessor.cpp index b6bb1bb20d..1d38b27e86 100644 --- a/Source/Core/VideoCommon/CommandProcessor.cpp +++ b/Source/Core/VideoCommon/CommandProcessor.cpp @@ -372,8 +372,8 @@ void CommandProcessorManager::GatherPipeBursted(Core::System& system) { // In multibuffer mode is not allowed write in the same FIFO attached to the GPU. // Fix Pokemon XD in DC mode. - if ((processor_interface.Fifo_CPUEnd == fifo.CPEnd.load(std::memory_order_relaxed)) && - (processor_interface.Fifo_CPUBase == fifo.CPBase.load(std::memory_order_relaxed)) && + if ((processor_interface.m_fifo_cpu_end == fifo.CPEnd.load(std::memory_order_relaxed)) && + (processor_interface.m_fifo_cpu_base == fifo.CPBase.load(std::memory_order_relaxed)) && fifo.CPReadWriteDistance.load(std::memory_order_relaxed) > 0) { system.GetFifo().FlushGpu(system); @@ -396,9 +396,10 @@ void CommandProcessorManager::GatherPipeBursted(Core::System& system) if (m_cp_ctrl_reg.GPReadEnable && m_cp_ctrl_reg.GPLinkEnable) { - processor_interface.Fifo_CPUWritePointer = fifo.CPWritePointer.load(std::memory_order_relaxed); - processor_interface.Fifo_CPUBase = fifo.CPBase.load(std::memory_order_relaxed); - processor_interface.Fifo_CPUEnd = fifo.CPEnd.load(std::memory_order_relaxed); + processor_interface.m_fifo_cpu_write_pointer = + fifo.CPWritePointer.load(std::memory_order_relaxed); + processor_interface.m_fifo_cpu_base = fifo.CPBase.load(std::memory_order_relaxed); + processor_interface.m_fifo_cpu_end = fifo.CPEnd.load(std::memory_order_relaxed); } // If the game is running close to overflowing, make the exception checking more frequent. @@ -418,13 +419,13 @@ void CommandProcessorManager::GatherPipeBursted(Core::System& system) // check if we are in sync ASSERT_MSG(COMMANDPROCESSOR, fifo.CPWritePointer.load(std::memory_order_relaxed) == - processor_interface.Fifo_CPUWritePointer, + processor_interface.m_fifo_cpu_write_pointer, "FIFOs linked but out of sync"); ASSERT_MSG(COMMANDPROCESSOR, - fifo.CPBase.load(std::memory_order_relaxed) == processor_interface.Fifo_CPUBase, + fifo.CPBase.load(std::memory_order_relaxed) == processor_interface.m_fifo_cpu_base, "FIFOs linked but out of sync"); ASSERT_MSG(COMMANDPROCESSOR, - fifo.CPEnd.load(std::memory_order_relaxed) == processor_interface.Fifo_CPUEnd, + fifo.CPEnd.load(std::memory_order_relaxed) == processor_interface.m_fifo_cpu_end, "FIFOs linked but out of sync"); }