From 34dbfd92db681bb5ec826df65260e65a79d6593d Mon Sep 17 00:00:00 2001 From: Sintendo Date: Tue, 26 Jan 2021 22:16:00 +0100 Subject: [PATCH] Jit64: boolX - Special case and with 0 Bitwise and with zero is always zero. Before: 45 8B F8 mov r15d,r8d 41 83 E7 00 and r15d,0 After: Nothing, register a is set to constant 0. --- .../Core/Core/PowerPC/Jit64/Jit_Integer.cpp | 42 +++++++++++-------- 1 file changed, 24 insertions(+), 18 deletions(-) diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp index 5c33e3e8b6..def501d988 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp @@ -714,27 +714,33 @@ void Jit64::boolX(UGeckoInstruction inst) } else if (is_and) { - RCOpArg Rj = gpr.Use(j, RCMode::Read); - RCX64Reg Ra = gpr.Bind(a, RCMode::Write); - RegCache::Realize(Rj, Ra); - - if (complement_b) - { - if (a != j) - MOV(32, Ra, Rj); - NOT(32, Ra); - AND(32, Ra, Imm32(imm)); - } + if (imm == 0) + gpr.SetImmediate32(a, final_not ? 0xFFFFFFFF : 0); else { - if (a != j) - MOV(32, Ra, Rj); - AND(32, Ra, Imm32(imm)); - } + RCOpArg Rj = gpr.Use(j, RCMode::Read); + RCX64Reg Ra = gpr.Bind(a, RCMode::Write); + RegCache::Realize(Rj, Ra); - if (final_not) { - NOT(32, Ra); - needs_test = true; + if (complement_b) + { + if (a != j) + MOV(32, Ra, Rj); + NOT(32, Ra); + AND(32, Ra, Imm32(imm)); + } + else + { + if (a != j) + MOV(32, Ra, Rj); + AND(32, Ra, Imm32(imm)); + } + + if (final_not) + { + NOT(32, Ra); + needs_test = true; + } } } else if (is_or)