mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2025-07-24 22:59:47 -06:00
Reformat all the things. Have fun with merge conflicts.
This commit is contained in:
Pierre Bourdon
@ -6,236 +6,228 @@
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bool DisassembleMov(const unsigned char* codePtr, InstructionInfo* info)
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{
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unsigned const char* startCodePtr = codePtr;
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u8 rex = 0;
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u32 opcode;
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int opcode_length;
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unsigned const char* startCodePtr = codePtr;
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u8 rex = 0;
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u32 opcode;
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int opcode_length;
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//Check for regular prefix
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info->operandSize = 4;
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info->zeroExtend = false;
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info->signExtend = false;
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info->hasImmediate = false;
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info->isMemoryWrite = false;
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info->byteSwap = false;
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// Check for regular prefix
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info->operandSize = 4;
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info->zeroExtend = false;
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info->signExtend = false;
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info->hasImmediate = false;
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info->isMemoryWrite = false;
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info->byteSwap = false;
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u8 modRMbyte = 0;
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u8 sibByte = 0;
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bool hasModRM = false;
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u8 modRMbyte = 0;
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u8 sibByte = 0;
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bool hasModRM = false;
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int displacementSize = 0;
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int displacementSize = 0;
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if (*codePtr == 0x66)
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{
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info->operandSize = 2;
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codePtr++;
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}
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else if (*codePtr == 0x67)
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{
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codePtr++;
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}
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if (*codePtr == 0x66)
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{
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info->operandSize = 2;
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codePtr++;
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}
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else if (*codePtr == 0x67)
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{
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codePtr++;
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}
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//Check for REX prefix
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if ((*codePtr & 0xF0) == 0x40)
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{
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rex = *codePtr;
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if (rex & 8) //REX.W
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{
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info->operandSize = 8;
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}
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codePtr++;
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}
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// Check for REX prefix
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if ((*codePtr & 0xF0) == 0x40)
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{
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rex = *codePtr;
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if (rex & 8) // REX.W
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{
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info->operandSize = 8;
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}
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codePtr++;
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}
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opcode = *codePtr++;
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opcode_length = 1;
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if (opcode == 0x0F)
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{
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opcode = (opcode << 8) | *codePtr++;
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opcode_length = 2;
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if ((opcode & 0xFB) == 0x38)
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{
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opcode = (opcode << 8) | *codePtr++;
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opcode_length = 3;
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}
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}
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opcode = *codePtr++;
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opcode_length = 1;
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if (opcode == 0x0F)
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{
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opcode = (opcode << 8) | *codePtr++;
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opcode_length = 2;
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if ((opcode & 0xFB) == 0x38)
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{
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opcode = (opcode << 8) | *codePtr++;
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opcode_length = 3;
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}
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}
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switch (opcode_length)
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{
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case 1:
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if ((opcode & 0xF0) == 0x80 ||
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((opcode & 0xF8) == 0xC0 && (opcode & 0x0E) != 0x02))
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{
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modRMbyte = *codePtr++;
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hasModRM = true;
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}
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break;
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case 2:
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if (((opcode & 0xF0) == 0x00 && (opcode & 0x0F) >= 0x04 && (opcode & 0x0D) != 0x0D) ||
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((opcode & 0xF0) == 0xA0 && (opcode & 0x07) <= 0x02) ||
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(opcode & 0xF0) == 0x30 ||
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(opcode & 0xFF) == 0x77 ||
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(opcode & 0xF0) == 0x80 ||
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(opcode & 0xF8) == 0xC8)
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{
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// No mod R/M byte
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}
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else
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{
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modRMbyte = *codePtr++;
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hasModRM = true;
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}
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break;
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case 3:
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// TODO: support more 3-byte opcode instructions
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if ((opcode & 0xFE) == 0xF0)
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{
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modRMbyte = *codePtr++;
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hasModRM = true;
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}
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break;
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}
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switch (opcode_length)
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{
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case 1:
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if ((opcode & 0xF0) == 0x80 || ((opcode & 0xF8) == 0xC0 && (opcode & 0x0E) != 0x02))
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{
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modRMbyte = *codePtr++;
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hasModRM = true;
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}
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break;
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case 2:
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if (((opcode & 0xF0) == 0x00 && (opcode & 0x0F) >= 0x04 && (opcode & 0x0D) != 0x0D) ||
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((opcode & 0xF0) == 0xA0 && (opcode & 0x07) <= 0x02) || (opcode & 0xF0) == 0x30 ||
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(opcode & 0xFF) == 0x77 || (opcode & 0xF0) == 0x80 || (opcode & 0xF8) == 0xC8)
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{
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// No mod R/M byte
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}
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else
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{
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modRMbyte = *codePtr++;
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hasModRM = true;
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}
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break;
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case 3:
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// TODO: support more 3-byte opcode instructions
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if ((opcode & 0xFE) == 0xF0)
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{
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modRMbyte = *codePtr++;
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hasModRM = true;
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}
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break;
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}
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if (hasModRM)
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{
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ModRM mrm(modRMbyte, rex);
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info->regOperandReg = mrm.reg;
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if (mrm.mod < 3)
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{
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if (mrm.rm == 4)
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{
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//SIB byte
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sibByte = *codePtr++;
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info->scaledReg = (sibByte >> 3) & 7;
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info->otherReg = (sibByte & 7);
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if (rex & 2) info->scaledReg += 8;
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if (rex & 1) info->otherReg += 8;
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}
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else
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{
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//info->scaledReg =
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}
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}
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if (mrm.mod == 1 || mrm.mod == 2)
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{
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if (mrm.mod == 1)
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displacementSize = 1;
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else
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displacementSize = 4;
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}
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}
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if (hasModRM)
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{
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ModRM mrm(modRMbyte, rex);
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info->regOperandReg = mrm.reg;
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if (mrm.mod < 3)
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{
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if (mrm.rm == 4)
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{
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// SIB byte
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sibByte = *codePtr++;
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info->scaledReg = (sibByte >> 3) & 7;
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info->otherReg = (sibByte & 7);
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if (rex & 2)
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info->scaledReg += 8;
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if (rex & 1)
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info->otherReg += 8;
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}
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else
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{
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// info->scaledReg =
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}
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}
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if (mrm.mod == 1 || mrm.mod == 2)
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{
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if (mrm.mod == 1)
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displacementSize = 1;
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else
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displacementSize = 4;
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}
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}
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if (displacementSize == 1)
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info->displacement = (s32)(s8)*codePtr;
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else
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info->displacement = *((s32*)codePtr);
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codePtr += displacementSize;
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if (displacementSize == 1)
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info->displacement = (s32)(s8)*codePtr;
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else
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info->displacement = *((s32*)codePtr);
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codePtr += displacementSize;
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switch (opcode)
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{
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case 0xC6: // mem <- imm8
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info->isMemoryWrite = true;
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info->hasImmediate = true;
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info->immediate = *codePtr;
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info->operandSize = 1;
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codePtr++;
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break;
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switch (opcode)
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{
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case 0xC6: // mem <- imm8
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info->isMemoryWrite = true;
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info->hasImmediate = true;
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info->immediate = *codePtr;
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info->operandSize = 1;
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codePtr++;
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break;
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case 0xC7: // mem <- imm16/32
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info->isMemoryWrite = true;
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switch (info->operandSize)
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{
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case 2:
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info->hasImmediate = true;
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info->immediate = *(u16*)codePtr;
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codePtr += 2;
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break;
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case 0xC7: // mem <- imm16/32
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info->isMemoryWrite = true;
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switch (info->operandSize)
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{
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case 2:
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info->hasImmediate = true;
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info->immediate = *(u16*)codePtr;
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codePtr += 2;
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break;
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case 4:
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info->hasImmediate = true;
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info->immediate = *(u32*)codePtr;
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codePtr += 4;
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break;
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case 4:
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info->hasImmediate = true;
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info->immediate = *(u32*)codePtr;
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codePtr += 4;
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break;
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case 8:
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info->zeroExtend = true;
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info->immediate = *(u32*)codePtr;
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codePtr += 4;
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break;
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}
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break;
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case 8:
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info->zeroExtend = true;
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info->immediate = *(u32*)codePtr;
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codePtr += 4;
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break;
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}
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break;
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case 0x88: // mem <- r8
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info->isMemoryWrite = true;
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if (info->operandSize != 4)
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{
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return false;
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}
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info->operandSize = 1;
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break;
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case 0x88: // mem <- r8
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info->isMemoryWrite = true;
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if (info->operandSize != 4)
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{
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return false;
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}
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info->operandSize = 1;
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break;
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case 0x89: // mem <- r16/32/64
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info->isMemoryWrite = true;
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break;
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case 0x89: // mem <- r16/32/64
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info->isMemoryWrite = true;
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break;
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case 0x8A: // r8 <- mem
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if (info->operandSize != 4)
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{
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return false;
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}
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info->operandSize = 1;
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break;
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case 0x8A: // r8 <- mem
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if (info->operandSize != 4)
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{
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return false;
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}
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info->operandSize = 1;
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break;
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case 0x8B: // r16/32/64 <- mem
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break;
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case 0x8B: // r16/32/64 <- mem
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break;
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case 0x0FB6: // movzx on byte
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info->zeroExtend = true;
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info->operandSize = 1;
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break;
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case 0x0FB6: // movzx on byte
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info->zeroExtend = true;
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info->operandSize = 1;
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break;
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case 0x0FB7: // movzx on short
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info->zeroExtend = true;
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info->operandSize = 2;
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break;
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case 0x0FB7: // movzx on short
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info->zeroExtend = true;
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info->operandSize = 2;
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break;
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case 0x0FBE: // movsx on byte
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info->signExtend = true;
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info->operandSize = 1;
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break;
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case 0x0FBE: // movsx on byte
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info->signExtend = true;
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info->operandSize = 1;
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break;
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case 0x0FBF: // movsx on short
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info->signExtend = true;
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info->operandSize = 2;
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break;
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case 0x0FBF: // movsx on short
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info->signExtend = true;
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info->operandSize = 2;
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break;
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case 0x0F38F0: // movbe read
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info->byteSwap = true;
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break;
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case 0x0F38F0: // movbe read
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info->byteSwap = true;
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break;
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case 0x0F38F1: // movbe write
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info->byteSwap = true;
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info->isMemoryWrite = true;
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break;
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case 0x0F38F1: // movbe write
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info->byteSwap = true;
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info->isMemoryWrite = true;
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break;
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default:
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return false;
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}
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info->instructionSize = (int)(codePtr - startCodePtr);
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return true;
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default:
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return false;
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}
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info->instructionSize = (int)(codePtr - startCodePtr);
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return true;
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}
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bool InstructionInfo::operator==(const InstructionInfo& other) const
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{
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return operandSize == other.operandSize &&
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instructionSize == other.instructionSize &&
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regOperandReg == other.regOperandReg &&
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otherReg == other.otherReg &&
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scaledReg == other.scaledReg &&
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zeroExtend == other.zeroExtend &&
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signExtend == other.signExtend &&
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hasImmediate == other.hasImmediate &&
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isMemoryWrite == other.isMemoryWrite &&
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byteSwap == other.byteSwap &&
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immediate == other.immediate &&
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displacement == other.displacement;
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return operandSize == other.operandSize && instructionSize == other.instructionSize &&
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regOperandReg == other.regOperandReg && otherReg == other.otherReg &&
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scaledReg == other.scaledReg && zeroExtend == other.zeroExtend &&
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signExtend == other.signExtend && hasImmediate == other.hasImmediate &&
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isMemoryWrite == other.isMemoryWrite && byteSwap == other.byteSwap &&
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immediate == other.immediate && displacement == other.displacement;
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}
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