mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2025-07-21 05:09:34 -06:00
Reformat all the things. Have fun with merge conflicts.
This commit is contained in:
Pierre Bourdon
@ -6,31 +6,29 @@
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#include "Common/ChunkFile.h"
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#include "Common/CommonTypes.h"
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#include "Common/FPURoundMode.h"
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#include "Common/MathUtil.h"
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#include "Common/Logging/Log.h"
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#include "Common/MathUtil.h"
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#include "Core/ConfigManager.h"
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#include "Core/Host.h"
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#include "Core/HW/CPU.h"
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#include "Core/HW/Memmap.h"
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#include "Core/HW/SystemTimers.h"
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#include "Core/Host.h"
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#include "Core/PowerPC/CPUCoreBase.h"
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#include "Core/PowerPC/JitInterface.h"
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#include "Core/PowerPC/PowerPC.h"
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#include "Core/PowerPC/PPCTables.h"
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#include "Core/PowerPC/Interpreter/Interpreter.h"
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#include "Core/PowerPC/JitInterface.h"
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#include "Core/PowerPC/PPCTables.h"
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#include "Core/PowerPC/PowerPC.h"
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namespace PowerPC
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{
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// STATE_TO_SAVE
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PowerPCState ppcState;
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static CPUCoreBase* s_cpu_core_base = nullptr;
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static bool s_cpu_core_base_is_injected = false;
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Interpreter* const s_interpreter = Interpreter::getInstance();
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static CoreMode s_mode = MODE_INTERPRETER;
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static CPUCoreBase* s_cpu_core_base = nullptr;
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static bool s_cpu_core_base_is_injected = false;
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Interpreter* const s_interpreter = Interpreter::getInstance();
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static CoreMode s_mode = MODE_INTERPRETER;
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Watches watches;
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BreakPoints breakpoints;
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@ -39,494 +37,496 @@ PPCDebugInterface debug_interface;
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u32 CompactCR()
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{
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u32 new_cr = 0;
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for (int i = 0; i < 8; i++)
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{
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new_cr |= GetCRField(i) << (28 - i * 4);
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}
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return new_cr;
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u32 new_cr = 0;
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for (int i = 0; i < 8; i++)
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{
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new_cr |= GetCRField(i) << (28 - i * 4);
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}
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return new_cr;
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}
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void ExpandCR(u32 cr)
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{
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for (int i = 0; i < 8; i++)
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{
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SetCRField(i, (cr >> (28 - i * 4)) & 0xF);
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}
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for (int i = 0; i < 8; i++)
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{
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SetCRField(i, (cr >> (28 - i * 4)) & 0xF);
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}
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}
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void DoState(PointerWrap &p)
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void DoState(PointerWrap& p)
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{
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// some of this code has been disabled, because
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// it changes registers even in MODE_MEASURE (which is suspicious and seems like it could cause desyncs)
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// and because the values it's changing have been added to CoreTiming::DoState, so it might conflict to mess with them here.
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// some of this code has been disabled, because
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// it changes registers even in MODE_MEASURE (which is suspicious and seems like it could cause
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// desyncs)
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// and because the values it's changing have been added to CoreTiming::DoState, so it might
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// conflict to mess with them here.
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// rSPR(SPR_DEC) = SystemTimers::GetFakeDecrementer();
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// *((u64 *)&TL) = SystemTimers::GetFakeTimeBase(); //works since we are little endian and TL comes first :)
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// rSPR(SPR_DEC) = SystemTimers::GetFakeDecrementer();
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// *((u64 *)&TL) = SystemTimers::GetFakeTimeBase(); //works since we are little endian and TL
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// comes first :)
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p.DoPOD(ppcState);
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p.DoPOD(ppcState);
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// SystemTimers::DecrementerSet();
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// SystemTimers::TimeBaseSet();
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// SystemTimers::DecrementerSet();
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// SystemTimers::TimeBaseSet();
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JitInterface::DoState(p);
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JitInterface::DoState(p);
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}
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static void ResetRegisters()
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{
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memset(ppcState.ps, 0, sizeof(ppcState.ps));
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memset(ppcState.gpr, 0, sizeof(ppcState.gpr));
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memset(ppcState.spr, 0, sizeof(ppcState.spr));
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/*
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0x00080200 = lonestar 2.0
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0x00088202 = lonestar 2.2
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0x70000100 = gekko 1.0
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0x00080100 = gekko 2.0
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0x00083203 = gekko 2.3a
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0x00083213 = gekko 2.3b
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0x00083204 = gekko 2.4
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0x00083214 = gekko 2.4e (8SE) - retail HW2
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*/
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ppcState.spr[SPR_PVR] = 0x00083214;
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ppcState.spr[SPR_HID1] = 0x80000000; // We're running at 3x the bus clock
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ppcState.spr[SPR_ECID_U] = 0x0d96e200;
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ppcState.spr[SPR_ECID_M] = 0x1840c00d;
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ppcState.spr[SPR_ECID_L] = 0x82bb08e8;
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memset(ppcState.ps, 0, sizeof(ppcState.ps));
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memset(ppcState.gpr, 0, sizeof(ppcState.gpr));
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memset(ppcState.spr, 0, sizeof(ppcState.spr));
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/*
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0x00080200 = lonestar 2.0
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0x00088202 = lonestar 2.2
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0x70000100 = gekko 1.0
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0x00080100 = gekko 2.0
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0x00083203 = gekko 2.3a
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0x00083213 = gekko 2.3b
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0x00083204 = gekko 2.4
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0x00083214 = gekko 2.4e (8SE) - retail HW2
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*/
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ppcState.spr[SPR_PVR] = 0x00083214;
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ppcState.spr[SPR_HID1] = 0x80000000; // We're running at 3x the bus clock
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ppcState.spr[SPR_ECID_U] = 0x0d96e200;
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ppcState.spr[SPR_ECID_M] = 0x1840c00d;
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ppcState.spr[SPR_ECID_L] = 0x82bb08e8;
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ppcState.fpscr = 0;
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ppcState.pc = 0;
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ppcState.npc = 0;
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ppcState.Exceptions = 0;
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for (auto& v : ppcState.cr_val)
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v = 0x8000000000000001;
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ppcState.fpscr = 0;
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ppcState.pc = 0;
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ppcState.npc = 0;
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ppcState.Exceptions = 0;
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for (auto& v : ppcState.cr_val)
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v = 0x8000000000000001;
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TL = 0;
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TU = 0;
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SystemTimers::TimeBaseSet();
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TL = 0;
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TU = 0;
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SystemTimers::TimeBaseSet();
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// MSR should be 0x40, but we don't emulate BS1, so it would never be turned off :}
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ppcState.msr = 0;
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rDEC = 0xFFFFFFFF;
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SystemTimers::DecrementerSet();
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// MSR should be 0x40, but we don't emulate BS1, so it would never be turned off :}
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ppcState.msr = 0;
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rDEC = 0xFFFFFFFF;
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SystemTimers::DecrementerSet();
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}
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void Init(int cpu_core)
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{
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// NOTE: This function runs on EmuThread, not the CPU Thread.
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// Changing the rounding mode has a limited effect.
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FPURoundMode::SetPrecisionMode(FPURoundMode::PREC_53);
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// NOTE: This function runs on EmuThread, not the CPU Thread.
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// Changing the rounding mode has a limited effect.
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FPURoundMode::SetPrecisionMode(FPURoundMode::PREC_53);
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memset(ppcState.sr, 0, sizeof(ppcState.sr));
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ppcState.pagetable_base = 0;
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ppcState.pagetable_hashmask = 0;
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memset(ppcState.sr, 0, sizeof(ppcState.sr));
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ppcState.pagetable_base = 0;
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ppcState.pagetable_hashmask = 0;
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for (int tlb = 0; tlb < 2; tlb++)
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{
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for (int set = 0; set < 64; set++)
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{
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ppcState.tlb[tlb][set].recent = 0;
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for (int way = 0; way < 2; way++)
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{
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ppcState.tlb[tlb][set].paddr[way] = 0;
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ppcState.tlb[tlb][set].pte[way] = 0;
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ppcState.tlb[tlb][set].tag[way] = TLB_TAG_INVALID;
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}
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}
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}
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for (int tlb = 0; tlb < 2; tlb++)
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{
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for (int set = 0; set < 64; set++)
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{
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ppcState.tlb[tlb][set].recent = 0;
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for (int way = 0; way < 2; way++)
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{
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ppcState.tlb[tlb][set].paddr[way] = 0;
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ppcState.tlb[tlb][set].pte[way] = 0;
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ppcState.tlb[tlb][set].tag[way] = TLB_TAG_INVALID;
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}
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}
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}
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ResetRegisters();
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PPCTables::InitTables(cpu_core);
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ResetRegisters();
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PPCTables::InitTables(cpu_core);
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// We initialize the interpreter because
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// it is used on boot and code window independently.
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s_interpreter->Init();
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// We initialize the interpreter because
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// it is used on boot and code window independently.
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s_interpreter->Init();
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switch (cpu_core)
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{
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case PowerPC::CORE_INTERPRETER:
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s_cpu_core_base = s_interpreter;
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break;
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switch (cpu_core)
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{
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case PowerPC::CORE_INTERPRETER:
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s_cpu_core_base = s_interpreter;
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break;
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default:
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s_cpu_core_base = JitInterface::InitJitCore(cpu_core);
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if (!s_cpu_core_base) // Handle Situations where JIT core isn't available
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{
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WARN_LOG(POWERPC, "Jit core %d not available. Defaulting to interpreter.", cpu_core);
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s_cpu_core_base = s_interpreter;
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}
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break;
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}
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default:
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s_cpu_core_base = JitInterface::InitJitCore(cpu_core);
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if (!s_cpu_core_base) // Handle Situations where JIT core isn't available
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{
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WARN_LOG(POWERPC, "Jit core %d not available. Defaulting to interpreter.", cpu_core);
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s_cpu_core_base = s_interpreter;
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}
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break;
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}
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if (s_cpu_core_base != s_interpreter)
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{
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s_mode = MODE_JIT;
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}
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else
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{
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s_mode = MODE_INTERPRETER;
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}
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if (s_cpu_core_base != s_interpreter)
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{
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s_mode = MODE_JIT;
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}
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else
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{
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s_mode = MODE_INTERPRETER;
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}
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ppcState.iCache.Init();
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ppcState.iCache.Init();
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if (SConfig::GetInstance().bEnableDebugging)
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breakpoints.ClearAllTemporary();
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if (SConfig::GetInstance().bEnableDebugging)
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breakpoints.ClearAllTemporary();
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}
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void Shutdown()
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{
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InjectExternalCPUCore(nullptr);
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JitInterface::Shutdown();
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s_interpreter->Shutdown();
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s_cpu_core_base = nullptr;
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InjectExternalCPUCore(nullptr);
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JitInterface::Shutdown();
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s_interpreter->Shutdown();
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s_cpu_core_base = nullptr;
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}
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CoreMode GetMode()
|
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{
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return !s_cpu_core_base_is_injected ? s_mode : MODE_INTERPRETER;
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||||
return !s_cpu_core_base_is_injected ? s_mode : MODE_INTERPRETER;
|
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}
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||||
|
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static void ApplyMode()
|
||||
{
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||||
switch (s_mode)
|
||||
{
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case MODE_INTERPRETER: // Switching from JIT to interpreter
|
||||
s_cpu_core_base = s_interpreter;
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||||
break;
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||||
switch (s_mode)
|
||||
{
|
||||
case MODE_INTERPRETER: // Switching from JIT to interpreter
|
||||
s_cpu_core_base = s_interpreter;
|
||||
break;
|
||||
|
||||
case MODE_JIT: // Switching from interpreter to JIT.
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||||
// Don't really need to do much. It'll work, the cache will refill itself.
|
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s_cpu_core_base = JitInterface::GetCore();
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if (!s_cpu_core_base) // Has a chance to not get a working JIT core if one isn't active on host
|
||||
s_cpu_core_base = s_interpreter;
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||||
break;
|
||||
}
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case MODE_JIT: // Switching from interpreter to JIT.
|
||||
// Don't really need to do much. It'll work, the cache will refill itself.
|
||||
s_cpu_core_base = JitInterface::GetCore();
|
||||
if (!s_cpu_core_base) // Has a chance to not get a working JIT core if one isn't active on host
|
||||
s_cpu_core_base = s_interpreter;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void SetMode(CoreMode new_mode)
|
||||
{
|
||||
if (new_mode == s_mode)
|
||||
return; // We don't need to do anything.
|
||||
if (new_mode == s_mode)
|
||||
return; // We don't need to do anything.
|
||||
|
||||
s_mode = new_mode;
|
||||
s_mode = new_mode;
|
||||
|
||||
// If we're using an external CPU core implementation then don't do anything.
|
||||
if (s_cpu_core_base_is_injected)
|
||||
return;
|
||||
// If we're using an external CPU core implementation then don't do anything.
|
||||
if (s_cpu_core_base_is_injected)
|
||||
return;
|
||||
|
||||
ApplyMode();
|
||||
ApplyMode();
|
||||
}
|
||||
|
||||
const char* GetCPUName()
|
||||
{
|
||||
return s_cpu_core_base->GetName();
|
||||
return s_cpu_core_base->GetName();
|
||||
}
|
||||
|
||||
void InjectExternalCPUCore(CPUCoreBase* new_cpu)
|
||||
{
|
||||
// Previously injected.
|
||||
if (s_cpu_core_base_is_injected)
|
||||
s_cpu_core_base->Shutdown();
|
||||
// Previously injected.
|
||||
if (s_cpu_core_base_is_injected)
|
||||
s_cpu_core_base->Shutdown();
|
||||
|
||||
// nullptr means just remove
|
||||
if (!new_cpu)
|
||||
{
|
||||
if (s_cpu_core_base_is_injected)
|
||||
{
|
||||
s_cpu_core_base_is_injected = false;
|
||||
ApplyMode();
|
||||
}
|
||||
return;
|
||||
}
|
||||
// nullptr means just remove
|
||||
if (!new_cpu)
|
||||
{
|
||||
if (s_cpu_core_base_is_injected)
|
||||
{
|
||||
s_cpu_core_base_is_injected = false;
|
||||
ApplyMode();
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
new_cpu->Init();
|
||||
s_cpu_core_base = new_cpu;
|
||||
s_cpu_core_base_is_injected = true;
|
||||
new_cpu->Init();
|
||||
s_cpu_core_base = new_cpu;
|
||||
s_cpu_core_base_is_injected = true;
|
||||
}
|
||||
|
||||
void SingleStep()
|
||||
{
|
||||
s_cpu_core_base->SingleStep();
|
||||
s_cpu_core_base->SingleStep();
|
||||
}
|
||||
|
||||
void RunLoop()
|
||||
{
|
||||
Host_UpdateDisasmDialog();
|
||||
s_cpu_core_base->Run();
|
||||
Host_UpdateDisasmDialog();
|
||||
Host_UpdateDisasmDialog();
|
||||
s_cpu_core_base->Run();
|
||||
Host_UpdateDisasmDialog();
|
||||
}
|
||||
|
||||
void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst)
|
||||
{
|
||||
switch (MMCR0.PMC1SELECT)
|
||||
{
|
||||
case 0: // No change
|
||||
break;
|
||||
case 1: // Processor cycles
|
||||
PowerPC::ppcState.spr[SPR_PMC1] += cycles;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
switch (MMCR0.PMC1SELECT)
|
||||
{
|
||||
case 0: // No change
|
||||
break;
|
||||
case 1: // Processor cycles
|
||||
PowerPC::ppcState.spr[SPR_PMC1] += cycles;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
switch (MMCR0.PMC2SELECT)
|
||||
{
|
||||
case 0: // No change
|
||||
break;
|
||||
case 1: // Processor cycles
|
||||
PowerPC::ppcState.spr[SPR_PMC2] += cycles;
|
||||
break;
|
||||
case 11: // Number of loads and stores completed
|
||||
PowerPC::ppcState.spr[SPR_PMC2] += num_load_stores;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
switch (MMCR0.PMC2SELECT)
|
||||
{
|
||||
case 0: // No change
|
||||
break;
|
||||
case 1: // Processor cycles
|
||||
PowerPC::ppcState.spr[SPR_PMC2] += cycles;
|
||||
break;
|
||||
case 11: // Number of loads and stores completed
|
||||
PowerPC::ppcState.spr[SPR_PMC2] += num_load_stores;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
switch (MMCR1.PMC3SELECT)
|
||||
{
|
||||
case 0: // No change
|
||||
break;
|
||||
case 1: // Processor cycles
|
||||
PowerPC::ppcState.spr[SPR_PMC3] += cycles;
|
||||
break;
|
||||
case 11: // Number of FPU instructions completed
|
||||
PowerPC::ppcState.spr[SPR_PMC3] += num_fp_inst;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
switch (MMCR1.PMC3SELECT)
|
||||
{
|
||||
case 0: // No change
|
||||
break;
|
||||
case 1: // Processor cycles
|
||||
PowerPC::ppcState.spr[SPR_PMC3] += cycles;
|
||||
break;
|
||||
case 11: // Number of FPU instructions completed
|
||||
PowerPC::ppcState.spr[SPR_PMC3] += num_fp_inst;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
switch (MMCR1.PMC4SELECT)
|
||||
{
|
||||
case 0: // No change
|
||||
break;
|
||||
case 1: // Processor cycles
|
||||
PowerPC::ppcState.spr[SPR_PMC4] += cycles;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
switch (MMCR1.PMC4SELECT)
|
||||
{
|
||||
case 0: // No change
|
||||
break;
|
||||
case 1: // Processor cycles
|
||||
PowerPC::ppcState.spr[SPR_PMC4] += cycles;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if ((MMCR0.PMC1INTCONTROL && (PowerPC::ppcState.spr[SPR_PMC1] & 0x80000000) != 0) ||
|
||||
(MMCR0.PMCINTCONTROL && (PowerPC::ppcState.spr[SPR_PMC2] & 0x80000000) != 0) ||
|
||||
(MMCR0.PMCINTCONTROL && (PowerPC::ppcState.spr[SPR_PMC3] & 0x80000000) != 0) ||
|
||||
(MMCR0.PMCINTCONTROL && (PowerPC::ppcState.spr[SPR_PMC4] & 0x80000000) != 0))
|
||||
PowerPC::ppcState.Exceptions |= EXCEPTION_PERFORMANCE_MONITOR;
|
||||
if ((MMCR0.PMC1INTCONTROL && (PowerPC::ppcState.spr[SPR_PMC1] & 0x80000000) != 0) ||
|
||||
(MMCR0.PMCINTCONTROL && (PowerPC::ppcState.spr[SPR_PMC2] & 0x80000000) != 0) ||
|
||||
(MMCR0.PMCINTCONTROL && (PowerPC::ppcState.spr[SPR_PMC3] & 0x80000000) != 0) ||
|
||||
(MMCR0.PMCINTCONTROL && (PowerPC::ppcState.spr[SPR_PMC4] & 0x80000000) != 0))
|
||||
PowerPC::ppcState.Exceptions |= EXCEPTION_PERFORMANCE_MONITOR;
|
||||
}
|
||||
|
||||
void CheckExceptions()
|
||||
{
|
||||
u32 exceptions = ppcState.Exceptions;
|
||||
u32 exceptions = ppcState.Exceptions;
|
||||
|
||||
// Example procedure:
|
||||
// set SRR0 to either PC or NPC
|
||||
//SRR0 = NPC;
|
||||
// save specified MSR bits
|
||||
//SRR1 = MSR & 0x87C0FFFF;
|
||||
// copy ILE bit to LE
|
||||
//MSR |= (MSR >> 16) & 1;
|
||||
// clear MSR as specified
|
||||
//MSR &= ~0x04EF36; // 0x04FF36 also clears ME (only for machine check exception)
|
||||
// set to exception type entry point
|
||||
//NPC = 0x00000x00;
|
||||
// Example procedure:
|
||||
// set SRR0 to either PC or NPC
|
||||
// SRR0 = NPC;
|
||||
// save specified MSR bits
|
||||
// SRR1 = MSR & 0x87C0FFFF;
|
||||
// copy ILE bit to LE
|
||||
// MSR |= (MSR >> 16) & 1;
|
||||
// clear MSR as specified
|
||||
// MSR &= ~0x04EF36; // 0x04FF36 also clears ME (only for machine check exception)
|
||||
// set to exception type entry point
|
||||
// NPC = 0x00000x00;
|
||||
|
||||
// TODO(delroth): Exception priority is completely wrong here: depending on
|
||||
// the instruction class, exceptions should be executed in a given order,
|
||||
// which is very different from the one arbitrarily chosen here. See §6.1.5
|
||||
// in 6xx_pem.pdf.
|
||||
// TODO(delroth): Exception priority is completely wrong here: depending on
|
||||
// the instruction class, exceptions should be executed in a given order,
|
||||
// which is very different from the one arbitrarily chosen here. See §6.1.5
|
||||
// in 6xx_pem.pdf.
|
||||
|
||||
if (exceptions & EXCEPTION_ISI)
|
||||
{
|
||||
SRR0 = NPC;
|
||||
// Page fault occurred
|
||||
SRR1 = (MSR & 0x87C0FFFF) | (1 << 30);
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000400;
|
||||
if (exceptions & EXCEPTION_ISI)
|
||||
{
|
||||
SRR0 = NPC;
|
||||
// Page fault occurred
|
||||
SRR1 = (MSR & 0x87C0FFFF) | (1 << 30);
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000400;
|
||||
|
||||
INFO_LOG(POWERPC, "EXCEPTION_ISI");
|
||||
ppcState.Exceptions &= ~EXCEPTION_ISI;
|
||||
}
|
||||
else if (exceptions & EXCEPTION_PROGRAM)
|
||||
{
|
||||
SRR0 = PC;
|
||||
// say that it's a trap exception
|
||||
SRR1 = (MSR & 0x87C0FFFF) | 0x20000;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000700;
|
||||
INFO_LOG(POWERPC, "EXCEPTION_ISI");
|
||||
ppcState.Exceptions &= ~EXCEPTION_ISI;
|
||||
}
|
||||
else if (exceptions & EXCEPTION_PROGRAM)
|
||||
{
|
||||
SRR0 = PC;
|
||||
// say that it's a trap exception
|
||||
SRR1 = (MSR & 0x87C0FFFF) | 0x20000;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000700;
|
||||
|
||||
INFO_LOG(POWERPC, "EXCEPTION_PROGRAM");
|
||||
ppcState.Exceptions &= ~EXCEPTION_PROGRAM;
|
||||
}
|
||||
else if (exceptions & EXCEPTION_SYSCALL)
|
||||
{
|
||||
SRR0 = NPC;
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000C00;
|
||||
INFO_LOG(POWERPC, "EXCEPTION_PROGRAM");
|
||||
ppcState.Exceptions &= ~EXCEPTION_PROGRAM;
|
||||
}
|
||||
else if (exceptions & EXCEPTION_SYSCALL)
|
||||
{
|
||||
SRR0 = NPC;
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000C00;
|
||||
|
||||
INFO_LOG(POWERPC, "EXCEPTION_SYSCALL (PC=%08x)", PC);
|
||||
ppcState.Exceptions &= ~EXCEPTION_SYSCALL;
|
||||
}
|
||||
else if (exceptions & EXCEPTION_FPU_UNAVAILABLE)
|
||||
{
|
||||
//This happens a lot - GameCube OS uses deferred FPU context switching
|
||||
SRR0 = PC; // re-execute the instruction
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000800;
|
||||
INFO_LOG(POWERPC, "EXCEPTION_SYSCALL (PC=%08x)", PC);
|
||||
ppcState.Exceptions &= ~EXCEPTION_SYSCALL;
|
||||
}
|
||||
else if (exceptions & EXCEPTION_FPU_UNAVAILABLE)
|
||||
{
|
||||
// This happens a lot - GameCube OS uses deferred FPU context switching
|
||||
SRR0 = PC; // re-execute the instruction
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000800;
|
||||
|
||||
INFO_LOG(POWERPC, "EXCEPTION_FPU_UNAVAILABLE");
|
||||
ppcState.Exceptions &= ~EXCEPTION_FPU_UNAVAILABLE;
|
||||
}
|
||||
INFO_LOG(POWERPC, "EXCEPTION_FPU_UNAVAILABLE");
|
||||
ppcState.Exceptions &= ~EXCEPTION_FPU_UNAVAILABLE;
|
||||
}
|
||||
#ifdef ENABLE_MEM_CHECK
|
||||
else if (exceptions & EXCEPTION_FAKE_MEMCHECK_HIT)
|
||||
{
|
||||
ppcState.Exceptions &= ~EXCEPTION_DSI & ~EXCEPTION_FAKE_MEMCHECK_HIT;
|
||||
}
|
||||
else if (exceptions & EXCEPTION_FAKE_MEMCHECK_HIT)
|
||||
{
|
||||
ppcState.Exceptions &= ~EXCEPTION_DSI & ~EXCEPTION_FAKE_MEMCHECK_HIT;
|
||||
}
|
||||
#endif
|
||||
else if (exceptions & EXCEPTION_DSI)
|
||||
{
|
||||
SRR0 = PC;
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000300;
|
||||
//DSISR and DAR regs are changed in GenerateDSIException()
|
||||
else if (exceptions & EXCEPTION_DSI)
|
||||
{
|
||||
SRR0 = PC;
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000300;
|
||||
// DSISR and DAR regs are changed in GenerateDSIException()
|
||||
|
||||
INFO_LOG(POWERPC, "EXCEPTION_DSI");
|
||||
ppcState.Exceptions &= ~EXCEPTION_DSI;
|
||||
}
|
||||
else if (exceptions & EXCEPTION_ALIGNMENT)
|
||||
{
|
||||
//This never happens ATM
|
||||
// perhaps we can get dcb* instructions to use this :p
|
||||
SRR0 = PC;
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000600;
|
||||
INFO_LOG(POWERPC, "EXCEPTION_DSI");
|
||||
ppcState.Exceptions &= ~EXCEPTION_DSI;
|
||||
}
|
||||
else if (exceptions & EXCEPTION_ALIGNMENT)
|
||||
{
|
||||
// This never happens ATM
|
||||
// perhaps we can get dcb* instructions to use this :p
|
||||
SRR0 = PC;
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000600;
|
||||
|
||||
//TODO crazy amount of DSISR options to check out
|
||||
// TODO crazy amount of DSISR options to check out
|
||||
|
||||
INFO_LOG(POWERPC, "EXCEPTION_ALIGNMENT");
|
||||
ppcState.Exceptions &= ~EXCEPTION_ALIGNMENT;
|
||||
}
|
||||
INFO_LOG(POWERPC, "EXCEPTION_ALIGNMENT");
|
||||
ppcState.Exceptions &= ~EXCEPTION_ALIGNMENT;
|
||||
}
|
||||
|
||||
// EXTERNAL INTERRUPT
|
||||
else if (MSR & 0x0008000) // Handling is delayed until MSR.EE=1.
|
||||
{
|
||||
if (exceptions & EXCEPTION_EXTERNAL_INT)
|
||||
{
|
||||
// Pokemon gets this "too early", it hasn't a handler yet
|
||||
SRR0 = NPC;
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000500;
|
||||
// EXTERNAL INTERRUPT
|
||||
else if (MSR & 0x0008000) // Handling is delayed until MSR.EE=1.
|
||||
{
|
||||
if (exceptions & EXCEPTION_EXTERNAL_INT)
|
||||
{
|
||||
// Pokemon gets this "too early", it hasn't a handler yet
|
||||
SRR0 = NPC;
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000500;
|
||||
|
||||
INFO_LOG(POWERPC, "EXCEPTION_EXTERNAL_INT");
|
||||
ppcState.Exceptions &= ~EXCEPTION_EXTERNAL_INT;
|
||||
INFO_LOG(POWERPC, "EXCEPTION_EXTERNAL_INT");
|
||||
ppcState.Exceptions &= ~EXCEPTION_EXTERNAL_INT;
|
||||
|
||||
_dbg_assert_msg_(POWERPC, (SRR1 & 0x02) != 0, "EXTERNAL_INT unrecoverable???");
|
||||
}
|
||||
else if (exceptions & EXCEPTION_PERFORMANCE_MONITOR)
|
||||
{
|
||||
SRR0 = NPC;
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000F00;
|
||||
_dbg_assert_msg_(POWERPC, (SRR1 & 0x02) != 0, "EXTERNAL_INT unrecoverable???");
|
||||
}
|
||||
else if (exceptions & EXCEPTION_PERFORMANCE_MONITOR)
|
||||
{
|
||||
SRR0 = NPC;
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000F00;
|
||||
|
||||
INFO_LOG(POWERPC, "EXCEPTION_PERFORMANCE_MONITOR");
|
||||
ppcState.Exceptions &= ~EXCEPTION_PERFORMANCE_MONITOR;
|
||||
}
|
||||
else if (exceptions & EXCEPTION_DECREMENTER)
|
||||
{
|
||||
SRR0 = NPC;
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000900;
|
||||
INFO_LOG(POWERPC, "EXCEPTION_PERFORMANCE_MONITOR");
|
||||
ppcState.Exceptions &= ~EXCEPTION_PERFORMANCE_MONITOR;
|
||||
}
|
||||
else if (exceptions & EXCEPTION_DECREMENTER)
|
||||
{
|
||||
SRR0 = NPC;
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000900;
|
||||
|
||||
INFO_LOG(POWERPC, "EXCEPTION_DECREMENTER");
|
||||
ppcState.Exceptions &= ~EXCEPTION_DECREMENTER;
|
||||
}
|
||||
}
|
||||
INFO_LOG(POWERPC, "EXCEPTION_DECREMENTER");
|
||||
ppcState.Exceptions &= ~EXCEPTION_DECREMENTER;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void CheckExternalExceptions()
|
||||
{
|
||||
u32 exceptions = ppcState.Exceptions;
|
||||
u32 exceptions = ppcState.Exceptions;
|
||||
|
||||
// EXTERNAL INTERRUPT
|
||||
if (exceptions && (MSR & 0x0008000)) // Handling is delayed until MSR.EE=1.
|
||||
{
|
||||
if (exceptions & EXCEPTION_EXTERNAL_INT)
|
||||
{
|
||||
// Pokemon gets this "too early", it hasn't a handler yet
|
||||
SRR0 = NPC;
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000500;
|
||||
// EXTERNAL INTERRUPT
|
||||
if (exceptions && (MSR & 0x0008000)) // Handling is delayed until MSR.EE=1.
|
||||
{
|
||||
if (exceptions & EXCEPTION_EXTERNAL_INT)
|
||||
{
|
||||
// Pokemon gets this "too early", it hasn't a handler yet
|
||||
SRR0 = NPC;
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000500;
|
||||
|
||||
INFO_LOG(POWERPC, "EXCEPTION_EXTERNAL_INT");
|
||||
ppcState.Exceptions &= ~EXCEPTION_EXTERNAL_INT;
|
||||
INFO_LOG(POWERPC, "EXCEPTION_EXTERNAL_INT");
|
||||
ppcState.Exceptions &= ~EXCEPTION_EXTERNAL_INT;
|
||||
|
||||
_dbg_assert_msg_(POWERPC, (SRR1 & 0x02) != 0, "EXTERNAL_INT unrecoverable???");
|
||||
}
|
||||
else if (exceptions & EXCEPTION_PERFORMANCE_MONITOR)
|
||||
{
|
||||
SRR0 = NPC;
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000F00;
|
||||
_dbg_assert_msg_(POWERPC, (SRR1 & 0x02) != 0, "EXTERNAL_INT unrecoverable???");
|
||||
}
|
||||
else if (exceptions & EXCEPTION_PERFORMANCE_MONITOR)
|
||||
{
|
||||
SRR0 = NPC;
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000F00;
|
||||
|
||||
INFO_LOG(POWERPC, "EXCEPTION_PERFORMANCE_MONITOR");
|
||||
ppcState.Exceptions &= ~EXCEPTION_PERFORMANCE_MONITOR;
|
||||
}
|
||||
else if (exceptions & EXCEPTION_DECREMENTER)
|
||||
{
|
||||
SRR0 = NPC;
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000900;
|
||||
INFO_LOG(POWERPC, "EXCEPTION_PERFORMANCE_MONITOR");
|
||||
ppcState.Exceptions &= ~EXCEPTION_PERFORMANCE_MONITOR;
|
||||
}
|
||||
else if (exceptions & EXCEPTION_DECREMENTER)
|
||||
{
|
||||
SRR0 = NPC;
|
||||
SRR1 = MSR & 0x87C0FFFF;
|
||||
MSR |= (MSR >> 16) & 1;
|
||||
MSR &= ~0x04EF36;
|
||||
PC = NPC = 0x00000900;
|
||||
|
||||
INFO_LOG(POWERPC, "EXCEPTION_DECREMENTER");
|
||||
ppcState.Exceptions &= ~EXCEPTION_DECREMENTER;
|
||||
}
|
||||
else
|
||||
{
|
||||
_dbg_assert_msg_(POWERPC, 0, "Unknown EXT interrupt: Exceptions == %08x", exceptions);
|
||||
ERROR_LOG(POWERPC, "Unknown EXTERNAL INTERRUPT exception: Exceptions == %08x", exceptions);
|
||||
}
|
||||
}
|
||||
INFO_LOG(POWERPC, "EXCEPTION_DECREMENTER");
|
||||
ppcState.Exceptions &= ~EXCEPTION_DECREMENTER;
|
||||
}
|
||||
else
|
||||
{
|
||||
_dbg_assert_msg_(POWERPC, 0, "Unknown EXT interrupt: Exceptions == %08x", exceptions);
|
||||
ERROR_LOG(POWERPC, "Unknown EXTERNAL INTERRUPT exception: Exceptions == %08x", exceptions);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void CheckBreakPoints()
|
||||
{
|
||||
if (PowerPC::breakpoints.IsAddressBreakPoint(PC))
|
||||
{
|
||||
CPU::Break();
|
||||
if (PowerPC::breakpoints.IsTempBreakPoint(PC))
|
||||
PowerPC::breakpoints.Remove(PC);
|
||||
}
|
||||
if (PowerPC::breakpoints.IsAddressBreakPoint(PC))
|
||||
{
|
||||
CPU::Break();
|
||||
if (PowerPC::breakpoints.IsTempBreakPoint(PC))
|
||||
PowerPC::breakpoints.Remove(PC);
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace
|
||||
|
||||
|
||||
// FPSCR update functions
|
||||
|
||||
void UpdateFPRF(double dvalue)
|
||||
{
|
||||
FPSCR.FPRF = MathUtil::ClassifyDouble(dvalue);
|
||||
//if (FPSCR.FPRF == 0x11)
|
||||
// PanicAlert("QNAN alert");
|
||||
FPSCR.FPRF = MathUtil::ClassifyDouble(dvalue);
|
||||
// if (FPSCR.FPRF == 0x11)
|
||||
// PanicAlert("QNAN alert");
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user