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DSP LLE: code cleanup that doesn't affect behavior.
Make DSPCore build properly in debugfast (breakpoints work again) git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@4816 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
Shawn Hoffman
@ -30,149 +30,149 @@
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#include "DSPBreakpoints.h"
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#define DSP_IRAM_BYTE_SIZE 0x2000
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#define DSP_IRAM_SIZE 0x1000
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#define DSP_IRAM_MASK 0x0fff
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#define DSP_IRAM_BYTE_SIZE 0x2000
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#define DSP_IRAM_SIZE 0x1000
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#define DSP_IRAM_MASK 0x0fff
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#define DSP_IROM_BYTE_SIZE 0x2000
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#define DSP_IROM_SIZE 0x1000
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#define DSP_IROM_MASK 0x0fff
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#define DSP_IROM_BYTE_SIZE 0x2000
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#define DSP_IROM_SIZE 0x1000
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#define DSP_IROM_MASK 0x0fff
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#define DSP_DRAM_BYTE_SIZE 0x2000
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#define DSP_DRAM_SIZE 0x1000
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#define DSP_DRAM_MASK 0x0fff
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#define DSP_DRAM_BYTE_SIZE 0x2000
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#define DSP_DRAM_SIZE 0x1000
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#define DSP_DRAM_MASK 0x0fff
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#define DSP_COEF_BYTE_SIZE 0x1000
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#define DSP_COEF_SIZE 0x800
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#define DSP_COEF_MASK 0x7ff
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#define DSP_COEF_BYTE_SIZE 0x1000
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#define DSP_COEF_SIZE 0x800
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#define DSP_COEF_MASK 0x7ff
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#define DSP_RESET_VECTOR 0x8000
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#define DSP_RESET_VECTOR 0x8000
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#define DSP_STACK_DEPTH 0x20
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#define DSP_STACK_MASK 0x1f
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#define DSP_STACK_DEPTH 0x20
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#define DSP_STACK_MASK 0x1f
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#define DSP_CR_IMEM 2
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#define DSP_CR_DMEM 0
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#define DSP_CR_TO_CPU 1
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#define DSP_CR_FROM_CPU 0
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#define DSP_CR_IMEM 2
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#define DSP_CR_DMEM 0
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#define DSP_CR_TO_CPU 1
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#define DSP_CR_FROM_CPU 0
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// Register table taken from libasnd
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#define DSP_REG_AR0 0x00 // address registers
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#define DSP_REG_AR1 0x01
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#define DSP_REG_AR2 0x02
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#define DSP_REG_AR3 0x03
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#define DSP_REG_AR0 0x00 // address registers
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#define DSP_REG_AR1 0x01
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#define DSP_REG_AR2 0x02
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#define DSP_REG_AR3 0x03
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#define DSP_REG_IX0 0x04 // indexing registers (actually, mostly used as increments)
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#define DSP_REG_IX1 0x05
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#define DSP_REG_IX2 0x06
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#define DSP_REG_IX3 0x07
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#define DSP_REG_IX0 0x04 // indexing registers (actually, mostly used as increments)
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#define DSP_REG_IX1 0x05
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#define DSP_REG_IX2 0x06
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#define DSP_REG_IX3 0x07
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#define DSP_REG_WR0 0x08 // address wrapping registers. should be initialized to 0xFFFF if not used.
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#define DSP_REG_WR1 0x09
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#define DSP_REG_WR2 0x0a
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#define DSP_REG_WR3 0x0b
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#define DSP_REG_WR0 0x08 // address wrapping registers. should be initialized to 0xFFFF if not used.
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#define DSP_REG_WR1 0x09
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#define DSP_REG_WR2 0x0a
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#define DSP_REG_WR3 0x0b
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#define DSP_REG_ST0 0x0c // stacks.
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#define DSP_REG_ST1 0x0d
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#define DSP_REG_ST2 0x0e
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#define DSP_REG_ST3 0x0f
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#define DSP_REG_ST0 0x0c // stacks.
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#define DSP_REG_ST1 0x0d
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#define DSP_REG_ST2 0x0e
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#define DSP_REG_ST3 0x0f
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#define DSP_REG_CR 0x12 // Seems to be the top 8 bits of LRS/SRS.
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#define DSP_REG_SR 0x13
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#define DSP_REG_CR 0x12 // Seems to be the top 8 bits of LRS/SRS.
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#define DSP_REG_SR 0x13
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#define DSP_REG_PRODL 0x14 // product.
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#define DSP_REG_PRODM 0x15
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#define DSP_REG_PRODH 0x16
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#define DSP_REG_PRODM2 0x17
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#define DSP_REG_PRODL 0x14 // product.
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#define DSP_REG_PRODM 0x15
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#define DSP_REG_PRODH 0x16
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#define DSP_REG_PRODM2 0x17
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#define DSP_REG_AXL0 0x18
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#define DSP_REG_AXL1 0x19
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#define DSP_REG_AXH0 0x1a
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#define DSP_REG_AXH1 0x1b
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#define DSP_REG_AXL0 0x18
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#define DSP_REG_AXL1 0x19
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#define DSP_REG_AXH0 0x1a
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#define DSP_REG_AXH1 0x1b
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#define DSP_REG_ACC0 0x1c // accumulator (global)
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#define DSP_REG_ACC1 0x1d
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#define DSP_REG_ACC0 0x1c // accumulator (global)
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#define DSP_REG_ACC1 0x1d
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#define DSP_REG_ACL0 0x1c // Low accumulator
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#define DSP_REG_ACL1 0x1d
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#define DSP_REG_ACM0 0x1e // Mid accumulator
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#define DSP_REG_ACM1 0x1f
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#define DSP_REG_ACH0 0x10 // Sign extended 8 bit register 0
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#define DSP_REG_ACH1 0x11 // Sign extended 8 bit register 1
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#define DSP_REG_ACL0 0x1c // Low accumulator
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#define DSP_REG_ACL1 0x1d
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#define DSP_REG_ACM0 0x1e // Mid accumulator
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#define DSP_REG_ACM1 0x1f
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#define DSP_REG_ACH0 0x10 // Sign extended 8 bit register 0
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#define DSP_REG_ACH1 0x11 // Sign extended 8 bit register 1
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// Hardware registers address
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#define DSP_COEF_A1_0 0xa0
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#define DSP_COEF_A1_0 0xa0
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#define DSP_DSMAH 0xce
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#define DSP_DSMAL 0xcf
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#define DSP_DSCR 0xc9 // DSP DMA Control Reg
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#define DSP_DSPA 0xcd // DSP DMA Block Length
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#define DSP_DSBL 0xcb // DSP DMA DMEM Address
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#define DSP_DSMAH 0xce // DSP DMA Mem Address H
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#define DSP_DSMAL 0xcf // DSP DMA Mem Address L
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#define DSP_DSCR 0xc9 // DSP DMA Control Reg
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#define DSP_DSPA 0xcd // DSP DMA Address (DSP)
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#define DSP_DSBL 0xcb // DSP DMA Block Length
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#define DSP_DSMAH 0xce // DSP DMA Address High (External)
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#define DSP_DSMAL 0xcf // DSP DMA Address Low (External)
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#define DSP_FORMAT 0xd1
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#define DSP_ACDATA1 0xd3 // used only by Zelda ucodes
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#define DSP_ACSAH 0xd4
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#define DSP_ACSAL 0xd5
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#define DSP_ACEAH 0xd6
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#define DSP_ACEAL 0xd7
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#define DSP_ACCAH 0xd8
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#define DSP_ACCAL 0xd9
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#define DSP_PRED_SCALE 0xda
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#define DSP_YN1 0xdb
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#define DSP_YN2 0xdc
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#define DSP_ACCELERATOR 0xdd // ADPCM accelerator read. Used by AX.
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#define DSP_GAIN 0xde
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#define DSP_FORMAT 0xd1 // Sample format
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#define DSP_ACDATA1 0xd3 // used only by Zelda ucodes
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#define DSP_ACSAH 0xd4 // Start of loop
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#define DSP_ACSAL 0xd5
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#define DSP_ACEAH 0xd6 // End of sample (and loop)
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#define DSP_ACEAL 0xd7
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#define DSP_ACCAH 0xd8 // Current playback position
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#define DSP_ACCAL 0xd9
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#define DSP_PRED_SCALE 0xda // ADPCM predictor and scale
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#define DSP_YN1 0xdb
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#define DSP_YN2 0xdc
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#define DSP_ACCELERATOR 0xdd // ADPCM accelerator read. Used by AX.
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#define DSP_GAIN 0xde
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#define DSP_DIRQ 0xfb // DSP Irq Rest
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#define DSP_DMBH 0xfc // DSP Mailbox H
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#define DSP_DMBL 0xfd // DSP Mailbox L
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#define DSP_CMBH 0xfe // CPU Mailbox H
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#define DSP_CMBL 0xff // CPU Mailbox L
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#define DSP_DREQ_MASK 0xef // ARAM DMA Request Mask
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#define DMA_TO_DSP 0
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#define DMA_TO_CPU 1
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#define DSP_DIRQ 0xfb // DSP Irq Rest
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#define DSP_DMBH 0xfc // DSP Mailbox H
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#define DSP_DMBL 0xfd // DSP Mailbox L
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#define DSP_CMBH 0xfe // CPU Mailbox H
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#define DSP_CMBL 0xff // CPU Mailbox L
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#define DMA_TO_DSP 0
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#define DMA_TO_CPU 1
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// Stacks
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#define DSP_STACK_C 0
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#define DSP_STACK_D 1
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#define DSP_STACK_C 0
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#define DSP_STACK_D 1
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// cr (Not g_dsp.r[CR]) bits
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// See HW/DSP.cpp.
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#define CR_HALT 0x0004
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#define CR_EXTERNAL_INT 0x0002
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#define CR_HALT 0x0004
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#define CR_INIT 0x0400
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#define CR_EXTERNAL_INT 0x0002
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// SR bits
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#define SR_CARRY 0x0001
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#define SR_OVERFLOW 0x0002
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#define SR_ARITH_ZERO 0x0004
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#define SR_SIGN 0x0008
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#define SR_10 0x0010 // seem to be set by tst
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#define SR_TOP2BITS 0x0020 // if the upper 2 bits are equal
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#define SR_LOGIC_ZERO 0x0040
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#define SR_80 0x0080 // Unknown, set by add
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#define SR_INT_ENABLE 0x0200 // Not 100% sure but duddie says so. This should replace the hack, if so.
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#define SR_EXT_INT_ENABLE 0x0800 // Appears in zelda - seems to disable external interupts
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#define SR_MUL_MODIFY 0x2000 // 1 = normal. 0 = x2 (M0, M2)
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#define SR_40_MODE_BIT 0x4000 // 0 = "16", 1 = "40" (SET16, SET40) Controls sign extension when loading mid accums.
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#define SR_MUL_UNSIGNED 0x8000 // 0 = normal. 1 = unsigned (CLR15, SET15) If set, treats operands as unsigned. Tested with mulx only so far.
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#define SR_CARRY 0x0001
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#define SR_OVERFLOW 0x0002
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#define SR_ARITH_ZERO 0x0004
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#define SR_SIGN 0x0008
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#define SR_10 0x0010 // seem to be set by tst
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#define SR_TOP2BITS 0x0020 // if the upper 2 bits are equal
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#define SR_LOGIC_ZERO 0x0040
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#define SR_80 0x0080 // Unknown, set by add
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#define SR_INT_ENABLE 0x0200 // Not 100% sure but duddie says so. This should replace the hack, if so.
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#define SR_EXT_INT_ENABLE 0x0800 // Appears in zelda - seems to disable external interupts
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#define SR_MUL_MODIFY 0x2000 // 1 = normal. 0 = x2 (M0, M2)
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#define SR_40_MODE_BIT 0x4000 // 0 = "16", 1 = "40" (SET16, SET40) Controls sign extension when loading mid accums.
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#define SR_MUL_UNSIGNED 0x8000 // 0 = normal. 1 = unsigned (CLR15, SET15) If set, treats operands as unsigned. Tested with mulx only so far.
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// This should be the bits affected by CMP. Does not include logic zero.
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#define SR_CMP_MASK 0x3f
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#define SR_CMP_MASK 0x3f
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// exceptions vector
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#define EXP_STOVF 1 // 0x0002 stack under/over flow
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#define EXP_2 2 // 0x0004
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#define EXP_3 3 // 0x0006
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#define EXP_4 4 // 0x0008
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#define EXP_ACCOV 5 // 0x000a accelerator address overflow
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#define EXP_6 6 // 0x000c
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#define EXP_INT 7 // 0x000e external int (message from cpu)
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#define EXP_STOVF 1 // 0x0002 stack under/over flow
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#define EXP_2 2 // 0x0004
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#define EXP_3 3 // 0x0006
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#define EXP_4 4 // 0x0008
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#define EXP_ACCOV 5 // 0x000a accelerator address overflow
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#define EXP_6 6 // 0x000c
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#define EXP_INT 7 // 0x000e external int (message from cpu)
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// All the state of the DSP should be in this struct. Any DSP state that is not filled on init
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// should be moved here.
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@ -232,7 +232,7 @@ extern DSPBreakpoints dsp_breakpoints;
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bool DSPCore_Init(const char *irom_filename, const char *coef_filename);
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void DSPCore_Reset();
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void DSPCore_Shutdown(); // Frees all allocated memory.
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void DSPCore_Shutdown(); // Frees all allocated memory.
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void DSPCore_CheckExternalInterrupt();
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void DSPCore_CheckExceptions();
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@ -254,4 +254,4 @@ DSPCoreState DSPCore_GetState();
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void DSPCore_Step();
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#endif // _DSPCORE_H
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#endif // _DSPCORE_H
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@ -144,14 +144,14 @@ void ln(const UDSPInstruction& opc)
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void ls(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
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u8 sreg = 0x03;
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u8 sreg = DSP_REG_AR3;
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u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0;
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dsp_dmem_write(g_dsp.r[sreg], g_dsp.r[areg]);
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[0x00]));
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR0]));
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writeToBackLog(1, sreg, dsp_increment_addr_reg(sreg));
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writeToBackLog(2, 0x00, dsp_increment_addr_reg(0x00));
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writeToBackLog(2, DSP_REG_AR0, dsp_increment_addr_reg(DSP_REG_AR0));
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}
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@ -164,14 +164,14 @@ void ls(const UDSPInstruction& opc)
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void lsn(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
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u8 sreg = 0x03;
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u8 sreg = DSP_REG_AR3;
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u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0;
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dsp_dmem_write(g_dsp.r[sreg], g_dsp.r[areg]);
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[0x00]));
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR0]));
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writeToBackLog(1, sreg, dsp_increment_addr_reg(sreg));
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writeToBackLog(2, 0x00,dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0]));
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writeToBackLog(2, DSP_REG_AR0, dsp_increase_addr_reg(DSP_REG_AR0, (s16)g_dsp.r[DSP_REG_IX0]));
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}
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// LSM $acD.l, $acS.m
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@ -183,14 +183,14 @@ void lsn(const UDSPInstruction& opc)
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void lsm(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
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u8 sreg = 0x03;
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u8 sreg = DSP_REG_AR3;
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u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0;
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dsp_dmem_write(g_dsp.r[sreg], g_dsp.r[areg]);
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[0x00]));
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR0]));
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writeToBackLog(1, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]));
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writeToBackLog(2, 0x00, dsp_increment_addr_reg(0x00));
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writeToBackLog(2, DSP_REG_AR0, dsp_increment_addr_reg(DSP_REG_AR0));
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}
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// LSMN $acD.l, $acS.m
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@ -203,14 +203,14 @@ void lsm(const UDSPInstruction& opc)
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void lsnm(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
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u8 sreg = 0x03;
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u8 sreg = DSP_REG_AR3;
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u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0;
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dsp_dmem_write(g_dsp.r[sreg], g_dsp.r[areg]);
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[0x00]));
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR0]));
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writeToBackLog(1, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]));
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writeToBackLog(2, 0x00, dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0]));
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writeToBackLog(2, DSP_REG_AR0, dsp_increase_addr_reg(DSP_REG_AR0, (s16)g_dsp.r[DSP_REG_IX0]));
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}
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// SL $acS.m, $acD.l
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@ -222,13 +222,13 @@ void sl(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
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u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0;
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const u8 sreg = 0x03;
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const u8 sreg = DSP_REG_AR3;
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dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]);
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dsp_dmem_write(g_dsp.r[DSP_REG_AR0], g_dsp.r[areg]);
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[sreg]));
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writeToBackLog(1, sreg, dsp_increment_addr_reg(sreg));
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writeToBackLog(2, 0x00, dsp_increment_addr_reg(0x00));
|
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writeToBackLog(2, DSP_REG_AR0, dsp_increment_addr_reg(DSP_REG_AR0));
|
||||
}
|
||||
|
||||
// SLN $acS.m, $acD.l
|
||||
@ -241,13 +241,13 @@ void sln(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
|
||||
u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0;
|
||||
const u8 sreg = 0x03;
|
||||
const u8 sreg = DSP_REG_AR3;
|
||||
|
||||
dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]);
|
||||
dsp_dmem_write(g_dsp.r[DSP_REG_AR0], g_dsp.r[areg]);
|
||||
|
||||
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[sreg]));
|
||||
writeToBackLog(1, sreg, dsp_increment_addr_reg(sreg));
|
||||
writeToBackLog(2, 0x00, dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0]));
|
||||
writeToBackLog(2, DSP_REG_AR0, dsp_increase_addr_reg(DSP_REG_AR0, (s16)g_dsp.r[DSP_REG_IX0]));
|
||||
}
|
||||
|
||||
// SLM $acS.m, $acD.l
|
||||
@ -260,13 +260,13 @@ void slm(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
|
||||
u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0;
|
||||
const u8 sreg = 0x03;
|
||||
const u8 sreg = DSP_REG_AR3;
|
||||
|
||||
dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]);
|
||||
dsp_dmem_write(g_dsp.r[DSP_REG_AR0], g_dsp.r[areg]);
|
||||
|
||||
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[sreg]));
|
||||
writeToBackLog(1, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]));
|
||||
writeToBackLog(2, 0x00, dsp_increment_addr_reg(0x00));
|
||||
writeToBackLog(2, DSP_REG_AR0, dsp_increment_addr_reg(DSP_REG_AR0));
|
||||
}
|
||||
|
||||
// SLMN $acS.m, $acD.l
|
||||
@ -279,13 +279,13 @@ void slnm(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
|
||||
u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0;
|
||||
const u8 sreg = 0x03;
|
||||
const u8 sreg = DSP_REG_AR3;
|
||||
|
||||
dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]);
|
||||
dsp_dmem_write(g_dsp.r[DSP_REG_AR0], g_dsp.r[areg]);
|
||||
|
||||
writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[sreg]));
|
||||
writeToBackLog(1, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]));
|
||||
writeToBackLog(2, 0x00, dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0]));
|
||||
writeToBackLog(2, DSP_REG_AR0, dsp_increase_addr_reg(DSP_REG_AR0, (s16)g_dsp.r[DSP_REG_IX0]));
|
||||
}
|
||||
|
||||
// Not in duddie's doc
|
||||
@ -297,22 +297,22 @@ void ld(const UDSPInstruction& opc)
|
||||
u8 rreg = (opc.hex >> 4) & 0x1;
|
||||
u8 sreg = opc.hex & 0x3;
|
||||
|
||||
if (sreg != 0x03) {
|
||||
if (sreg != DSP_REG_AR3) {
|
||||
writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[sreg]));
|
||||
|
||||
if (IsSameMemArea(g_dsp.r[sreg],g_dsp.r[0x3]))
|
||||
if (IsSameMemArea(g_dsp.r[sreg], g_dsp.r[DSP_REG_AR3]))
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[sreg]));
|
||||
else
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[0x3]));
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
|
||||
writeToBackLog(2, sreg, dsp_increment_addr_reg(sreg));
|
||||
} else {
|
||||
writeToBackLog(0, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[dreg]));
|
||||
|
||||
if (IsSameMemArea(g_dsp.r[dreg],g_dsp.r[0x3]))
|
||||
if (IsSameMemArea(g_dsp.r[dreg], g_dsp.r[DSP_REG_AR3]))
|
||||
writeToBackLog(1, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[dreg]));
|
||||
else
|
||||
writeToBackLog(1, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[0x3]));
|
||||
writeToBackLog(1, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
|
||||
writeToBackLog(2, dreg, dsp_increment_addr_reg(dreg));
|
||||
}
|
||||
@ -329,22 +329,22 @@ void ldn(const UDSPInstruction& opc)
|
||||
u8 rreg = (opc.hex >> 4) & 0x1;
|
||||
u8 sreg = opc.hex & 0x3;
|
||||
|
||||
if (sreg != 0x03) {
|
||||
if (sreg != DSP_REG_AR3) {
|
||||
writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[sreg]));
|
||||
|
||||
if (IsSameMemArea(g_dsp.r[sreg],g_dsp.r[0x3]))
|
||||
if (IsSameMemArea(g_dsp.r[sreg], g_dsp.r[DSP_REG_AR3]))
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[sreg]));
|
||||
else
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[0x3]));
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
|
||||
writeToBackLog(2, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]));
|
||||
} else {
|
||||
writeToBackLog(0, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[dreg]));
|
||||
|
||||
if (IsSameMemArea(g_dsp.r[dreg],g_dsp.r[0x3]))
|
||||
if (IsSameMemArea(g_dsp.r[dreg], g_dsp.r[DSP_REG_AR3]))
|
||||
writeToBackLog(1, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[dreg]));
|
||||
else
|
||||
writeToBackLog(1, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[0x3]));
|
||||
writeToBackLog(1, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
|
||||
writeToBackLog(2, dreg, dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]));
|
||||
}
|
||||
@ -362,22 +362,22 @@ void ldm(const UDSPInstruction& opc)
|
||||
u8 rreg = (opc.hex >> 4) & 0x1;
|
||||
u8 sreg = opc.hex & 0x3;
|
||||
|
||||
if (sreg != 0x03) {
|
||||
if (sreg != DSP_REG_AR3) {
|
||||
writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[sreg]));
|
||||
|
||||
if (IsSameMemArea(g_dsp.r[sreg],g_dsp.r[0x3]))
|
||||
if (IsSameMemArea(g_dsp.r[sreg], g_dsp.r[DSP_REG_AR3]))
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[sreg]));
|
||||
else
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[0x3]));
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
|
||||
writeToBackLog(2, sreg, dsp_increment_addr_reg(sreg));
|
||||
} else {
|
||||
writeToBackLog(0, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[dreg]));
|
||||
|
||||
if (IsSameMemArea(g_dsp.r[dreg],g_dsp.r[0x3]))
|
||||
if (IsSameMemArea(g_dsp.r[dreg], g_dsp.r[DSP_REG_AR3]))
|
||||
writeToBackLog(1, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[dreg]));
|
||||
else
|
||||
writeToBackLog(1, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[0x3]));
|
||||
writeToBackLog(1, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
|
||||
writeToBackLog(2, dreg, dsp_increment_addr_reg(dreg));
|
||||
}
|
||||
@ -395,22 +395,22 @@ void ldnm(const UDSPInstruction& opc)
|
||||
u8 rreg = (opc.hex >> 4) & 0x1;
|
||||
u8 sreg = opc.hex & 0x3;
|
||||
|
||||
if (sreg != 0x03) {
|
||||
if (sreg != DSP_REG_AR3) {
|
||||
writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[sreg]));
|
||||
|
||||
if (IsSameMemArea(g_dsp.r[sreg],g_dsp.r[0x3]))
|
||||
if (IsSameMemArea(g_dsp.r[sreg], g_dsp.r[DSP_REG_AR3]))
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[sreg]));
|
||||
else
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[0x3]));
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
|
||||
writeToBackLog(2, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]));
|
||||
} else {
|
||||
writeToBackLog(0, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[dreg]));
|
||||
|
||||
if (IsSameMemArea(g_dsp.r[dreg],g_dsp.r[0x3]))
|
||||
if (IsSameMemArea(g_dsp.r[dreg], g_dsp.r[DSP_REG_AR3]))
|
||||
writeToBackLog(1, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[dreg]));
|
||||
else
|
||||
writeToBackLog(1, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[0x3]));
|
||||
writeToBackLog(1, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
|
||||
writeToBackLog(2, dreg, dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]));
|
||||
}
|
||||
|
||||
@ -84,10 +84,11 @@ void clrp(const UDSPInstruction& opc)
|
||||
// Magic numbers taken from duddie's doc
|
||||
// These are probably a bad idea to put here.
|
||||
zeroWriteBackLog();
|
||||
g_dsp.r[0x14] = 0x0000;
|
||||
g_dsp.r[0x15] = 0xfff0;
|
||||
g_dsp.r[0x16] = 0x00ff;
|
||||
g_dsp.r[0x17] = 0x0010;
|
||||
g_dsp.r[DSP_REG_PRODL] = 0x0000;
|
||||
g_dsp.r[DSP_REG_PRODM] = 0xfff0;
|
||||
g_dsp.r[DSP_REG_PRODH] = 0x00ff;
|
||||
g_dsp.r[DSP_REG_PRODM2] = 0x0010;
|
||||
// 00ff_(fff0 + 0010)_0000 = 0100_0000_0000, conveniently, lower 40bits = 0
|
||||
}
|
||||
|
||||
// MOVP $acD
|
||||
|
||||
Reference in New Issue
Block a user