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PowerPC: Parametrize DMAL macro.

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This commit is contained in:
Admiral H. Curtiss
2023-01-09 20:56:18 +01:00
parent 2374365274
commit 38529a2d8d
2 changed files with 6 additions and 6 deletions
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10
Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp
View File

@ -390,20 +390,20 @@ void Interpreter::mtspr(UGeckoInstruction inst)
case SPR_DMAL: case SPR_DMAL:
// Locked cache<->Memory DMA // Locked cache<->Memory DMA
// Total fake, we ignore that DMAs take time. // Total fake, we ignore that DMAs take time.
if (DMAL.DMA_T) if (DMAL(PowerPC::ppcState).DMA_T)
{ {
const u32 mem_address = DMAU(PowerPC::ppcState).MEM_ADDR << 5; const u32 mem_address = DMAU(PowerPC::ppcState).MEM_ADDR << 5;
const u32 cache_address = DMAL.LC_ADDR << 5; const u32 cache_address = DMAL(PowerPC::ppcState).LC_ADDR << 5;
u32 length = ((DMAU(PowerPC::ppcState).DMA_LEN_U << 2) | DMAL.DMA_LEN_L); u32 length = ((DMAU(PowerPC::ppcState).DMA_LEN_U << 2) | DMAL(PowerPC::ppcState).DMA_LEN_L);
if (length == 0) if (length == 0)
length = 128; length = 128;
if (DMAL.DMA_LD) if (DMAL(PowerPC::ppcState).DMA_LD)
PowerPC::DMA_MemoryToLC(cache_address, mem_address, length); PowerPC::DMA_MemoryToLC(cache_address, mem_address, length);
else else
PowerPC::DMA_LCToMemory(mem_address, cache_address, length); PowerPC::DMA_LCToMemory(mem_address, cache_address, length);
} }
DMAL.DMA_T = 0; DMAL(PowerPC::ppcState).DMA_T = 0;
break; break;
case SPR_L2CR: case SPR_L2CR:

2
Source/Core/Core/PowerPC/PowerPC.h
View File

@ -239,7 +239,7 @@ void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst);
#define HID2(ppc_state) ((UReg_HID2&)(ppc_state).spr[SPR_HID2]) #define HID2(ppc_state) ((UReg_HID2&)(ppc_state).spr[SPR_HID2])
#define HID4(ppc_state) ((UReg_HID4&)(ppc_state).spr[SPR_HID4]) #define HID4(ppc_state) ((UReg_HID4&)(ppc_state).spr[SPR_HID4])
#define DMAU(ppc_state) (*(UReg_DMAU*)&(ppc_state).spr[SPR_DMAU]) #define DMAU(ppc_state) (*(UReg_DMAU*)&(ppc_state).spr[SPR_DMAU])
#define DMAL (*(UReg_DMAL*)&PowerPC::ppcState.spr[SPR_DMAL]) #define DMAL(ppc_state) (*(UReg_DMAL*)&(ppc_state).spr[SPR_DMAL])
#define MMCR0 ((UReg_MMCR0&)PowerPC::ppcState.spr[SPR_MMCR0]) #define MMCR0 ((UReg_MMCR0&)PowerPC::ppcState.spr[SPR_MMCR0])
#define MMCR1 ((UReg_MMCR1&)PowerPC::ppcState.spr[SPR_MMCR1]) #define MMCR1 ((UReg_MMCR1&)PowerPC::ppcState.spr[SPR_MMCR1])
#define THRM1 ((UReg_THRM12&)PowerPC::ppcState.spr[SPR_THRM1]) #define THRM1 ((UReg_THRM12&)PowerPC::ppcState.spr[SPR_THRM1])