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give serial port 1 it's own log

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git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3154 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
Shawn Hoffman
2009-05-04 19:28:53 +00:00
parent c6a16ac3b6
commit 3b173a2dad
3 changed files with 121 additions and 109 deletions
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1
Source/Core/Common/Src/Log.h
View File

@ -52,6 +52,7 @@ enum LOG_TYPE {
PERIPHERALINTERFACE, PERIPHERALINTERFACE,
PIXELENGINE, PIXELENGINE,
SERIALINTERFACE, SERIALINTERFACE,
SP1,
STREAMINGINTERFACE, STREAMINGINTERFACE,
VIDEO, VIDEO,
VIDEOINTERFACE, VIDEOINTERFACE,

1
Source/Core/Common/Src/LogManager.cpp
View File

@ -34,6 +34,7 @@ LogManager::LogManager()\
m_Log[LogTypes::SERIALINTERFACE] = new LogContainer("SI", "SerialInt"); m_Log[LogTypes::SERIALINTERFACE] = new LogContainer("SI", "SerialInt");
m_Log[LogTypes::PERIPHERALINTERFACE]= new LogContainer("PI", "PeripheralInt"); m_Log[LogTypes::PERIPHERALINTERFACE]= new LogContainer("PI", "PeripheralInt");
m_Log[LogTypes::MEMMAP] = new LogContainer("MI", "MI & memmap"); m_Log[LogTypes::MEMMAP] = new LogContainer("MI", "MI & memmap");
m_Log[LogTypes::SP1] = new LogContainer("SP1", "Serial Port 1");
m_Log[LogTypes::STREAMINGINTERFACE] = new LogContainer("Stream", "StreamingInt"); m_Log[LogTypes::STREAMINGINTERFACE] = new LogContainer("Stream", "StreamingInt");
m_Log[LogTypes::DSPINTERFACE] = new LogContainer("DSP", "DSPInterface"); m_Log[LogTypes::DSPINTERFACE] = new LogContainer("DSP", "DSPInterface");
m_Log[LogTypes::DVDINTERFACE] = new LogContainer("DVD", "DVDInterface"); m_Log[LogTypes::DVDINTERFACE] = new LogContainer("DVD", "DVDInterface");

128
Source/Core/Core/Src/HW/EXI_DeviceEthernet.cpp
View File

@ -21,17 +21,45 @@
#include "EXI_Device.h" #include "EXI_Device.h"
#include "EXI_DeviceEthernet.h" #include "EXI_DeviceEthernet.h"
inline u8 makemaskb(int start, int end) {
return (u8)_rotl((2 << (end - start)) - 1, 7 - end);
}
inline u32 makemaskh(int start, int end) {
return (u32)_rotl((2 << (end - start)) - 1, 15 - end);
}
inline u32 makemaskw(int start, int end) {
return _rotl((2 << (end - start)) - 1, 31 - end);
}
inline u8 getbitsb(u8 byte, int start, int end) {
return (byte & makemaskb(start, end)) >> u8(7 - end);
}
inline u32 getbitsh(u32 hword, int start, int end) {
return (hword & makemaskh(start, end)) >> u32(15 - end);
}
inline u32 getbitsw(u32 dword, int start, int end) {
return (dword & makemaskw(start, end)) >> (31 - end);
}
enum { enum {
EXPECT_NONE = 0, EXPECT_NONE = 0,
EXPECT_ID, EXPECT_ID,
}; };
#define MAKE(type, arg) (*(type *)&(arg))
#define RISE(flags) ((SwappedData & (flags)) && !(mBbaMem[0x00] & (flags)))
#define BBA_INTERRUPT_RECV 0x02 #define BBA_INTERRUPT_RECV 0x02
#define BBA_INTERRUPT_SENT 0x04 #define BBA_INTERRUPT_SENT 0x04
#define BBA_INTERRUPT_RECV_ERROR 0x08 #define BBA_INTERRUPT_RECV_ERROR 0x08
#define BBA_INTERRUPT_SEND_ERROR 0x10 #define BBA_INTERRUPT_SEND_ERROR 0x10
int mPacketsSent = 0; int mPacketsSent = 0;
u8 mac_address[6] = {0x4D, 0xFF, 0x11, 0x88, 0xF1, 0x76}; u8 mac_address[6] = {0x4D, 0xFF, 0x11, 0x88, 0xF1, 0x76};
unsigned int Expecting; unsigned int Expecting;
CEXIETHERNET::CEXIETHERNET() : CEXIETHERNET::CEXIETHERNET() :
m_uPosition(0), m_uPosition(0),
m_uCommand(0), m_uCommand(0),
@ -83,25 +111,6 @@ bool CEXIETHERNET::isActivated()
// Todo: Return actual check // Todo: Return actual check
return Activated; return Activated;
} }
inline u8 makemaskb(int start, int end) {
return (u8)_rotl((2 << (end - start)) - 1, 7 - end);
}
inline u32 makemaskh(int start, int end) {
return (u32)_rotl((2 << (end - start)) - 1, 15 - end);
}
inline u32 makemaskw(int start, int end) {
return _rotl((2 << (end - start)) - 1, 31 - end);
}
inline u8 getbitsb(u8 byte, int start, int end) {
return (byte & makemaskb(start, end)) >> u8(7 - end);
}
inline u32 getbitsh(u32 hword, int start, int end) {
return (hword & makemaskh(start, end)) >> u32(15 - end);
}
inline u32 getbitsw(u32 dword, int start, int end) {
return (dword & makemaskw(start, end)) >> (31 - end);
}
#define MAKE(type, arg) (*(type *)&(arg))
void CEXIETHERNET::recordSendComplete() void CEXIETHERNET::recordSendComplete()
{ {
@ -109,7 +118,7 @@ void CEXIETHERNET::recordSendComplete()
if(mBbaMem[0x08] & BBA_INTERRUPT_SENT) if(mBbaMem[0x08] & BBA_INTERRUPT_SENT)
{ {
mBbaMem[0x09] |= BBA_INTERRUPT_SENT; mBbaMem[0x09] |= BBA_INTERRUPT_SENT;
printf("BBA Send interrupt raised\n"); INFO_LOG(SP1, "BBA Send interrupt raised\n");
exit(0); exit(0);
//interrupt.raiseEXI("BBA Send"); //interrupt.raiseEXI("BBA Send");
} }
@ -118,12 +127,12 @@ void CEXIETHERNET::recordSendComplete()
bool CEXIETHERNET::sendPacket(u8 *etherpckt, size_t size) bool CEXIETHERNET::sendPacket(u8 *etherpckt, size_t size)
{ {
printf("Packet: 0x"); INFO_LOG(SP1, "Packet: 0x");
for(int a = 0; a < size; ++a) for(int a = 0; a < size; ++a)
{ {
printf("%02X", etherpckt[a]); INFO_LOG(SP1, "%02X", etherpckt[a]);
} }
printf(" : Size: %d\n", size); INFO_LOG(SP1, " : Size: %d\n", size);
/*DWORD numBytesWrit; /*DWORD numBytesWrit;
OVERLAPPED overlap; OVERLAPPED overlap;
ZERO_OBJECT(overlap); ZERO_OBJECT(overlap);
@ -141,17 +150,17 @@ bool CEXIETHERNET::sendPacket(u8 *etherpckt, size_t size)
void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize) void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
{ {
printf("IMM Write, size 0x%x, data 0x%x mWriteP 0x%x\n", _uSize, _uData, mWriteP); INFO_LOG(SP1, "IMM Write, size 0x%x, data 0x%x mWriteP 0x%x\n", _uSize, _uData, mWriteP);
if (mExpectVariableLengthImmWrite) if (mExpectVariableLengthImmWrite)
{ {
printf("Not doing expecting variable length imm write!\n"); INFO_LOG(SP1, "Not doing expecting variable length imm write!\n");
exit(0); exit(0);
} }
else if (mWriteP != INVALID_P) else if (mWriteP != INVALID_P)
{ {
if (mWriteP + _uSize > BBAMEM_SIZE) if (mWriteP + _uSize > BBAMEM_SIZE)
{ {
printf("Write error: mWriteP + size = 0x%04X + %i\n", mWriteP, _uSize); INFO_LOG(SP1, "Write error: mWriteP + size = 0x%04X + %i\n", mWriteP, _uSize);
exit(0); exit(0);
} }
//BBADEGUB("Write to BBA address 0x%0*X, %i byte%s: 0x%0*X\n",mWriteP >= CB_OFFSET ? 4 : 2, mWriteP, size, (size==1?"":"s"), size*2, data); //BBADEGUB("Write to BBA address 0x%0*X, %i byte%s: 0x%0*X\n",mWriteP >= CB_OFFSET ? 4 : 2, mWriteP, size, (size==1?"":"s"), size*2, data);
@ -159,7 +168,7 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
switch (mWriteP) switch (mWriteP)
{ {
case 0x09: case 0x09:
printf("mWriteP is %x\n", mWriteP); INFO_LOG(SP1, "mWriteP is %x\n", mWriteP);
//BBADEGUB("BBA Interrupt reset 0x%02X & ~(0x%02X) => 0x%02X\n", mBbaMem[0x09], MAKE(BYTE, data), mBbaMem[0x09] & ~MAKE(BYTE, data)); //BBADEGUB("BBA Interrupt reset 0x%02X & ~(0x%02X) => 0x%02X\n", mBbaMem[0x09], MAKE(BYTE, data), mBbaMem[0x09] & ~MAKE(BYTE, data));
//assert(_uSize == 1); //assert(_uSize == 1);
// TODO: Should we swap our data? // TODO: Should we swap our data?
@ -170,26 +179,25 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
{ {
u32 SwappedData = Common::swap32(_uData); u32 SwappedData = Common::swap32(_uData);
// TODO: Should we swap our data? // TODO: Should we swap our data?
#define RISE(flags) ((SwappedData & (flags)) && !(mBbaMem[0x00] & (flags)))
if (RISE(BBA_NCRA_RESET)) if (RISE(BBA_NCRA_RESET))
{ {
// Normal // Normal
// Whinecube did nothing else as well // Whinecube did nothing else as well
printf("BBA Reset\n"); INFO_LOG(SP1, "BBA Reset\n");
} }
if (RISE(BBA_NCRA_SR) && isActivated()) if (RISE(BBA_NCRA_SR) && isActivated())
{ {
printf("BBA Start Recieve\n"); INFO_LOG(SP1, "BBA Start Recieve\n");
exit(0); exit(0);
// TODO: Need to make our virtual network device start receiving // TODO: Need to make our virtual network device start receiving
//HWGLE(startRecv()); //HWGLE(startRecv());
} }
if (RISE(BBA_NCRA_ST1)) if (RISE(BBA_NCRA_ST1))
{ {
printf("BBA Start Transmit\n"); INFO_LOG(SP1, "BBA Start Transmit\n");
if (!mReadyToSend) if (!mReadyToSend)
{ {
printf("Not ready to send!\n"); INFO_LOG(SP1, "Not ready to send!\n");
exit(0); exit(0);
//throw hardware_fatal_exception("BBA Transmit without a packet!"); //throw hardware_fatal_exception("BBA Transmit without a packet!");
} }
@ -202,7 +210,7 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
} }
break; break;
case BBA_NWAYC: case BBA_NWAYC:
printf("mWriteP is %x\n", mWriteP); INFO_LOG(SP1, "mWriteP is %x\n", mWriteP);
exit(0); exit(0);
/*if(data & (BBA_NWAYC_ANE | BBA_NWAYC_ANS_RA)) /*if(data & (BBA_NWAYC_ANE | BBA_NWAYC_ANS_RA))
{ {
@ -214,7 +222,7 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
}*/ }*/
break; break;
case 0x18: //RRP - Receive Buffer Read Page Pointer case 0x18: //RRP - Receive Buffer Read Page Pointer
printf("mWriteP is %x\n", mWriteP); INFO_LOG(SP1, "mWriteP is %x\n", mWriteP);
exit(0); exit(0);
/*MYASSERT(size == 2 || size == 1); /*MYASSERT(size == 2 || size == 1);
mRBRPP = (BYTE)data << 8; //I hope this works with both write sizes. mRBRPP = (BYTE)data << 8; //I hope this works with both write sizes.
@ -222,19 +230,20 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
HWGLE(checkRecvBuffer());*/ HWGLE(checkRecvBuffer());*/
break; break;
case 0x16: //RWP case 0x16: //RWP
printf("mWriteP is %x\n", mWriteP); INFO_LOG(SP1, "mWriteP is %x\n", mWriteP);
exit(0); exit(0);
/*MYASSERT(size == 2 || size == 1); /*MYASSERT(size == 2 || size == 1);
MYASSERT(data == DWORD((WORD)mCbw.p_write() + CB_OFFSET) >> 8);*/ MYASSERT(data == DWORD((WORD)mCbw.p_write() + CB_OFFSET) >> 8);*/
break; break;
default: default:
printf("Default one!Size 0x%x _uData: 0x%08x Swapped 0x%08x to 0x%x\n", _uSize, _uData, Common::swap32(_uData),mWriteP); INFO_LOG(SP1, "Default one!Size 0x%x _uData: 0x%08x Swapped 0x%08x to 0x%x\n", _uSize, _uData, Common::swap32(_uData),mWriteP);
u32 SwappedData = Common::swap32(_uData); u32 SwappedData = Common::swap32(_uData);
memcpy(mBbaMem + mWriteP, &SwappedData, _uSize); memcpy(mBbaMem + mWriteP, &SwappedData, _uSize);
mWriteP = mWriteP + _uSize; mWriteP = mWriteP + _uSize;
} }
return; return;
}else if(_uSize == 2 && _uData == 0) }
else if (_uSize == 2 && _uData == 0)
{ {
// Device ID Request // Device ID Request
// 100% this returns correctly // 100% this returns correctly
@ -243,8 +252,9 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
return; return;
} }
else if ((_uSize == 4 && (_uData & 0xC0000000) == 0xC0000000) || (_uSize == 2 && (_uData & 0x4000) == 0x4000)) else if ((_uSize == 4 && (_uData & 0xC0000000) == 0xC0000000) || (_uSize == 2 && (_uData & 0x4000) == 0x4000))
{ // Write to BBA Register {
printf("Write to BBA register!\n"); // Write to BBA Register
INFO_LOG(SP1, "Write to BBA register!\n");
u32 SwappedData = Common::swap32(_uData); u32 SwappedData = Common::swap32(_uData);
//u32 SwappedData = _uData; //u32 SwappedData = _uData;
if (_uSize == 4) if (_uSize == 4)
@ -257,19 +267,18 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
{ {
mWriteBuffer.clear(); mWriteBuffer.clear();
mExpectVariableLengthImmWrite = true; mExpectVariableLengthImmWrite = true;
printf("Prepared for variable length write to address 0x48\n"); INFO_LOG(SP1, "Prepared for variable length write to address 0x48\n");
} }
else else
{ {
INFO_LOG(SP1, "BBA Write pointer set to 0x%0*X\n", _uSize, mWriteP);
printf("BBA Write pointer set to 0x%0*X\n", _uSize, mWriteP);
//exit(0); //exit(0);
} }
return; return;
} }
else if ((_uSize == 4 && (_uData & 0xC0000000) == 0x80000000) || (_uSize == 2 && (_uData & 0x4000) == 0x0000)) else if ((_uSize == 4 && (_uData & 0xC0000000) == 0x80000000) || (_uSize == 2 && (_uData & 0x4000) == 0x0000))
{ {
printf("Read from BBA register!\n"); INFO_LOG(SP1, "Read from BBA register!\n");
//u32 SwappedData = Common::swap32(_uData); //u32 SwappedData = Common::swap32(_uData);
u32 SwappedData = _uData; u32 SwappedData = _uData;
// Read from BBA Register! // Read from BBA Register!
@ -278,7 +287,7 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
mReadP = (u32)getbitsw(SwappedData, 8, 23); mReadP = (u32)getbitsw(SwappedData, 8, 23);
if (mReadP >= BBAMEM_SIZE) if (mReadP >= BBAMEM_SIZE)
{ {
printf("Illegal BBA address: 0x%04X\n", mReadP); INFO_LOG(SP1, "Illegal BBA address: 0x%04X\n", mReadP);
//if(g::bouehr) //if(g::bouehr)
exit(0); exit(0);
//return EXI_UNHANDLED; //return EXI_UNHANDLED;
@ -291,23 +300,23 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
switch (mReadP) switch (mReadP)
{ {
case 0x20: //MAC address case 0x20: //MAC address
printf("Mac Address!\n"); INFO_LOG(SP1, "Mac Address!\n");
memcpy(mBbaMem + mReadP, mac_address, 6); memcpy(mBbaMem + mReadP, mac_address, 6);
break; break;
case 0x01: //Revision ID case 0x01: //Revision ID
break; break;
case 0x16: //RWP - Receive Buffer Write Page Pointer case 0x16: //RWP - Receive Buffer Write Page Pointer
printf("RWP!\n"); INFO_LOG(SP1, "RWP!\n");
exit(0); exit(0);
//MAKE(WORD, mBbaMem[mReadP]) = ((WORD)mCbw.p_write() + CB_OFFSET) >> 8; //MAKE(WORD, mBbaMem[mReadP]) = ((WORD)mCbw.p_write() + CB_OFFSET) >> 8;
break; break;
case 0x18: //RRP - Receive Buffer Read Page Pointer case 0x18: //RRP - Receive Buffer Read Page Pointer
printf("RRP!\n"); INFO_LOG(SP1, "RRP!\n");
exit(0); exit(0);
//MAKE(WORD, mBbaMem[mReadP]) = (mRBRPP) >> 8; //MAKE(WORD, mBbaMem[mReadP]) = (mRBRPP) >> 8;
break; break;
case 0x3A: //bit 1 set if no data available case 0x3A: //bit 1 set if no data available
printf("Bit 1 set!\n"); INFO_LOG(SP1, "Bit 1 set!\n");
exit(0); exit(0);
//mBbaMem[mReadP] = !mRBEmpty; //mBbaMem[mReadP] = !mRBEmpty;
break; break;
@ -316,28 +325,29 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
//mBbaMem[mReadP] = 0x00; //mBbaMem[mReadP] = 0x00;
//if(!sendInProgress()) //if(!sendInProgress())
mBbaMem[mReadP] &= ~(0x06); mBbaMem[mReadP] &= ~(0x06);
printf("mBbaMem[0x%x] &= ~(0x06);! Now %x\n", mReadP, mBbaMem[mReadP]); INFO_LOG(SP1, "mBbaMem[0x%x] &= ~(0x06);! Now %x\n", mReadP, mBbaMem[mReadP]);
//exit(0); //exit(0);
break; break;
case 0x03: case 0x03:
mBbaMem[mReadP] = 0x80; mBbaMem[mReadP] = 0x80;
printf("mBbaMem[0x%x] = 0x80;! Now %x\n", mReadP, mBbaMem[mReadP]); INFO_LOG(SP1, "mBbaMem[0x%x] = 0x80;! Now %x\n", mReadP, mBbaMem[mReadP]);
exit(0); exit(0);
break; break;
} }
//BBADEGUB("BBA Read pointer set to 0x%0*X\n", size, mReadP); //BBADEGUB("BBA Read pointer set to 0x%0*X\n", size, mReadP);
return; return;
} }
printf("Not expecting ImmWrite of size %d\n", _uSize); INFO_LOG(SP1, "Not expecting ImmWrite of size %d\n", _uSize);
exit(0); exit(0);
} }
u32 CEXIETHERNET::ImmRead(u32 _uSize) u32 CEXIETHERNET::ImmRead(u32 _uSize)
{ {
printf("IMM Read, size 0x%x\n", _uSize); INFO_LOG(SP1, "IMM Read, size 0x%x\n", _uSize);
if (mExpectSpecialImmRead) if (mExpectSpecialImmRead)
{ {
// 100% that this returns correctly // 100% that this returns correctly
printf("special IMMRead\n"); INFO_LOG(SP1, "special IMMRead\n");
mExpectSpecialImmRead = false; mExpectSpecialImmRead = false;
return mSpecialImmData; return mSpecialImmData;
} }
@ -345,7 +355,7 @@ u32 CEXIETHERNET::ImmRead(u32 _uSize)
{ {
if (mReadP + _uSize > BBAMEM_SIZE) if (mReadP + _uSize > BBAMEM_SIZE)
{ {
printf("Read error: mReadP + size = 0x%04X + %i\n", mReadP, _uSize); INFO_LOG(SP1, "Read error: mReadP + size = 0x%04X + %i\n", mReadP, _uSize);
exit(0); exit(0);
} }
u32 uResult = 0; u32 uResult = 0;
@ -353,26 +363,26 @@ u32 CEXIETHERNET::ImmRead(u32 _uSize)
// TODO: We do as well? // TODO: We do as well?
//uResult = Common::swap32(uResult); //Whinecube : we have a byteswap problem... //uResult = Common::swap32(uResult); //Whinecube : we have a byteswap problem...
printf("Read from BBA address 0x%0*X, %i byte%s: 0x%0*X\n",mReadP >= CB_OFFSET ? 4 : 2, mReadP, _uSize, (_uSize==1?"":"s"),_uSize*2, getbitsw(uResult, 0, _uSize * 8 - 1)); INFO_LOG(SP1, "Read from BBA address 0x%0*X, %i byte%s: 0x%0*X\n",mReadP >= CB_OFFSET ? 4 : 2, mReadP, _uSize, (_uSize==1?"":"s"),_uSize*2, getbitsw(uResult, 0, _uSize * 8 - 1));
mReadP = mReadP + _uSize; mReadP = mReadP + _uSize;
return uResult; return uResult;
} }
else else
{ {
printf("Unhandled IMM read of %d bytes\n", _uSize); INFO_LOG(SP1, "Unhandled IMM read of %d bytes\n", _uSize);
} }
printf("Not Expecting IMMRead of size %d!\n", _uSize); INFO_LOG(SP1, "Not Expecting IMMRead of size %d!\n", _uSize);
exit(0); exit(0);
} }
void CEXIETHERNET::DMAWrite(u32 _uAddr, u32 _uSize) void CEXIETHERNET::DMAWrite(u32 _uAddr, u32 _uSize)
{ {
printf("DMAW\n"); INFO_LOG(SP1, "DMAW\n");
exit(0); exit(0);
} }
void CEXIETHERNET::DMARead(u32 _uAddr, u32 _uSize) void CEXIETHERNET::DMARead(u32 _uAddr, u32 _uSize)
{ {
printf("DMAR\n"); INFO_LOG(SP1, "DMAR\n");
exit(0); exit(0);
}; };