piwalker/dolphin
1
0
Fork 0
mirror of https://github.com/dolphin-emu/dolphin.git synced 2024-11-14 21:37:52 -07:00
Code Issues Actions Packages Projects Releases Wiki Activity

DSPLLE: Rename cr to control_reg

Browse Source 
Before, there were two distinct fields called cr and r.cr, which is needlessly confusing (see the comment in DSPCore.h).
This commit is contained in:
Pokechu22 2022-06-07 20:45:52 -07:00
parent 107a928452
commit 3ceda1df8c
9 changed files with 26 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Source/Core/Core/DSP/DSPCore.cpp
View File

@ -161,7 +161,7 @@ bool SDSP::Initialize(const DSPInitOptions& opts)
r.sr |= SR_INT_ENABLE;
r.sr |= SR_EXT_INT_ENABLE;
cr = CR_INIT | CR_HALT;
control_reg = CR_INIT | CR_HALT;
InitializeIFX();
// Mostly keep IRAM write protected. We unprotect only when DMA-ing
// in new ucodes.
@ -210,7 +210,7 @@ void SDSP::CheckExternalInterrupt()
// Signal the SPU about new mail
SetException(ExceptionType::ExternalInterrupt);
cr &= ~CR_EXTERNAL_INT;
control_reg &= ~CR_EXTERNAL_INT;
}
void SDSP::CheckExceptions()
@ -378,7 +378,7 @@ void SDSP::DoState(PointerWrap& p)
{
p.Do(r);
p.Do(pc);
p.Do(cr);
p.Do(control_reg);
p.Do(reg_stack_ptrs);
p.Do(exceptions);
p.Do(external_interrupt_waiting);

4
Source/Core/Core/DSP/DSPCore.h
View File

@ -419,11 +419,11 @@ struct SDSP
DSP_Regs r{};
u16 pc = 0;
// This is NOT the same cr as r.cr.
// This is NOT the same as r.cr.
// This register is shared with the main emulation, see DSP.cpp
// The engine has control over 0x0C07 of this reg.
// Bits are defined in a struct in DSP.cpp.
u16 cr = 0;
u16 control_reg = 0;
u8 reg_stack_ptrs[4]{};
u8 exceptions = 0; // pending exceptions

2
Source/Core/Core/DSP/Interpreter/DSPIntBranch.cpp
View File

@ -127,7 +127,7 @@ void Interpreter::rti(const UDSPInstruction opc)
void Interpreter::halt(const UDSPInstruction)
{
auto& state = m_dsp_core.DSPState();
state.cr |= CR_HALT;
state.control_reg |= CR_HALT;
state.pc--;
}

22
Source/Core/Core/DSP/Interpreter/DSPInterpreter.cpp
View File

@ -81,7 +81,7 @@ int Interpreter::RunCyclesThread(int cycles)
while (true)
{
if ((state.cr & CR_HALT) != 0)
if ((state.control_reg & CR_HALT) != 0)
return 0;
if (state.external_interrupt_waiting.exchange(false, std::memory_order_acquire))
@ -104,7 +104,7 @@ int Interpreter::RunCyclesDebug(int cycles)
// First, let's run a few cycles with no idle skipping so that things can progress a bit.
for (int i = 0; i < 8; i++)
{
if ((state.cr & CR_HALT) != 0)
if ((state.control_reg & CR_HALT) != 0)
return 0;
if (m_dsp_core.BreakPoints().IsAddressBreakPoint(state.pc))
@ -124,7 +124,7 @@ int Interpreter::RunCyclesDebug(int cycles)
// idle loops.
for (int i = 0; i < 8; i++)
{
if ((state.cr & CR_HALT) != 0)
if ((state.control_reg & CR_HALT) != 0)
return 0;
if (m_dsp_core.BreakPoints().IsAddressBreakPoint(state.pc))
@ -169,7 +169,7 @@ int Interpreter::RunCycles(int cycles)
// progress a bit.
for (int i = 0; i < 8; i++)
{
if ((state.cr & CR_HALT) != 0)
if ((state.control_reg & CR_HALT) != 0)
return 0;
Step();
@ -185,7 +185,7 @@ int Interpreter::RunCycles(int cycles)
// idle loops.
for (int i = 0; i < 8; i++)
{
if ((state.cr & CR_HALT) != 0)
if ((state.control_reg & CR_HALT) != 0)
return 0;
if (state.GetAnalyzer().IsIdleSkip(state.pc))
@ -212,7 +212,7 @@ int Interpreter::RunCycles(int cycles)
}
// NOTE: These have nothing to do with SDSP::r::cr!
void Interpreter::WriteCR(u16 val)
void Interpreter::WriteControlRegister(u16 val)
{
// reset
if ((val & CR_RESET) != 0)
@ -232,23 +232,23 @@ void Interpreter::WriteCR(u16 val)
}
// update cr
m_dsp_core.DSPState().cr = val;
m_dsp_core.DSPState().control_reg = val;
}
u16 Interpreter::ReadCR()
u16 Interpreter::ReadControlRegister()
{
auto& state = m_dsp_core.DSPState();
if ((state.pc & 0x8000) != 0)
{
state.cr |= CR_INIT;
state.control_reg |= CR_INIT;
}
else
{
state.cr &= ~CR_INIT;
state.control_reg &= ~CR_INIT;
}
return state.cr;
return state.control_reg;
}
void Interpreter::SetSRFlag(u16 flag)

4
Source/Core/Core/DSP/Interpreter/DSPInterpreter.h
View File

@ -32,8 +32,8 @@ public:
int RunCycles(int cycles);
int RunCyclesDebug(int cycles);
void WriteCR(u16 val);
u16 ReadCR();
void WriteControlRegister(u16 val);
u16 ReadControlRegister();
void SetSRFlag(u16 flag);
bool IsSRFlagSet(u16 flag) const;

6
Source/Core/Core/DSP/Jit/x64/DSPEmitter.cpp
View File

@ -443,7 +443,7 @@ void DSPEmitter::CompileDispatcher()
}
// Check for DSP halt
TEST(8, M_SDSP_cr(), Imm8(CR_HALT));
TEST(8, M_SDSP_control_reg(), Imm8(CR_HALT));
FixupBranch _halt = J_CC(CC_NE);
// Execute block. Cycles executed returned in EAX.
@ -484,9 +484,9 @@ Gen::OpArg DSPEmitter::M_SDSP_exceptions()
return MDisp(R15, static_cast<int>(offsetof(SDSP, exceptions)));
}
Gen::OpArg DSPEmitter::M_SDSP_cr()
Gen::OpArg DSPEmitter::M_SDSP_control_reg()
{
return MDisp(R15, static_cast<int>(offsetof(SDSP, cr)));
return MDisp(R15, static_cast<int>(offsetof(SDSP, control_reg)));
}
Gen::OpArg DSPEmitter::M_SDSP_external_interrupt_waiting()

2
Source/Core/Core/DSP/Jit/x64/DSPEmitter.h
View File

@ -292,7 +292,7 @@ private:
// SDSP memory offset helpers
Gen::OpArg M_SDSP_pc();
Gen::OpArg M_SDSP_exceptions();
Gen::OpArg M_SDSP_cr();
Gen::OpArg M_SDSP_control_reg();
Gen::OpArg M_SDSP_external_interrupt_waiting();
Gen::OpArg M_SDSP_r_st(size_t index);
Gen::OpArg M_SDSP_reg_stack_ptrs(size_t index);

2
Source/Core/Core/DSP/Jit/x64/DSPJitBranch.cpp
View File

@ -304,7 +304,7 @@ void DSPEmitter::rti(const UDSPInstruction opc)
// Stops execution of DSP code. Sets bit DSP_CR_HALT in register DREG_CR.
void DSPEmitter::halt(const UDSPInstruction)
{
OR(16, M_SDSP_cr(), Imm16(CR_HALT));
OR(16, M_SDSP_control_reg(), Imm16(CR_HALT));
// g_dsp.pc = dsp_reg_load_stack(StackRegister::Call);
dsp_reg_load_stack(StackRegister::Call);
MOV(16, M_SDSP_pc(), R(DX));

4
Source/Core/Core/HW/DSPLLE/DSPLLE.cpp
View File

@ -183,7 +183,7 @@ void DSPLLE::Shutdown()
u16 DSPLLE::DSP_WriteControlRegister(u16 value)
{
m_dsp_core.GetInterpreter().WriteCR(value);
m_dsp_core.GetInterpreter().WriteControlRegister(value);
if ((value & CR_EXTERNAL_INT) != 0)
{
@ -207,7 +207,7 @@ u16 DSPLLE::DSP_WriteControlRegister(u16 value)
u16 DSPLLE::DSP_ReadControlRegister()
{
return m_dsp_core.GetInterpreter().ReadCR();
return m_dsp_core.GetInterpreter().ReadControlRegister();
}
u16 DSPLLE::DSP_ReadMailBoxHigh(bool cpu_mailbox)