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Merge pull request #1660 from Tilka/avx_bitwise

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Fix opcodes of AVX bitwise instructions
This commit is contained in:
Ryan Houdek 2014-12-06 21:58:35 -06:00
commit 40f2333145
3 changed files with 45 additions and 12 deletions
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18
Source/Core/Common/x64Emitter.cpp
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@ -1795,14 +1795,24 @@ void XEmitter::VSUBPD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x6
void XEmitter::VMULPD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, sseMUL, regOp1, regOp2, arg);}
void XEmitter::VDIVPD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, sseDIV, regOp1, regOp2, arg);}
void XEmitter::VSQRTSD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0xF2, sseSQRT, regOp1, regOp2, arg);}
void XEmitter::VPAND(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, sseAND, regOp1, regOp2, arg);}
void XEmitter::VPANDN(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, sseANDN, regOp1, regOp2, arg);}
void XEmitter::VPOR(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, sseOR, regOp1, regOp2, arg);}
void XEmitter::VPXOR(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, sseXOR, regOp1, regOp2, arg);}
void XEmitter::VSHUFPD(X64Reg regOp1, X64Reg regOp2, OpArg arg, u8 shuffle) {WriteAVXOp(0x66, sseSHUF, regOp1, regOp2, arg, 0, 1); Write8(shuffle);}
void XEmitter::VUNPCKLPD(X64Reg regOp1, X64Reg regOp2, OpArg arg){WriteAVXOp(0x66, 0x14, regOp1, regOp2, arg);}
void XEmitter::VUNPCKHPD(X64Reg regOp1, X64Reg regOp2, OpArg arg){WriteAVXOp(0x66, 0x15, regOp1, regOp2, arg);}
void XEmitter::VANDPS(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x00, sseAND, regOp1, regOp2, arg);}
void XEmitter::VANDPD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, sseAND, regOp1, regOp2, arg);}
void XEmitter::VANDNPS(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x00, sseANDN, regOp1, regOp2, arg);}
void XEmitter::VANDNPD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, sseANDN, regOp1, regOp2, arg);}
void XEmitter::VORPS(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x00, sseOR, regOp1, regOp2, arg);}
void XEmitter::VORPD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, sseOR, regOp1, regOp2, arg);}
void XEmitter::VXORPS(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x00, sseXOR, regOp1, regOp2, arg);}
void XEmitter::VXORPD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, sseXOR, regOp1, regOp2, arg);}
void XEmitter::VPAND(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, 0xDB, regOp1, regOp2, arg);}
void XEmitter::VPANDN(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, 0xDF, regOp1, regOp2, arg);}
void XEmitter::VPOR(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, 0xEB, regOp1, regOp2, arg);}
void XEmitter::VPXOR(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, 0xEF, regOp1, regOp2, arg);}
void XEmitter::VFMADD132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, 0x3898, regOp1, regOp2, arg);}
void XEmitter::VFMADD213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, 0x38A8, regOp1, regOp2, arg);}
void XEmitter::VFMADD231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, 0x38B8, regOp1, regOp2, arg);}

20
Source/Core/Common/x64Emitter.h
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@ -766,15 +766,25 @@ public:
void VMULPD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VDIVPD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VSQRTSD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VPAND(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VPANDN(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VPOR(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VPXOR(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VSHUFPD(X64Reg regOp1, X64Reg regOp2, OpArg arg, u8 shuffle);
void VUNPCKLPD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VUNPCKHPD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
// FMA
void VANDPS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VANDPD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VANDNPS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VANDNPD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VORPS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VORPD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VXORPS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VXORPD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VPAND(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VPANDN(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VPOR(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VPXOR(X64Reg regOp1, X64Reg regOp2, OpArg arg);
// FMA3
void VFMADD132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADD213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADD231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);

19
Source/UnitTests/Common/x64EmitterTest.cpp
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@ -963,15 +963,28 @@ VEX_RMI_TEST(RORX)
for (const auto& regset : regsets) \
for (const auto& r : regset.regs) \
{ \
emitter->Name(r.reg, RAX, R(RAX)); \
emitter->Name(RAX, RAX, R(r.reg)); \
emitter->Name(RAX, r.reg, MatR(R12)); \
emitter->Name(r.reg, XMM0, R(XMM0)); \
emitter->Name(XMM0, XMM0, R(r.reg)); \
emitter->Name(XMM0, r.reg, MatR(R12)); \
ExpectDisassembly(#Name " " + r.name+ ", " + regset.out_name + ", " + regset.out_name + " " \
#Name " " + regset.out_name + ", " + regset.out_name + ", " + r.name + " " \
#Name " " + regset.out_name + ", " + r.name + ", " + regset.size + " ptr ds:[r12] "); \
} \
}
AVX_RRM_TEST(VANDPS, "dqword")
AVX_RRM_TEST(VANDPD, "dqword")
AVX_RRM_TEST(VANDNPS, "dqword")
AVX_RRM_TEST(VANDNPD, "dqword")
AVX_RRM_TEST(VORPS, "dqword")
AVX_RRM_TEST(VORPD, "dqword")
AVX_RRM_TEST(VXORPS, "dqword")
AVX_RRM_TEST(VXORPD, "dqword")
AVX_RRM_TEST(VPAND, "dqword")
AVX_RRM_TEST(VPANDN, "dqword")
AVX_RRM_TEST(VPOR, "dqword")
AVX_RRM_TEST(VPXOR, "dqword")
#define FMA_TEST(Name, P, packed) \
AVX_RRM_TEST(Name ## 132 ## P ## S, packed ? "dqword" : "dword") \
AVX_RRM_TEST(Name ## 213 ## P ## S, packed ? "dqword" : "dword") \