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Merge pull request #4680 from lioncash/ir

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IR: Minor changes
This commit is contained in:
Matthew Parlane
2017-01-18 17:31:40 +13:00
committed by GitHub
parent 1086f91ca1 bb49012445
commit 41f7995916
2 changed files with 30 additions and 40 deletions
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56
Source/Core/Core/PowerPC/JitILCommon/IR.cpp
View File

@ -121,6 +121,7 @@ TODO (in no particular order):
#endif #endif
#include <algorithm> #include <algorithm>
#include <array>
#include <cinttypes> #include <cinttypes>
#include <ctime> #include <ctime>
#include <memory> #include <memory>
@ -149,6 +150,11 @@ void IRBuilder::Reset()
MarkUsed.clear(); MarkUsed.clear();
MarkUsed.reserve(100000); MarkUsed.reserve(100000);
InvalidateCaches();
}
void IRBuilder::InvalidateCaches()
{
GRegCache = {}; GRegCache = {};
GRegCacheStore = {}; GRegCacheStore = {};
@ -1208,25 +1214,7 @@ InstLoc IRBuilder::FoldICmpCRUnsigned(InstLoc Op1, InstLoc Op2)
InstLoc IRBuilder::FoldFallBackToInterpreter(InstLoc Op1, InstLoc Op2) InstLoc IRBuilder::FoldFallBackToInterpreter(InstLoc Op1, InstLoc Op2)
{ {
for (unsigned i = 0; i < 32; i++) InvalidateCaches();
{
GRegCache[i] = nullptr;
GRegCacheStore[i] = nullptr;
FRegCache[i] = nullptr;
FRegCacheStore[i] = nullptr;
}
CarryCache = nullptr;
CarryCacheStore = nullptr;
for (unsigned i = 0; i < 8; i++)
{
CRCache[i] = nullptr;
CRCacheStore[i] = nullptr;
}
CTRCache = nullptr;
CTRCacheStore = nullptr;
return EmitBiOp(FallBackToInterpreter, Op1, Op2); return EmitBiOp(FallBackToInterpreter, Op1, Op2);
} }
@ -1371,22 +1359,22 @@ unsigned IRBuilder::getComplexity(InstLoc I) const
unsigned IRBuilder::getNumberOfOperands(InstLoc I) const unsigned IRBuilder::getNumberOfOperands(InstLoc I) const
{ {
static unsigned numberOfOperands[256]; static std::array<u32, 256> number_of_operands;
static bool initialized = false; static bool initialized = false;
if (!initialized) if (!initialized)
{ {
initialized = true; initialized = true;
std::fill_n(numberOfOperands, sizeof(numberOfOperands) / sizeof(numberOfOperands[0]), -1U);
numberOfOperands[Nop] = 0; number_of_operands.fill(0xFFFFFFFF);
numberOfOperands[CInt16] = 0; number_of_operands[Nop] = 0;
numberOfOperands[CInt32] = 0; number_of_operands[CInt16] = 0;
number_of_operands[CInt32] = 0;
static unsigned ZeroOp[] = { static constexpr std::array<u32, 12> zero_op = {
LoadCR, LoadLink, LoadMSR, LoadGReg, LoadCTR, InterpreterBranch, LoadCR, LoadLink, LoadMSR, LoadGReg, LoadCTR, InterpreterBranch,
LoadCarry, RFIExit, LoadFReg, LoadFRegDENToZero, LoadGQR, Int3, LoadCarry, RFIExit, LoadFReg, LoadFRegDENToZero, LoadGQR, Int3,
}; };
static unsigned UOp[] = { static constexpr std::array<u32, 39> unary_op = {
StoreLink, StoreLink,
BranchUncond, BranchUncond,
StoreCR, StoreCR,
@ -1427,7 +1415,7 @@ unsigned IRBuilder::getNumberOfOperands(InstLoc I) const
FastCRGTSet, FastCRGTSet,
FastCRLTSet, FastCRLTSet,
}; };
static unsigned BiOp[] = { static constexpr std::array<u32, 44> binary_op = {
BranchCond, BranchCond,
IdleBranch, IdleBranch,
And, And,
@ -1473,17 +1461,17 @@ unsigned IRBuilder::getNumberOfOperands(InstLoc I) const
FPMerge11, FPMerge11,
FDCmpCR, FDCmpCR,
}; };
for (auto& op : ZeroOp) for (auto op : zero_op)
numberOfOperands[op] = 0; number_of_operands[op] = 0;
for (auto& op : UOp) for (auto op : unary_op)
numberOfOperands[op] = 1; number_of_operands[op] = 1;
for (auto& op : BiOp) for (auto op : binary_op)
numberOfOperands[op] = 2; number_of_operands[op] = 2;
} }
return numberOfOperands[getOpcode(*I)]; return number_of_operands[getOpcode(*I)];
} }
// Performs a few simplifications for commutative operators // Performs a few simplifications for commutative operators

14
Source/Core/Core/PowerPC/JitILCommon/IR.h
View File

@ -182,25 +182,25 @@ enum Opcode
Int3 Int3
}; };
typedef unsigned Inst; using Inst = u32;
typedef Inst* InstLoc; using InstLoc = Inst*;
unsigned inline getOpcode(Inst i) constexpr u32 getOpcode(Inst i)
{ {
return i & 255; return i & 255;
} }
unsigned inline isImm(Inst i) constexpr bool isImm(Inst i)
{ {
return getOpcode(i) >= CInt16 && getOpcode(i) <= CInt32; return getOpcode(i) >= CInt16 && getOpcode(i) <= CInt32;
} }
unsigned inline isICmp(Inst i) constexpr bool isICmp(Inst i)
{ {
return getOpcode(i) >= ICmpEq && getOpcode(i) <= ICmpSle; return getOpcode(i) >= ICmpEq && getOpcode(i) <= ICmpSle;
} }
unsigned inline isFResult(Inst i) constexpr bool isFResult(Inst i)
{ {
return getOpcode(i) > FResult_Start && getOpcode(i) < FResult_End; return getOpcode(i) > FResult_Start && getOpcode(i) < FResult_End;
} }
@ -388,6 +388,8 @@ public:
void WriteToFile(u64 codeHash); void WriteToFile(u64 codeHash);
private: private:
void InvalidateCaches();
InstLoc EmitZeroOp(unsigned Opcode, unsigned extra); InstLoc EmitZeroOp(unsigned Opcode, unsigned extra);
InstLoc EmitUOp(unsigned OpCode, InstLoc Op1, unsigned extra = 0); InstLoc EmitUOp(unsigned OpCode, InstLoc Op1, unsigned extra = 0);
InstLoc EmitBiOp(unsigned OpCode, InstLoc Op1, InstLoc Op2, unsigned extra = 0); InstLoc EmitBiOp(unsigned OpCode, InstLoc Op1, InstLoc Op2, unsigned extra = 0);