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X64Emitter: add unit test for FMA
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@ -948,4 +948,47 @@ VEX_RM_TEST(BLSI)
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VEX_RMI_TEST(RORX)
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VEX_RMI_TEST(RORX)
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// for AVX instructions that take the form op reg, reg, r/m
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#define AVX_RRM_TEST(Name, sizename) \
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TEST_F(x64EmitterTest, Name) \
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{ \
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struct { \
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int bits; \
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std::vector<NamedReg> regs; \
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std::string out_name; \
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std::string size; \
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} regsets[] = { \
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{ 64, xmmnames, "xmm0", sizename }, \
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}; \
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for (const auto& regset : regsets) \
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for (const auto& r : regset.regs) \
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{ \
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emitter->Name(r.reg, RAX, R(RAX)); \
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emitter->Name(RAX, RAX, R(r.reg)); \
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emitter->Name(RAX, r.reg, MatR(R12)); \
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ExpectDisassembly(#Name " " + r.name+ ", " + regset.out_name + ", " + regset.out_name + " " \
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#Name " " + regset.out_name + ", " + regset.out_name + ", " + r.name + " " \
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#Name " " + regset.out_name + ", " + r.name + ", " + regset.size + " ptr ds:[r12] "); \
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} \
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}
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#define FMA_TEST(Name, P, packed) \
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AVX_RRM_TEST(Name ## 132 ## P ## S, packed ? "dqword" : "dword") \
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AVX_RRM_TEST(Name ## 213 ## P ## S, packed ? "dqword" : "dword") \
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AVX_RRM_TEST(Name ## 231 ## P ## S, packed ? "dqword" : "dword") \
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AVX_RRM_TEST(Name ## 132 ## P ## D, packed ? "dqword" : "qword") \
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AVX_RRM_TEST(Name ## 213 ## P ## D, packed ? "dqword" : "qword") \
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AVX_RRM_TEST(Name ## 231 ## P ## D, packed ? "dqword" : "qword")
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FMA_TEST(VFMADD, P, true)
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FMA_TEST(VFMADD, S, false)
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FMA_TEST(VFMSUB, P, true)
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FMA_TEST(VFMSUB, S, false)
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FMA_TEST(VFNMADD, P, true)
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FMA_TEST(VFNMADD, S, false)
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FMA_TEST(VFNMSUB, P, true)
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FMA_TEST(VFNMSUB, S, false)
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FMA_TEST(VFMADDSUB, P, true)
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FMA_TEST(VFMSUBADD, P, true)
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} // namespace Gen
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} // namespace Gen
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