From 78b36921d2087c913e298dab3d8f8c0ed6abec76 Mon Sep 17 00:00:00 2001 From: degasus Date: Sun, 22 Jan 2017 09:00:43 +0100 Subject: [PATCH 1/3] Jit64: Use a temporary register for memory references. Part 1. --- Source/Core/Core/HW/CPU.cpp | 2 +- Source/Core/Core/HW/CPU.h | 2 +- Source/Core/Core/PowerPC/Jit64/Jit.cpp | 6 ++++-- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/Source/Core/Core/HW/CPU.cpp b/Source/Core/Core/HW/CPU.cpp index a57e1cb1a1..14a8249829 100644 --- a/Source/Core/Core/HW/CPU.cpp +++ b/Source/Core/Core/HW/CPU.cpp @@ -183,7 +183,7 @@ State GetState() return s_state; } -const volatile State* GetStatePtr() +const State* GetStatePtr() { return &s_state; } diff --git a/Source/Core/Core/HW/CPU.h b/Source/Core/Core/HW/CPU.h index 280db7f500..5337483e3e 100644 --- a/Source/Core/Core/HW/CPU.h +++ b/Source/Core/Core/HW/CPU.h @@ -57,7 +57,7 @@ State GetState(); // Direct State Access (Raw pointer for embedding into JIT Blocks) // Strictly read-only. A lock is required to change the value. -const volatile State* GetStatePtr(); +const State* GetStatePtr(); // Locks the CPU Thread (waiting for it to become idle). // While this lock is held, the CPU Thread will not perform any action so it is safe to access diff --git a/Source/Core/Core/PowerPC/Jit64/Jit.cpp b/Source/Core/Core/PowerPC/Jit64/Jit.cpp index e157994416..05a235a731 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit.cpp @@ -780,7 +780,8 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer* code_buf, JitBloc SetJumpTarget(extException); TEST(32, PPCSTATE(msr), Imm32(0x0008000)); FixupBranch noExtIntEnable = J_CC(CC_Z, true); - TEST(32, M(&ProcessorInterface::m_InterruptCause), + MOV(64, R(RSCRATCH), ImmPtr(&ProcessorInterface::m_InterruptCause)); + TEST(32, MatR(RSCRATCH), Imm32(ProcessorInterface::INT_CAUSE_CP | ProcessorInterface::INT_CAUSE_PE_TOKEN | ProcessorInterface::INT_CAUSE_PE_FINISH)); FixupBranch noCPInt = J_CC(CC_Z, true); @@ -854,7 +855,8 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer* code_buf, JitBloc ABI_PushRegistersAndAdjustStack({}, 0); ABI_CallFunction(PowerPC::CheckBreakPoints); ABI_PopRegistersAndAdjustStack({}, 0); - TEST(32, M(CPU::GetStatePtr()), Imm32(0xFFFFFFFF)); + MOV(64, R(RSCRATCH), ImmPtr(CPU::GetStatePtr())); + TEST(32, MatR(RSCRATCH), Imm32(0xFFFFFFFF)); FixupBranch noBreakpoint = J_CC(CC_Z); WriteExit(ops[i].address); From 0ddd90b539ff144a2b19528f4d3c9c372b35b28b Mon Sep 17 00:00:00 2001 From: degasus Date: Sun, 22 Jan 2017 09:29:43 +0100 Subject: [PATCH 2/3] Jit64: Use a temporary register for memory references. Part 3. --- Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp index 6588763f63..5b68fae157 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp @@ -410,7 +410,8 @@ void Jit64::mtmsr(UGeckoInstruction inst) FixupBranch noExceptionsPending = J_CC(CC_Z); // Check if a CP interrupt is waiting and keep the GPU emulation in sync (issue 4336) - TEST(32, M(&ProcessorInterface::m_InterruptCause), Imm32(ProcessorInterface::INT_CAUSE_CP)); + MOV(64, R(RSCRATCH), ImmPtr(&ProcessorInterface::m_InterruptCause)); + TEST(32, MatR(RSCRATCH), Imm32(ProcessorInterface::INT_CAUSE_CP)); FixupBranch cpInt = J_CC(CC_NZ); MOV(32, PPCSTATE(pc), Imm32(js.compilerPC + 4)); From 64ccf803bd2a8da0ae4194004b91275fec110b16 Mon Sep 17 00:00:00 2001 From: degasus Date: Sun, 22 Jan 2017 09:37:22 +0100 Subject: [PATCH 3/3] Jit64: Use a temporary register for memory references. Part 4. --- Source/Core/Core/PowerPC/Jit64/JitAsm.cpp | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Source/Core/Core/PowerPC/Jit64/JitAsm.cpp b/Source/Core/Core/PowerPC/Jit64/JitAsm.cpp index cc47c1d695..f96495cfa1 100644 --- a/Source/Core/Core/PowerPC/Jit64/JitAsm.cpp +++ b/Source/Core/Core/PowerPC/Jit64/JitAsm.cpp @@ -84,12 +84,14 @@ void Jit64AsmRoutineManager::Generate() if (SConfig::GetInstance().bEnableDebugging) { - TEST(32, M(CPU::GetStatePtr()), Imm32(static_cast(CPU::State::Stepping))); + MOV(64, R(RSCRATCH), ImmPtr(CPU::GetStatePtr())); + TEST(32, MatR(RSCRATCH), Imm32(static_cast(CPU::State::Stepping))); FixupBranch notStepping = J_CC(CC_Z); ABI_PushRegistersAndAdjustStack({}, 0); ABI_CallFunction(PowerPC::CheckBreakPoints); ABI_PopRegistersAndAdjustStack({}, 0); - TEST(32, M(CPU::GetStatePtr()), Imm32(0xFFFFFFFF)); + MOV(64, R(RSCRATCH), ImmPtr(CPU::GetStatePtr())); + TEST(32, MatR(RSCRATCH), Imm32(0xFFFFFFFF)); dbg_exit = J_CC(CC_NZ, true); SetJumpTarget(notStepping); } @@ -187,7 +189,8 @@ void Jit64AsmRoutineManager::Generate() // Check the state pointer to see if we are exiting // Gets checked on at the end of every slice - TEST(32, M(CPU::GetStatePtr()), Imm32(0xFFFFFFFF)); + MOV(64, R(RSCRATCH), ImmPtr(CPU::GetStatePtr())); + TEST(32, MatR(RSCRATCH), Imm32(0xFFFFFFFF)); J_CC(CC_Z, outerLoop); // Landing pad for drec space