mirror of
https://github.com/dolphin-emu/dolphin.git
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Hg:
enable newline normalization get revision number via `hg svn info` for svnrev.h ignore incremental/generated binary files (windows/VS at least) leave a comment if some files need native eol set in svnprops git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@5637 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
Shawn Hoffman
@ -1,20 +1,20 @@
|
||||
|
||||
Microsoft Visual Studio Solution File, Format Version 10.00
|
||||
# Visual Studio 2008
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "DSP_InterC", "DSP_InterC\DSP_InterC.vcproj", "{A010425E-9D5E-461E-910D-0804C2A944D5}"
|
||||
EndProject
|
||||
Global
|
||||
GlobalSection(SolutionConfigurationPlatforms) = preSolution
|
||||
Debug|Win32 = Debug|Win32
|
||||
Release|Win32 = Release|Win32
|
||||
EndGlobalSection
|
||||
GlobalSection(ProjectConfigurationPlatforms) = postSolution
|
||||
{A010425E-9D5E-461E-910D-0804C2A944D5}.Debug|Win32.ActiveCfg = Debug|Win32
|
||||
{A010425E-9D5E-461E-910D-0804C2A944D5}.Debug|Win32.Build.0 = Debug|Win32
|
||||
{A010425E-9D5E-461E-910D-0804C2A944D5}.Release|Win32.ActiveCfg = Release|Win32
|
||||
{A010425E-9D5E-461E-910D-0804C2A944D5}.Release|Win32.Build.0 = Release|Win32
|
||||
EndGlobalSection
|
||||
GlobalSection(SolutionProperties) = preSolution
|
||||
HideSolutionNode = FALSE
|
||||
EndGlobalSection
|
||||
EndGlobal
|
||||
|
||||
Microsoft Visual Studio Solution File, Format Version 10.00
|
||||
# Visual Studio 2008
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "DSP_InterC", "DSP_InterC\DSP_InterC.vcproj", "{A010425E-9D5E-461E-910D-0804C2A944D5}"
|
||||
EndProject
|
||||
Global
|
||||
GlobalSection(SolutionConfigurationPlatforms) = preSolution
|
||||
Debug|Win32 = Debug|Win32
|
||||
Release|Win32 = Release|Win32
|
||||
EndGlobalSection
|
||||
GlobalSection(ProjectConfigurationPlatforms) = postSolution
|
||||
{A010425E-9D5E-461E-910D-0804C2A944D5}.Debug|Win32.ActiveCfg = Debug|Win32
|
||||
{A010425E-9D5E-461E-910D-0804C2A944D5}.Debug|Win32.Build.0 = Debug|Win32
|
||||
{A010425E-9D5E-461E-910D-0804C2A944D5}.Release|Win32.ActiveCfg = Release|Win32
|
||||
{A010425E-9D5E-461E-910D-0804C2A944D5}.Release|Win32.Build.0 = Release|Win32
|
||||
EndGlobalSection
|
||||
GlobalSection(SolutionProperties) = preSolution
|
||||
HideSolutionNode = FALSE
|
||||
EndGlobalSection
|
||||
EndGlobal
|
||||
|
||||
@ -1,320 +1,320 @@
|
||||
/*====================================================================
|
||||
|
||||
filename: opcodes.h
|
||||
project: GameCube DSP Tool (gcdsp)
|
||||
created: 2005.03.04
|
||||
mail: duddie@walla.com
|
||||
|
||||
Copyright (c) 2005 Duddie
|
||||
|
||||
This program is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU General Public License
|
||||
as published by the Free Software Foundation; either version 2
|
||||
of the License, or (at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
====================================================================*/
|
||||
//
|
||||
//
|
||||
// At the moment just ls and sl are using the prolog
|
||||
// perhaps all actions on r03 must be in the prolog
|
||||
//
|
||||
#include <stdafx.h>
|
||||
|
||||
#include "OutBuffer.h"
|
||||
|
||||
|
||||
|
||||
//
|
||||
void dsp_op_ext_r_epi(uint16 _Opcode)
|
||||
{
|
||||
uint8 op = (_Opcode >> 2) & 0x3;
|
||||
uint8 reg = _Opcode & 0x3;
|
||||
|
||||
switch (op)
|
||||
{
|
||||
case 0x00:
|
||||
OutBuffer::AddCode("Error: dsp_op_ext_r_epi");
|
||||
break;
|
||||
|
||||
case 0x01:
|
||||
OutBuffer::AddCode("%s--", OutBuffer::GetRegName(reg));
|
||||
// g_dsp.r[reg]--;
|
||||
break;
|
||||
|
||||
case 0x02:
|
||||
OutBuffer::AddCode("%s++", OutBuffer::GetRegName(reg));
|
||||
//g_dsp.r[reg]++;
|
||||
break;
|
||||
|
||||
case 0x03:
|
||||
OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(reg), OutBuffer::GetRegName(reg+4));
|
||||
// g_dsp.r[reg] += g_dsp.r[reg + 4];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_mv(uint16 _Opcode)
|
||||
{
|
||||
uint8 sreg = _Opcode & 0x3;
|
||||
uint8 dreg = ((_Opcode >> 2) & 0x3);
|
||||
|
||||
OutBuffer::AddCode("%s = %s", OutBuffer::GetRegName(dreg + 0x18), OutBuffer::GetRegName(sreg + 0x1c));
|
||||
|
||||
// g_dsp.r[dreg + 0x18] = g_dsp.r[sreg + 0x1c];
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_s(uint16 _Opcode)
|
||||
{
|
||||
uint8 dreg = _Opcode & 0x3;
|
||||
uint8 sreg = ((_Opcode >> 3) & 0x3) + 0x1c;
|
||||
|
||||
OutBuffer::AddCode("WriteDMEM(%s, %s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(sreg));
|
||||
// dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
|
||||
|
||||
if (_Opcode & 0x04)
|
||||
{
|
||||
OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(dreg+4));
|
||||
// g_dsp.r[dreg] += g_dsp.r[dreg + 4];
|
||||
}
|
||||
else
|
||||
{
|
||||
OutBuffer::AddCode("%s++", OutBuffer::GetRegName(dreg));
|
||||
//g_dsp.r[dreg]++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_l(uint16 _Opcode)
|
||||
{
|
||||
uint8 sreg = _Opcode & 0x3;
|
||||
uint8 dreg = ((_Opcode >> 3) & 0x7) + 0x18;
|
||||
|
||||
OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(sreg));
|
||||
// uint16 val = dsp_dmem_read(g_dsp.r[sreg]);
|
||||
// g_dsp.r[dreg] = val;
|
||||
|
||||
if (_Opcode & 0x04)
|
||||
{
|
||||
OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(sreg), OutBuffer::GetRegName(sreg+4));
|
||||
// g_dsp.r[sreg] += g_dsp.r[sreg + 4];
|
||||
}
|
||||
else
|
||||
{
|
||||
OutBuffer::AddCode("%s++", OutBuffer::GetRegName(sreg));
|
||||
// g_dsp.r[sreg]++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_ls_pro(uint16 _Opcode)
|
||||
{
|
||||
uint8 areg = (_Opcode & 0x1) + 0x1e;
|
||||
|
||||
OutBuffer::AddCode("WriteDMEM(%s, %s)", OutBuffer::GetRegName(0x03), OutBuffer::GetRegName(areg));
|
||||
// dsp_dmem_write(g_dsp.r[0x03], g_dsp.r[areg]);
|
||||
|
||||
if (_Opcode & 0x8)
|
||||
{
|
||||
OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(0x03), OutBuffer::GetRegName(0x07));
|
||||
// g_dsp.r[0x03] += g_dsp.r[0x07];
|
||||
}
|
||||
else
|
||||
{
|
||||
OutBuffer::AddCode("%s++", OutBuffer::GetRegName(0x03));
|
||||
// g_dsp.r[0x03]++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_ls_epi(uint16 _Opcode)
|
||||
{
|
||||
uint8 dreg = ((_Opcode >> 4) & 0x3) + 0x18;
|
||||
|
||||
OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(0x00));
|
||||
// uint16 val = dsp_dmem_read(g_dsp.r[0x00]);
|
||||
// dsp_op_write_reg(dreg, val);
|
||||
|
||||
if (_Opcode & 0x4)
|
||||
{
|
||||
OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(0x00), OutBuffer::GetRegName(0x04));
|
||||
// g_dsp.r[0x00] += g_dsp.r[0x04];
|
||||
}
|
||||
else
|
||||
{
|
||||
OutBuffer::AddCode("%s++", OutBuffer::GetRegName(0x00));
|
||||
// g_dsp.r[0x00]++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_sl_pro(uint16 _Opcode)
|
||||
{
|
||||
uint8 areg = (_Opcode & 0x1) + 0x1e;
|
||||
|
||||
OutBuffer::AddCode("WriteDMEM(%s, %s)", OutBuffer::GetRegName(0x00), OutBuffer::GetRegName(areg));
|
||||
// dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]);
|
||||
|
||||
if (_Opcode & 0x4)
|
||||
{
|
||||
OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(0x00), OutBuffer::GetRegName(0x04));
|
||||
// g_dsp.r[0x00] += g_dsp.r[0x04];
|
||||
}
|
||||
else
|
||||
{
|
||||
OutBuffer::AddCode("%s++", OutBuffer::GetRegName(0x00));
|
||||
// g_dsp.r[0x00]++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_sl_epi(uint16 _Opcode)
|
||||
{
|
||||
uint8 dreg = ((_Opcode >> 4) & 0x3) + 0x18;
|
||||
|
||||
OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(0x03));
|
||||
// uint16 val = dsp_dmem_read(g_dsp.r[0x03]);
|
||||
// dsp_op_write_reg(dreg, val);
|
||||
|
||||
if (_Opcode & 0x8)
|
||||
{
|
||||
OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(0x03), OutBuffer::GetRegName(0x07));
|
||||
// g_dsp.r[0x03] += g_dsp.r[0x07];
|
||||
}
|
||||
else
|
||||
{
|
||||
OutBuffer::AddCode("%s++", OutBuffer::GetRegName(0x03));
|
||||
// g_dsp.r[0x03]++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_ld(uint16 _Opcode)
|
||||
{
|
||||
uint8 dreg1 = (((_Opcode >> 5) & 0x1) << 1) + 0x18;
|
||||
uint8 dreg2 = (((_Opcode >> 4) & 0x1) << 1) + 0x19;
|
||||
uint8 sreg = _Opcode & 0x3;
|
||||
|
||||
OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg1), OutBuffer::GetRegName(sreg));
|
||||
OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg2), OutBuffer::GetRegName(0x03));
|
||||
|
||||
// g_dsp.r[dreg1] = dsp_dmem_read(g_dsp.r[sreg]);
|
||||
// g_dsp.r[dreg2] = dsp_dmem_read(g_dsp.r[0x03]);
|
||||
|
||||
if (_Opcode & 0x04)
|
||||
{
|
||||
OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(sreg), OutBuffer::GetRegName(sreg + 0x04));
|
||||
// g_dsp.r[sreg] += g_dsp.r[sreg + 0x04];
|
||||
}
|
||||
else
|
||||
{
|
||||
OutBuffer::AddCode("%s++", OutBuffer::GetRegName(sreg));
|
||||
// g_dsp.r[sreg]++;
|
||||
}
|
||||
|
||||
if (_Opcode & 0x08)
|
||||
{
|
||||
OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(0x03), OutBuffer::GetRegName(sreg + 0x07));
|
||||
// g_dsp.r[0x03] += g_dsp.r[0x07];
|
||||
}
|
||||
else
|
||||
{
|
||||
OutBuffer::AddCode("%s++", OutBuffer::GetRegName(0x03));
|
||||
// g_dsp.r[0x03]++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// ================================================================================
|
||||
//
|
||||
//
|
||||
//
|
||||
// ================================================================================
|
||||
|
||||
void dsp_op_ext_ops_pro(uint16 _Opcode)
|
||||
{
|
||||
if ((_Opcode & 0xFF) == 0){return;}
|
||||
|
||||
switch ((_Opcode >> 4) & 0xf)
|
||||
{
|
||||
case 0x00:
|
||||
dsp_op_ext_r_epi(_Opcode);
|
||||
break;
|
||||
|
||||
case 0x01:
|
||||
dsp_op_ext_mv(_Opcode);
|
||||
break;
|
||||
|
||||
case 0x02:
|
||||
case 0x03:
|
||||
dsp_op_ext_s(_Opcode);
|
||||
break;
|
||||
|
||||
case 0x04:
|
||||
case 0x05:
|
||||
case 0x06:
|
||||
case 0x07:
|
||||
dsp_op_ext_l(_Opcode);
|
||||
break;
|
||||
|
||||
case 0x08:
|
||||
case 0x09:
|
||||
case 0x0a:
|
||||
case 0x0b:
|
||||
|
||||
if (_Opcode & 0x2)
|
||||
{
|
||||
dsp_op_ext_sl_pro(_Opcode);
|
||||
}
|
||||
else
|
||||
{
|
||||
dsp_op_ext_ls_pro(_Opcode);
|
||||
}
|
||||
|
||||
return;
|
||||
|
||||
case 0x0c:
|
||||
case 0x0d:
|
||||
case 0x0e:
|
||||
case 0x0f:
|
||||
dsp_op_ext_ld(_Opcode);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_ops_epi(uint16 _Opcode)
|
||||
{
|
||||
if ((_Opcode & 0xFF) == 0){return;}
|
||||
|
||||
switch ((_Opcode >> 4) & 0xf)
|
||||
{
|
||||
case 0x08:
|
||||
case 0x09:
|
||||
case 0x0a:
|
||||
case 0x0b:
|
||||
|
||||
if (_Opcode & 0x2)
|
||||
{
|
||||
dsp_op_ext_sl_epi(_Opcode);
|
||||
}
|
||||
else
|
||||
{
|
||||
dsp_op_ext_ls_epi(_Opcode);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*====================================================================
|
||||
|
||||
filename: opcodes.h
|
||||
project: GameCube DSP Tool (gcdsp)
|
||||
created: 2005.03.04
|
||||
mail: duddie@walla.com
|
||||
|
||||
Copyright (c) 2005 Duddie
|
||||
|
||||
This program is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU General Public License
|
||||
as published by the Free Software Foundation; either version 2
|
||||
of the License, or (at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
====================================================================*/
|
||||
//
|
||||
//
|
||||
// At the moment just ls and sl are using the prolog
|
||||
// perhaps all actions on r03 must be in the prolog
|
||||
//
|
||||
#include <stdafx.h>
|
||||
|
||||
#include "OutBuffer.h"
|
||||
|
||||
|
||||
|
||||
//
|
||||
void dsp_op_ext_r_epi(uint16 _Opcode)
|
||||
{
|
||||
uint8 op = (_Opcode >> 2) & 0x3;
|
||||
uint8 reg = _Opcode & 0x3;
|
||||
|
||||
switch (op)
|
||||
{
|
||||
case 0x00:
|
||||
OutBuffer::AddCode("Error: dsp_op_ext_r_epi");
|
||||
break;
|
||||
|
||||
case 0x01:
|
||||
OutBuffer::AddCode("%s--", OutBuffer::GetRegName(reg));
|
||||
// g_dsp.r[reg]--;
|
||||
break;
|
||||
|
||||
case 0x02:
|
||||
OutBuffer::AddCode("%s++", OutBuffer::GetRegName(reg));
|
||||
//g_dsp.r[reg]++;
|
||||
break;
|
||||
|
||||
case 0x03:
|
||||
OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(reg), OutBuffer::GetRegName(reg+4));
|
||||
// g_dsp.r[reg] += g_dsp.r[reg + 4];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_mv(uint16 _Opcode)
|
||||
{
|
||||
uint8 sreg = _Opcode & 0x3;
|
||||
uint8 dreg = ((_Opcode >> 2) & 0x3);
|
||||
|
||||
OutBuffer::AddCode("%s = %s", OutBuffer::GetRegName(dreg + 0x18), OutBuffer::GetRegName(sreg + 0x1c));
|
||||
|
||||
// g_dsp.r[dreg + 0x18] = g_dsp.r[sreg + 0x1c];
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_s(uint16 _Opcode)
|
||||
{
|
||||
uint8 dreg = _Opcode & 0x3;
|
||||
uint8 sreg = ((_Opcode >> 3) & 0x3) + 0x1c;
|
||||
|
||||
OutBuffer::AddCode("WriteDMEM(%s, %s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(sreg));
|
||||
// dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
|
||||
|
||||
if (_Opcode & 0x04)
|
||||
{
|
||||
OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(dreg+4));
|
||||
// g_dsp.r[dreg] += g_dsp.r[dreg + 4];
|
||||
}
|
||||
else
|
||||
{
|
||||
OutBuffer::AddCode("%s++", OutBuffer::GetRegName(dreg));
|
||||
//g_dsp.r[dreg]++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_l(uint16 _Opcode)
|
||||
{
|
||||
uint8 sreg = _Opcode & 0x3;
|
||||
uint8 dreg = ((_Opcode >> 3) & 0x7) + 0x18;
|
||||
|
||||
OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(sreg));
|
||||
// uint16 val = dsp_dmem_read(g_dsp.r[sreg]);
|
||||
// g_dsp.r[dreg] = val;
|
||||
|
||||
if (_Opcode & 0x04)
|
||||
{
|
||||
OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(sreg), OutBuffer::GetRegName(sreg+4));
|
||||
// g_dsp.r[sreg] += g_dsp.r[sreg + 4];
|
||||
}
|
||||
else
|
||||
{
|
||||
OutBuffer::AddCode("%s++", OutBuffer::GetRegName(sreg));
|
||||
// g_dsp.r[sreg]++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_ls_pro(uint16 _Opcode)
|
||||
{
|
||||
uint8 areg = (_Opcode & 0x1) + 0x1e;
|
||||
|
||||
OutBuffer::AddCode("WriteDMEM(%s, %s)", OutBuffer::GetRegName(0x03), OutBuffer::GetRegName(areg));
|
||||
// dsp_dmem_write(g_dsp.r[0x03], g_dsp.r[areg]);
|
||||
|
||||
if (_Opcode & 0x8)
|
||||
{
|
||||
OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(0x03), OutBuffer::GetRegName(0x07));
|
||||
// g_dsp.r[0x03] += g_dsp.r[0x07];
|
||||
}
|
||||
else
|
||||
{
|
||||
OutBuffer::AddCode("%s++", OutBuffer::GetRegName(0x03));
|
||||
// g_dsp.r[0x03]++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_ls_epi(uint16 _Opcode)
|
||||
{
|
||||
uint8 dreg = ((_Opcode >> 4) & 0x3) + 0x18;
|
||||
|
||||
OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(0x00));
|
||||
// uint16 val = dsp_dmem_read(g_dsp.r[0x00]);
|
||||
// dsp_op_write_reg(dreg, val);
|
||||
|
||||
if (_Opcode & 0x4)
|
||||
{
|
||||
OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(0x00), OutBuffer::GetRegName(0x04));
|
||||
// g_dsp.r[0x00] += g_dsp.r[0x04];
|
||||
}
|
||||
else
|
||||
{
|
||||
OutBuffer::AddCode("%s++", OutBuffer::GetRegName(0x00));
|
||||
// g_dsp.r[0x00]++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_sl_pro(uint16 _Opcode)
|
||||
{
|
||||
uint8 areg = (_Opcode & 0x1) + 0x1e;
|
||||
|
||||
OutBuffer::AddCode("WriteDMEM(%s, %s)", OutBuffer::GetRegName(0x00), OutBuffer::GetRegName(areg));
|
||||
// dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]);
|
||||
|
||||
if (_Opcode & 0x4)
|
||||
{
|
||||
OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(0x00), OutBuffer::GetRegName(0x04));
|
||||
// g_dsp.r[0x00] += g_dsp.r[0x04];
|
||||
}
|
||||
else
|
||||
{
|
||||
OutBuffer::AddCode("%s++", OutBuffer::GetRegName(0x00));
|
||||
// g_dsp.r[0x00]++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_sl_epi(uint16 _Opcode)
|
||||
{
|
||||
uint8 dreg = ((_Opcode >> 4) & 0x3) + 0x18;
|
||||
|
||||
OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(0x03));
|
||||
// uint16 val = dsp_dmem_read(g_dsp.r[0x03]);
|
||||
// dsp_op_write_reg(dreg, val);
|
||||
|
||||
if (_Opcode & 0x8)
|
||||
{
|
||||
OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(0x03), OutBuffer::GetRegName(0x07));
|
||||
// g_dsp.r[0x03] += g_dsp.r[0x07];
|
||||
}
|
||||
else
|
||||
{
|
||||
OutBuffer::AddCode("%s++", OutBuffer::GetRegName(0x03));
|
||||
// g_dsp.r[0x03]++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_ld(uint16 _Opcode)
|
||||
{
|
||||
uint8 dreg1 = (((_Opcode >> 5) & 0x1) << 1) + 0x18;
|
||||
uint8 dreg2 = (((_Opcode >> 4) & 0x1) << 1) + 0x19;
|
||||
uint8 sreg = _Opcode & 0x3;
|
||||
|
||||
OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg1), OutBuffer::GetRegName(sreg));
|
||||
OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg2), OutBuffer::GetRegName(0x03));
|
||||
|
||||
// g_dsp.r[dreg1] = dsp_dmem_read(g_dsp.r[sreg]);
|
||||
// g_dsp.r[dreg2] = dsp_dmem_read(g_dsp.r[0x03]);
|
||||
|
||||
if (_Opcode & 0x04)
|
||||
{
|
||||
OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(sreg), OutBuffer::GetRegName(sreg + 0x04));
|
||||
// g_dsp.r[sreg] += g_dsp.r[sreg + 0x04];
|
||||
}
|
||||
else
|
||||
{
|
||||
OutBuffer::AddCode("%s++", OutBuffer::GetRegName(sreg));
|
||||
// g_dsp.r[sreg]++;
|
||||
}
|
||||
|
||||
if (_Opcode & 0x08)
|
||||
{
|
||||
OutBuffer::AddCode("%s += %s", OutBuffer::GetRegName(0x03), OutBuffer::GetRegName(sreg + 0x07));
|
||||
// g_dsp.r[0x03] += g_dsp.r[0x07];
|
||||
}
|
||||
else
|
||||
{
|
||||
OutBuffer::AddCode("%s++", OutBuffer::GetRegName(0x03));
|
||||
// g_dsp.r[0x03]++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// ================================================================================
|
||||
//
|
||||
//
|
||||
//
|
||||
// ================================================================================
|
||||
|
||||
void dsp_op_ext_ops_pro(uint16 _Opcode)
|
||||
{
|
||||
if ((_Opcode & 0xFF) == 0){return;}
|
||||
|
||||
switch ((_Opcode >> 4) & 0xf)
|
||||
{
|
||||
case 0x00:
|
||||
dsp_op_ext_r_epi(_Opcode);
|
||||
break;
|
||||
|
||||
case 0x01:
|
||||
dsp_op_ext_mv(_Opcode);
|
||||
break;
|
||||
|
||||
case 0x02:
|
||||
case 0x03:
|
||||
dsp_op_ext_s(_Opcode);
|
||||
break;
|
||||
|
||||
case 0x04:
|
||||
case 0x05:
|
||||
case 0x06:
|
||||
case 0x07:
|
||||
dsp_op_ext_l(_Opcode);
|
||||
break;
|
||||
|
||||
case 0x08:
|
||||
case 0x09:
|
||||
case 0x0a:
|
||||
case 0x0b:
|
||||
|
||||
if (_Opcode & 0x2)
|
||||
{
|
||||
dsp_op_ext_sl_pro(_Opcode);
|
||||
}
|
||||
else
|
||||
{
|
||||
dsp_op_ext_ls_pro(_Opcode);
|
||||
}
|
||||
|
||||
return;
|
||||
|
||||
case 0x0c:
|
||||
case 0x0d:
|
||||
case 0x0e:
|
||||
case 0x0f:
|
||||
dsp_op_ext_ld(_Opcode);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_ops_epi(uint16 _Opcode)
|
||||
{
|
||||
if ((_Opcode & 0xFF) == 0){return;}
|
||||
|
||||
switch ((_Opcode >> 4) & 0xf)
|
||||
{
|
||||
case 0x08:
|
||||
case 0x09:
|
||||
case 0x0a:
|
||||
case 0x0b:
|
||||
|
||||
if (_Opcode & 0x2)
|
||||
{
|
||||
dsp_op_ext_sl_epi(_Opcode);
|
||||
}
|
||||
else
|
||||
{
|
||||
dsp_op_ext_ls_epi(_Opcode);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -1,33 +1,33 @@
|
||||
/*====================================================================
|
||||
|
||||
filename: opcodes.h
|
||||
project: GameCube DSP Tool (gcdsp)
|
||||
created: 2005.03.04
|
||||
mail: duddie@walla.com
|
||||
|
||||
Copyright (c) 2005 Duddie
|
||||
|
||||
This program is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU General Public License
|
||||
as published by the Free Software Foundation; either version 2
|
||||
of the License, or (at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
====================================================================*/
|
||||
|
||||
#ifndef _GDSP_EXT_OP_H
|
||||
#define _GDSP_EXT_OP_H
|
||||
|
||||
void dsp_op_ext_ops_pro(uint16 _Opcode);
|
||||
void dsp_op_ext_ops_epi(uint16 _Opcode);
|
||||
|
||||
|
||||
#endif
|
||||
/*====================================================================
|
||||
|
||||
filename: opcodes.h
|
||||
project: GameCube DSP Tool (gcdsp)
|
||||
created: 2005.03.04
|
||||
mail: duddie@walla.com
|
||||
|
||||
Copyright (c) 2005 Duddie
|
||||
|
||||
This program is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU General Public License
|
||||
as published by the Free Software Foundation; either version 2
|
||||
of the License, or (at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
====================================================================*/
|
||||
|
||||
#ifndef _GDSP_EXT_OP_H
|
||||
#define _GDSP_EXT_OP_H
|
||||
|
||||
void dsp_op_ext_ops_pro(uint16 _Opcode);
|
||||
void dsp_op_ext_ops_epi(uint16 _Opcode);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,48 +1,48 @@
|
||||
/*====================================================================
|
||||
|
||||
filename: gdsp_opcodes.h
|
||||
project: GCemu
|
||||
created: 2004-6-18
|
||||
mail: duddie@walla.com
|
||||
|
||||
Copyright (c) 2005 Duddie & Tratax
|
||||
|
||||
This program is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU General Public License
|
||||
as published by the Free Software Foundation; either version 2
|
||||
of the License, or (at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
====================================================================*/
|
||||
#ifndef _GDSP_OPCODES_H
|
||||
#define _GDSP_OPCODES_H
|
||||
|
||||
void dsp_op0(uint16 opc);
|
||||
void dsp_op1(uint16 opc);
|
||||
void dsp_op2(uint16 opc);
|
||||
void dsp_op3(uint16 opc);
|
||||
void dsp_op4(uint16 opc);
|
||||
void dsp_op5(uint16 opc);
|
||||
void dsp_op6(uint16 opc);
|
||||
void dsp_op7(uint16 opc);
|
||||
void dsp_op8(uint16 opc);
|
||||
void dsp_op9(uint16 opc);
|
||||
void dsp_opab(uint16 opc);
|
||||
void dsp_opcd(uint16 opc);
|
||||
void dsp_ope(uint16 opc);
|
||||
void dsp_opf(uint16 opc);
|
||||
|
||||
|
||||
#define R_SR 0x13
|
||||
|
||||
#define FLAG_ENABLE_INTERUPT 11
|
||||
|
||||
#endif
|
||||
/*====================================================================
|
||||
|
||||
filename: gdsp_opcodes.h
|
||||
project: GCemu
|
||||
created: 2004-6-18
|
||||
mail: duddie@walla.com
|
||||
|
||||
Copyright (c) 2005 Duddie & Tratax
|
||||
|
||||
This program is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU General Public License
|
||||
as published by the Free Software Foundation; either version 2
|
||||
of the License, or (at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
====================================================================*/
|
||||
#ifndef _GDSP_OPCODES_H
|
||||
#define _GDSP_OPCODES_H
|
||||
|
||||
void dsp_op0(uint16 opc);
|
||||
void dsp_op1(uint16 opc);
|
||||
void dsp_op2(uint16 opc);
|
||||
void dsp_op3(uint16 opc);
|
||||
void dsp_op4(uint16 opc);
|
||||
void dsp_op5(uint16 opc);
|
||||
void dsp_op6(uint16 opc);
|
||||
void dsp_op7(uint16 opc);
|
||||
void dsp_op8(uint16 opc);
|
||||
void dsp_op9(uint16 opc);
|
||||
void dsp_opab(uint16 opc);
|
||||
void dsp_opcd(uint16 opc);
|
||||
void dsp_ope(uint16 opc);
|
||||
void dsp_opf(uint16 opc);
|
||||
|
||||
|
||||
#define R_SR 0x13
|
||||
|
||||
#define FLAG_ENABLE_INTERUPT 11
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,155 +1,155 @@
|
||||
// stdafx.cpp : source file that includes just the standard includes
|
||||
// DSP_InterC.pch will be the pre-compiled header
|
||||
// stdafx.obj will contain the pre-compiled type information
|
||||
|
||||
#include "stdafx.h"
|
||||
|
||||
#include <stdarg.h>
|
||||
#include <stdio.h>
|
||||
|
||||
namespace OutBuffer
|
||||
{
|
||||
void Init()
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void Add(const char* _fmt, ...)
|
||||
{
|
||||
static char Msg[2048];
|
||||
va_list ap;
|
||||
|
||||
va_start(ap, _fmt);
|
||||
vsprintf(Msg, _fmt, ap);
|
||||
va_end(ap);
|
||||
|
||||
printf("%s\n", Msg);
|
||||
}
|
||||
|
||||
void AddCode(const char* _fmt, ...)
|
||||
{
|
||||
static char Msg[2048];
|
||||
va_list ap;
|
||||
|
||||
va_start(ap, _fmt);
|
||||
vsprintf(Msg, _fmt, ap);
|
||||
va_end(ap);
|
||||
|
||||
printf(" %s;\n", Msg);
|
||||
}
|
||||
|
||||
// predefined labels
|
||||
typedef struct pdlabel_t
|
||||
{
|
||||
uint16 addr;
|
||||
const char* name;
|
||||
const char* description;
|
||||
} pdlabels_t;
|
||||
|
||||
pdlabel_t regnames[] =
|
||||
{
|
||||
{0x00, "R00", "Register 00",},
|
||||
{0x01, "R01", "Register 01",},
|
||||
{0x02, "R02", "Register 02",},
|
||||
{0x03, "R03", "Register 03",},
|
||||
{0x04, "R04", "Register 04",},
|
||||
{0x05, "R05", "Register 05",},
|
||||
{0x06, "R06", "Register 06",},
|
||||
{0x07, "R07", "Register 07",},
|
||||
{0x08, "R08", "Register 08",},
|
||||
{0x09, "R09", "Register 09",},
|
||||
{0x0a, "R10", "Register 10",},
|
||||
{0x0b, "R11", "Register 11",},
|
||||
{0x0c, "ST0", "Call stack",},
|
||||
{0x0d, "ST1", "Data stack",},
|
||||
{0x0e, "ST2", "Loop address stack",},
|
||||
{0x0f, "ST3", "Loop counter",},
|
||||
{0x00, "ACH0", "Accumulator High 0",},
|
||||
{0x11, "ACH1", "Accumulator High 1",},
|
||||
{0x12, "CR", "Config Register",},
|
||||
{0x13, "SR", "Special Register",},
|
||||
{0x14, "PROD_l", "PROD L",},
|
||||
{0x15, "PROD_m1", "PROD M1",},
|
||||
{0x16, "PROD_h", "PROD H",},
|
||||
{0x17, "PROD_m2", "PROD M2",},
|
||||
{0x18, "AX0_l", "Additional Accumulators Low 0",},
|
||||
{0x19, "AX1_l", "Additional Accumulators Low 1",},
|
||||
{0x1a, "AX0_h", "Additional Accumulators High 0",},
|
||||
{0x1b, "AX1_h", "Additional Accumulators High 1",},
|
||||
{0x1c, "AC0_l", "Register 28",},
|
||||
{0x1d, "AC1_l", "Register 29",},
|
||||
{0x1e, "AC0_m", "Register 00",},
|
||||
{0x1f, "AC1_m", "Register 00",},
|
||||
|
||||
// additional to resolve special names
|
||||
{0x20, "ACC0", "Accumulators 0",},
|
||||
{0x21, "ACC1", "Accumulators 1",},
|
||||
{0x22, "AX0", "Additional Accumulators 0",},
|
||||
{0x23, "AX1", "Additional Accumulators 1",},
|
||||
};
|
||||
|
||||
const pdlabel_t pdlabels[] =
|
||||
{
|
||||
{0xffa0, "COEF_A1_0", "COEF_A1_0",},
|
||||
{0xffa1, "COEF_A2_0", "COEF_A2_0",},
|
||||
{0xffa2, "COEF_A1_1", "COEF_A1_1",},
|
||||
{0xffa3, "COEF_A2_1", "COEF_A2_1",},
|
||||
{0xffa4, "COEF_A1_2", "COEF_A1_2",},
|
||||
{0xffa5, "COEF_A2_2", "COEF_A2_2",},
|
||||
{0xffa6, "COEF_A1_3", "COEF_A1_3",},
|
||||
{0xffa7, "COEF_A2_3", "COEF_A2_3",},
|
||||
{0xffa8, "COEF_A1_4", "COEF_A1_4",},
|
||||
{0xffa9, "COEF_A2_4", "COEF_A2_4",},
|
||||
{0xffaa, "COEF_A1_5", "COEF_A1_5",},
|
||||
{0xffab, "COEF_A2_5", "COEF_A2_5",},
|
||||
{0xffac, "COEF_A1_6", "COEF_A1_6",},
|
||||
{0xffad, "COEF_A2_6", "COEF_A2_6",},
|
||||
{0xffae, "COEF_A1_7", "COEF_A1_7",},
|
||||
{0xffaf, "COEF_A2_7", "COEF_A2_7",},
|
||||
{0xffc9, "DSCR", "DSP DMA Control Reg",},
|
||||
{0xffcb, "DSBL", "DSP DMA Block Length",},
|
||||
{0xffcd, "DSPA", "DSP DMA DMEM Address",},
|
||||
{0xffce, "DSMAH", "DSP DMA Mem Address H",},
|
||||
{0xffcf, "DSMAL", "DSP DMA Mem Address L",},
|
||||
{0xffd1, "SampleFormat", "SampleFormat",},
|
||||
|
||||
{0xffd3, "Unk Zelda", "Unk Zelda writes to it",},
|
||||
|
||||
{0xffd4, "ACSAH", "Accelerator start address H",},
|
||||
{0xffd5, "ACSAL", "Accelerator start address L",},
|
||||
{0xffd6, "ACEAH", "Accelerator end address H",},
|
||||
{0xffd7, "ACEAL", "Accelerator end address L",},
|
||||
{0xffd8, "ACCAH", "Accelerator current address H",},
|
||||
{0xffd9, "ACCAL", "Accelerator current address L",},
|
||||
{0xffda, "pred_scale", "pred_scale",},
|
||||
{0xffdb, "yn1", "yn1",},
|
||||
{0xffdc, "yn2", "yn2",},
|
||||
{0xffdd, "ARAM", "Direct Read from ARAM (uses ADPCM)",},
|
||||
{0xffde, "GAIN", "Gain",},
|
||||
{0xffef, "AMDM", "ARAM DMA Request Mask",},
|
||||
{0xfffb, "DIRQ", "DSP IRQ Request",},
|
||||
{0xfffc, "DMBH", "DSP Mailbox H",},
|
||||
{0xfffd, "DMBL", "DSP Mailbox L",},
|
||||
{0xfffe, "CMBH", "CPU Mailbox H",},
|
||||
{0xffff, "CMBL", "CPU Mailbox L",},
|
||||
};
|
||||
|
||||
const char* GetRegName(uint16 reg)
|
||||
{
|
||||
return regnames[reg].name;
|
||||
}
|
||||
|
||||
const char* GetMemName(uint16 addr)
|
||||
{
|
||||
static char Buffer[1024];
|
||||
for (int i=0; i<sizeof(pdlabels); i++)
|
||||
{
|
||||
if (pdlabels[i].addr == addr)
|
||||
return pdlabels[i].name;
|
||||
}
|
||||
|
||||
sprintf(Buffer, "0x%4x", addr);
|
||||
return Buffer;
|
||||
}
|
||||
}
|
||||
|
||||
// stdafx.cpp : source file that includes just the standard includes
|
||||
// DSP_InterC.pch will be the pre-compiled header
|
||||
// stdafx.obj will contain the pre-compiled type information
|
||||
|
||||
#include "stdafx.h"
|
||||
|
||||
#include <stdarg.h>
|
||||
#include <stdio.h>
|
||||
|
||||
namespace OutBuffer
|
||||
{
|
||||
void Init()
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void Add(const char* _fmt, ...)
|
||||
{
|
||||
static char Msg[2048];
|
||||
va_list ap;
|
||||
|
||||
va_start(ap, _fmt);
|
||||
vsprintf(Msg, _fmt, ap);
|
||||
va_end(ap);
|
||||
|
||||
printf("%s\n", Msg);
|
||||
}
|
||||
|
||||
void AddCode(const char* _fmt, ...)
|
||||
{
|
||||
static char Msg[2048];
|
||||
va_list ap;
|
||||
|
||||
va_start(ap, _fmt);
|
||||
vsprintf(Msg, _fmt, ap);
|
||||
va_end(ap);
|
||||
|
||||
printf(" %s;\n", Msg);
|
||||
}
|
||||
|
||||
// predefined labels
|
||||
typedef struct pdlabel_t
|
||||
{
|
||||
uint16 addr;
|
||||
const char* name;
|
||||
const char* description;
|
||||
} pdlabels_t;
|
||||
|
||||
pdlabel_t regnames[] =
|
||||
{
|
||||
{0x00, "R00", "Register 00",},
|
||||
{0x01, "R01", "Register 01",},
|
||||
{0x02, "R02", "Register 02",},
|
||||
{0x03, "R03", "Register 03",},
|
||||
{0x04, "R04", "Register 04",},
|
||||
{0x05, "R05", "Register 05",},
|
||||
{0x06, "R06", "Register 06",},
|
||||
{0x07, "R07", "Register 07",},
|
||||
{0x08, "R08", "Register 08",},
|
||||
{0x09, "R09", "Register 09",},
|
||||
{0x0a, "R10", "Register 10",},
|
||||
{0x0b, "R11", "Register 11",},
|
||||
{0x0c, "ST0", "Call stack",},
|
||||
{0x0d, "ST1", "Data stack",},
|
||||
{0x0e, "ST2", "Loop address stack",},
|
||||
{0x0f, "ST3", "Loop counter",},
|
||||
{0x00, "ACH0", "Accumulator High 0",},
|
||||
{0x11, "ACH1", "Accumulator High 1",},
|
||||
{0x12, "CR", "Config Register",},
|
||||
{0x13, "SR", "Special Register",},
|
||||
{0x14, "PROD_l", "PROD L",},
|
||||
{0x15, "PROD_m1", "PROD M1",},
|
||||
{0x16, "PROD_h", "PROD H",},
|
||||
{0x17, "PROD_m2", "PROD M2",},
|
||||
{0x18, "AX0_l", "Additional Accumulators Low 0",},
|
||||
{0x19, "AX1_l", "Additional Accumulators Low 1",},
|
||||
{0x1a, "AX0_h", "Additional Accumulators High 0",},
|
||||
{0x1b, "AX1_h", "Additional Accumulators High 1",},
|
||||
{0x1c, "AC0_l", "Register 28",},
|
||||
{0x1d, "AC1_l", "Register 29",},
|
||||
{0x1e, "AC0_m", "Register 00",},
|
||||
{0x1f, "AC1_m", "Register 00",},
|
||||
|
||||
// additional to resolve special names
|
||||
{0x20, "ACC0", "Accumulators 0",},
|
||||
{0x21, "ACC1", "Accumulators 1",},
|
||||
{0x22, "AX0", "Additional Accumulators 0",},
|
||||
{0x23, "AX1", "Additional Accumulators 1",},
|
||||
};
|
||||
|
||||
const pdlabel_t pdlabels[] =
|
||||
{
|
||||
{0xffa0, "COEF_A1_0", "COEF_A1_0",},
|
||||
{0xffa1, "COEF_A2_0", "COEF_A2_0",},
|
||||
{0xffa2, "COEF_A1_1", "COEF_A1_1",},
|
||||
{0xffa3, "COEF_A2_1", "COEF_A2_1",},
|
||||
{0xffa4, "COEF_A1_2", "COEF_A1_2",},
|
||||
{0xffa5, "COEF_A2_2", "COEF_A2_2",},
|
||||
{0xffa6, "COEF_A1_3", "COEF_A1_3",},
|
||||
{0xffa7, "COEF_A2_3", "COEF_A2_3",},
|
||||
{0xffa8, "COEF_A1_4", "COEF_A1_4",},
|
||||
{0xffa9, "COEF_A2_4", "COEF_A2_4",},
|
||||
{0xffaa, "COEF_A1_5", "COEF_A1_5",},
|
||||
{0xffab, "COEF_A2_5", "COEF_A2_5",},
|
||||
{0xffac, "COEF_A1_6", "COEF_A1_6",},
|
||||
{0xffad, "COEF_A2_6", "COEF_A2_6",},
|
||||
{0xffae, "COEF_A1_7", "COEF_A1_7",},
|
||||
{0xffaf, "COEF_A2_7", "COEF_A2_7",},
|
||||
{0xffc9, "DSCR", "DSP DMA Control Reg",},
|
||||
{0xffcb, "DSBL", "DSP DMA Block Length",},
|
||||
{0xffcd, "DSPA", "DSP DMA DMEM Address",},
|
||||
{0xffce, "DSMAH", "DSP DMA Mem Address H",},
|
||||
{0xffcf, "DSMAL", "DSP DMA Mem Address L",},
|
||||
{0xffd1, "SampleFormat", "SampleFormat",},
|
||||
|
||||
{0xffd3, "Unk Zelda", "Unk Zelda writes to it",},
|
||||
|
||||
{0xffd4, "ACSAH", "Accelerator start address H",},
|
||||
{0xffd5, "ACSAL", "Accelerator start address L",},
|
||||
{0xffd6, "ACEAH", "Accelerator end address H",},
|
||||
{0xffd7, "ACEAL", "Accelerator end address L",},
|
||||
{0xffd8, "ACCAH", "Accelerator current address H",},
|
||||
{0xffd9, "ACCAL", "Accelerator current address L",},
|
||||
{0xffda, "pred_scale", "pred_scale",},
|
||||
{0xffdb, "yn1", "yn1",},
|
||||
{0xffdc, "yn2", "yn2",},
|
||||
{0xffdd, "ARAM", "Direct Read from ARAM (uses ADPCM)",},
|
||||
{0xffde, "GAIN", "Gain",},
|
||||
{0xffef, "AMDM", "ARAM DMA Request Mask",},
|
||||
{0xfffb, "DIRQ", "DSP IRQ Request",},
|
||||
{0xfffc, "DMBH", "DSP Mailbox H",},
|
||||
{0xfffd, "DMBL", "DSP Mailbox L",},
|
||||
{0xfffe, "CMBH", "CPU Mailbox H",},
|
||||
{0xffff, "CMBL", "CPU Mailbox L",},
|
||||
};
|
||||
|
||||
const char* GetRegName(uint16 reg)
|
||||
{
|
||||
return regnames[reg].name;
|
||||
}
|
||||
|
||||
const char* GetMemName(uint16 addr)
|
||||
{
|
||||
static char Buffer[1024];
|
||||
for (int i=0; i<sizeof(pdlabels); i++)
|
||||
{
|
||||
if (pdlabels[i].addr == addr)
|
||||
return pdlabels[i].name;
|
||||
}
|
||||
|
||||
sprintf(Buffer, "0x%4x", addr);
|
||||
return Buffer;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1,23 +1,23 @@
|
||||
// stdafx.h : include file for standard system include files,
|
||||
// or project specific include files that are used frequently, but
|
||||
// are changed infrequently
|
||||
//
|
||||
|
||||
#pragma once
|
||||
|
||||
namespace OutBuffer
|
||||
{
|
||||
void Init();
|
||||
|
||||
void Add(const char* _fmt, ...);
|
||||
void AddCode(const char* _fmt, ...);
|
||||
|
||||
const char* GetRegName(uint16 reg);
|
||||
const char* GetMemName(uint16 addr);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// TODO: reference additional headers your program requires here
|
||||
// stdafx.h : include file for standard system include files,
|
||||
// or project specific include files that are used frequently, but
|
||||
// are changed infrequently
|
||||
//
|
||||
|
||||
#pragma once
|
||||
|
||||
namespace OutBuffer
|
||||
{
|
||||
void Init();
|
||||
|
||||
void Add(const char* _fmt, ...);
|
||||
void AddCode(const char* _fmt, ...);
|
||||
|
||||
const char* GetRegName(uint16 reg);
|
||||
const char* GetMemName(uint16 addr);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// TODO: reference additional headers your program requires here
|
||||
|
||||
@ -1,234 +1,234 @@
|
||||
/*====================================================================
|
||||
|
||||
filename: opcodes.h
|
||||
project: GameCube DSP Tool (gcdsp)
|
||||
created: 2005.03.04
|
||||
mail: duddie@walla.com
|
||||
|
||||
Copyright (c) 2005 Duddie
|
||||
|
||||
This program is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU General Public License
|
||||
as published by the Free Software Foundation; either version 2
|
||||
of the License, or (at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
====================================================================*/
|
||||
|
||||
#ifndef _GDSP_OPCODES_HELPER_H
|
||||
#define _GDSP_OPCODES_HELPER_H
|
||||
|
||||
#include "Globals.h"
|
||||
|
||||
#include "gdsp_opcodes.h"
|
||||
#include "gdsp_memory.h"
|
||||
#include "gdsp_interpreter.h"
|
||||
#include "gdsp_registers.h"
|
||||
#include "gdsp_ext_op.h"
|
||||
|
||||
// ---------------------------------------------------------------------------------------
|
||||
//
|
||||
// --- SR
|
||||
//
|
||||
// ---------------------------------------------------------------------------------------
|
||||
|
||||
inline void dsp_SR_set_flag(uint8 flag)
|
||||
{
|
||||
g_dsp.r[R_SR] |= (1 << flag);
|
||||
}
|
||||
|
||||
|
||||
inline bool dsp_SR_is_flag_set(uint8 flag)
|
||||
{
|
||||
return((g_dsp.r[R_SR] & (1 << flag)) > 0);
|
||||
}
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------------------
|
||||
//
|
||||
// --- reg
|
||||
//
|
||||
// ---------------------------------------------------------------------------------------
|
||||
|
||||
inline uint16 dsp_op_read_reg(uint8 reg)
|
||||
{
|
||||
uint16 val;
|
||||
|
||||
switch (reg & 0x1f)
|
||||
{
|
||||
case 0x0c:
|
||||
case 0x0d:
|
||||
case 0x0e:
|
||||
case 0x0f:
|
||||
val = dsp_reg_load_stack(reg - 0x0c);
|
||||
break;
|
||||
|
||||
default:
|
||||
val = g_dsp.r[reg];
|
||||
break;
|
||||
}
|
||||
|
||||
return(val);
|
||||
}
|
||||
|
||||
|
||||
inline void dsp_op_write_reg(uint8 reg, uint16 val)
|
||||
{
|
||||
switch (reg & 0x1f)
|
||||
{
|
||||
case 0x0c:
|
||||
case 0x0d:
|
||||
case 0x0e:
|
||||
case 0x0f:
|
||||
dsp_reg_store_stack(reg - 0x0c, val);
|
||||
break;
|
||||
|
||||
default:
|
||||
g_dsp.r[reg] = val;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------------------
|
||||
//
|
||||
// --- prod
|
||||
//
|
||||
// ---------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
inline sint64 dsp_get_long_prod()
|
||||
{
|
||||
sint64 val;
|
||||
sint64 low_prod;
|
||||
val = (sint8)g_dsp.r[0x16];
|
||||
val <<= 32;
|
||||
low_prod = g_dsp.r[0x15];
|
||||
low_prod += g_dsp.r[0x17];
|
||||
low_prod <<= 16;
|
||||
low_prod |= g_dsp.r[0x14];
|
||||
val += low_prod;
|
||||
return(val);
|
||||
}
|
||||
|
||||
|
||||
inline void dsp_set_long_prod(sint64 val)
|
||||
{
|
||||
g_dsp.r[0x14] = (uint16)val;
|
||||
val >>= 16;
|
||||
g_dsp.r[0x15] = (uint16)val;
|
||||
val >>= 16;
|
||||
g_dsp.r[0x16] = (uint16)val;
|
||||
g_dsp.r[0x17] = 0;
|
||||
}
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------------------
|
||||
//
|
||||
// --- acc
|
||||
//
|
||||
// ---------------------------------------------------------------------------------------
|
||||
|
||||
inline sint64 dsp_get_long_acc(uint8 reg)
|
||||
{
|
||||
_dbg_assert_(reg < 2);
|
||||
sint64 val;
|
||||
sint64 low_acc;
|
||||
val = (sint8)g_dsp.r[0x10 + reg];
|
||||
val <<= 32;
|
||||
low_acc = g_dsp.r[0x1e + reg];
|
||||
low_acc <<= 16;
|
||||
low_acc |= g_dsp.r[0x1c + reg];
|
||||
val |= low_acc;
|
||||
return(val);
|
||||
}
|
||||
|
||||
|
||||
inline uint64 dsp_get_ulong_acc(uint8 reg)
|
||||
{
|
||||
_dbg_assert_(reg < 2);
|
||||
uint64 val;
|
||||
uint64 low_acc;
|
||||
val = (uint8)g_dsp.r[0x10 + reg];
|
||||
val <<= 32;
|
||||
low_acc = g_dsp.r[0x1e + reg];
|
||||
low_acc <<= 16;
|
||||
low_acc |= g_dsp.r[0x1c + reg];
|
||||
val |= low_acc;
|
||||
return(val);
|
||||
}
|
||||
|
||||
|
||||
inline void dsp_set_long_acc(uint8 _reg, sint64 val)
|
||||
{
|
||||
_dbg_assert_(_reg < 2);
|
||||
g_dsp.r[0x1c + _reg] = (uint16)val;
|
||||
val >>= 16;
|
||||
g_dsp.r[0x1e + _reg] = (uint16)val;
|
||||
val >>= 16;
|
||||
g_dsp.r[0x10 + _reg] = (uint16)val;
|
||||
}
|
||||
|
||||
|
||||
inline sint16 dsp_get_acc_l(uint8 _reg)
|
||||
{
|
||||
_dbg_assert_(_reg < 2);
|
||||
return(g_dsp.r[0x1c + _reg]);
|
||||
}
|
||||
|
||||
|
||||
inline sint16 dsp_get_acc_m(uint8 _reg)
|
||||
{
|
||||
_dbg_assert_(_reg < 2);
|
||||
return(g_dsp.r[0x1e + _reg]);
|
||||
}
|
||||
|
||||
|
||||
inline sint16 dsp_get_acc_h(uint8 _reg)
|
||||
{
|
||||
_dbg_assert_(_reg < 2);
|
||||
return(g_dsp.r[0x10 + _reg]);
|
||||
}
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------------------
|
||||
//
|
||||
// --- acx
|
||||
//
|
||||
// ---------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
inline sint64 dsp_get_long_acx(uint8 _reg)
|
||||
{
|
||||
_dbg_assert_(_reg < 2);
|
||||
sint64 val = (sint16)g_dsp.r[0x1a + _reg];
|
||||
val <<= 16;
|
||||
sint64 low_acc = g_dsp.r[0x18 + _reg];
|
||||
val |= low_acc;
|
||||
return(val);
|
||||
}
|
||||
|
||||
|
||||
inline sint16 dsp_get_ax_l(uint8 _reg)
|
||||
{
|
||||
_dbg_assert_(_reg < 2);
|
||||
return(g_dsp.r[0x18 + _reg]);
|
||||
}
|
||||
|
||||
|
||||
inline sint16 dsp_get_ax_h(uint8 _reg)
|
||||
{
|
||||
_dbg_assert_(_reg < 2);
|
||||
return(g_dsp.r[0x1a + _reg]);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
/*====================================================================
|
||||
|
||||
filename: opcodes.h
|
||||
project: GameCube DSP Tool (gcdsp)
|
||||
created: 2005.03.04
|
||||
mail: duddie@walla.com
|
||||
|
||||
Copyright (c) 2005 Duddie
|
||||
|
||||
This program is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU General Public License
|
||||
as published by the Free Software Foundation; either version 2
|
||||
of the License, or (at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
====================================================================*/
|
||||
|
||||
#ifndef _GDSP_OPCODES_HELPER_H
|
||||
#define _GDSP_OPCODES_HELPER_H
|
||||
|
||||
#include "Globals.h"
|
||||
|
||||
#include "gdsp_opcodes.h"
|
||||
#include "gdsp_memory.h"
|
||||
#include "gdsp_interpreter.h"
|
||||
#include "gdsp_registers.h"
|
||||
#include "gdsp_ext_op.h"
|
||||
|
||||
// ---------------------------------------------------------------------------------------
|
||||
//
|
||||
// --- SR
|
||||
//
|
||||
// ---------------------------------------------------------------------------------------
|
||||
|
||||
inline void dsp_SR_set_flag(uint8 flag)
|
||||
{
|
||||
g_dsp.r[R_SR] |= (1 << flag);
|
||||
}
|
||||
|
||||
|
||||
inline bool dsp_SR_is_flag_set(uint8 flag)
|
||||
{
|
||||
return((g_dsp.r[R_SR] & (1 << flag)) > 0);
|
||||
}
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------------------
|
||||
//
|
||||
// --- reg
|
||||
//
|
||||
// ---------------------------------------------------------------------------------------
|
||||
|
||||
inline uint16 dsp_op_read_reg(uint8 reg)
|
||||
{
|
||||
uint16 val;
|
||||
|
||||
switch (reg & 0x1f)
|
||||
{
|
||||
case 0x0c:
|
||||
case 0x0d:
|
||||
case 0x0e:
|
||||
case 0x0f:
|
||||
val = dsp_reg_load_stack(reg - 0x0c);
|
||||
break;
|
||||
|
||||
default:
|
||||
val = g_dsp.r[reg];
|
||||
break;
|
||||
}
|
||||
|
||||
return(val);
|
||||
}
|
||||
|
||||
|
||||
inline void dsp_op_write_reg(uint8 reg, uint16 val)
|
||||
{
|
||||
switch (reg & 0x1f)
|
||||
{
|
||||
case 0x0c:
|
||||
case 0x0d:
|
||||
case 0x0e:
|
||||
case 0x0f:
|
||||
dsp_reg_store_stack(reg - 0x0c, val);
|
||||
break;
|
||||
|
||||
default:
|
||||
g_dsp.r[reg] = val;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------------------
|
||||
//
|
||||
// --- prod
|
||||
//
|
||||
// ---------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
inline sint64 dsp_get_long_prod()
|
||||
{
|
||||
sint64 val;
|
||||
sint64 low_prod;
|
||||
val = (sint8)g_dsp.r[0x16];
|
||||
val <<= 32;
|
||||
low_prod = g_dsp.r[0x15];
|
||||
low_prod += g_dsp.r[0x17];
|
||||
low_prod <<= 16;
|
||||
low_prod |= g_dsp.r[0x14];
|
||||
val += low_prod;
|
||||
return(val);
|
||||
}
|
||||
|
||||
|
||||
inline void dsp_set_long_prod(sint64 val)
|
||||
{
|
||||
g_dsp.r[0x14] = (uint16)val;
|
||||
val >>= 16;
|
||||
g_dsp.r[0x15] = (uint16)val;
|
||||
val >>= 16;
|
||||
g_dsp.r[0x16] = (uint16)val;
|
||||
g_dsp.r[0x17] = 0;
|
||||
}
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------------------
|
||||
//
|
||||
// --- acc
|
||||
//
|
||||
// ---------------------------------------------------------------------------------------
|
||||
|
||||
inline sint64 dsp_get_long_acc(uint8 reg)
|
||||
{
|
||||
_dbg_assert_(reg < 2);
|
||||
sint64 val;
|
||||
sint64 low_acc;
|
||||
val = (sint8)g_dsp.r[0x10 + reg];
|
||||
val <<= 32;
|
||||
low_acc = g_dsp.r[0x1e + reg];
|
||||
low_acc <<= 16;
|
||||
low_acc |= g_dsp.r[0x1c + reg];
|
||||
val |= low_acc;
|
||||
return(val);
|
||||
}
|
||||
|
||||
|
||||
inline uint64 dsp_get_ulong_acc(uint8 reg)
|
||||
{
|
||||
_dbg_assert_(reg < 2);
|
||||
uint64 val;
|
||||
uint64 low_acc;
|
||||
val = (uint8)g_dsp.r[0x10 + reg];
|
||||
val <<= 32;
|
||||
low_acc = g_dsp.r[0x1e + reg];
|
||||
low_acc <<= 16;
|
||||
low_acc |= g_dsp.r[0x1c + reg];
|
||||
val |= low_acc;
|
||||
return(val);
|
||||
}
|
||||
|
||||
|
||||
inline void dsp_set_long_acc(uint8 _reg, sint64 val)
|
||||
{
|
||||
_dbg_assert_(_reg < 2);
|
||||
g_dsp.r[0x1c + _reg] = (uint16)val;
|
||||
val >>= 16;
|
||||
g_dsp.r[0x1e + _reg] = (uint16)val;
|
||||
val >>= 16;
|
||||
g_dsp.r[0x10 + _reg] = (uint16)val;
|
||||
}
|
||||
|
||||
|
||||
inline sint16 dsp_get_acc_l(uint8 _reg)
|
||||
{
|
||||
_dbg_assert_(_reg < 2);
|
||||
return(g_dsp.r[0x1c + _reg]);
|
||||
}
|
||||
|
||||
|
||||
inline sint16 dsp_get_acc_m(uint8 _reg)
|
||||
{
|
||||
_dbg_assert_(_reg < 2);
|
||||
return(g_dsp.r[0x1e + _reg]);
|
||||
}
|
||||
|
||||
|
||||
inline sint16 dsp_get_acc_h(uint8 _reg)
|
||||
{
|
||||
_dbg_assert_(_reg < 2);
|
||||
return(g_dsp.r[0x10 + _reg]);
|
||||
}
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------------------
|
||||
//
|
||||
// --- acx
|
||||
//
|
||||
// ---------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
inline sint64 dsp_get_long_acx(uint8 _reg)
|
||||
{
|
||||
_dbg_assert_(_reg < 2);
|
||||
sint64 val = (sint16)g_dsp.r[0x1a + _reg];
|
||||
val <<= 16;
|
||||
sint64 low_acc = g_dsp.r[0x18 + _reg];
|
||||
val |= low_acc;
|
||||
return(val);
|
||||
}
|
||||
|
||||
|
||||
inline sint16 dsp_get_ax_l(uint8 _reg)
|
||||
{
|
||||
_dbg_assert_(_reg < 2);
|
||||
return(g_dsp.r[0x18 + _reg]);
|
||||
}
|
||||
|
||||
|
||||
inline sint16 dsp_get_ax_h(uint8 _reg)
|
||||
{
|
||||
_dbg_assert_(_reg < 2);
|
||||
return(g_dsp.r[0x1a + _reg]);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,23 +1,23 @@
|
||||
// stdafx.cpp : source file that includes just the standard includes
|
||||
// DSP_InterC.pch will be the pre-compiled header
|
||||
// stdafx.obj will contain the pre-compiled type information
|
||||
|
||||
#include "stdafx.h"
|
||||
|
||||
// TODO: reference any additional headers you need in STDAFX.H
|
||||
// and not in this file
|
||||
|
||||
#include <stdarg.h>
|
||||
|
||||
void ErrorLog(const char* _fmt, ...)
|
||||
{
|
||||
char Msg[512];
|
||||
va_list ap;
|
||||
|
||||
va_start(ap, _fmt);
|
||||
vsprintf(Msg, _fmt, ap);
|
||||
va_end(ap);
|
||||
|
||||
printf("Error");
|
||||
|
||||
// stdafx.cpp : source file that includes just the standard includes
|
||||
// DSP_InterC.pch will be the pre-compiled header
|
||||
// stdafx.obj will contain the pre-compiled type information
|
||||
|
||||
#include "stdafx.h"
|
||||
|
||||
// TODO: reference any additional headers you need in STDAFX.H
|
||||
// and not in this file
|
||||
|
||||
#include <stdarg.h>
|
||||
|
||||
void ErrorLog(const char* _fmt, ...)
|
||||
{
|
||||
char Msg[512];
|
||||
va_list ap;
|
||||
|
||||
va_start(ap, _fmt);
|
||||
vsprintf(Msg, _fmt, ap);
|
||||
va_end(ap);
|
||||
|
||||
printf("Error");
|
||||
|
||||
}
|
||||
@ -1,39 +1,39 @@
|
||||
// stdafx.h : include file for standard system include files,
|
||||
// or project specific include files that are used frequently, but
|
||||
// are changed infrequently
|
||||
//
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "targetver.h"
|
||||
|
||||
#include <stdio.h>
|
||||
#include <tchar.h>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
typedef unsigned char uint8;
|
||||
typedef unsigned short uint16;
|
||||
typedef unsigned int uint32;
|
||||
typedef unsigned long long uint64;
|
||||
typedef unsigned int uint;
|
||||
|
||||
typedef signed char sint8;
|
||||
typedef signed short sint16;
|
||||
typedef signed int sint32;
|
||||
typedef signed long long sint64;
|
||||
|
||||
extern uint16 FetchOpcode();
|
||||
extern void ErrorLog(const char* _fmt, ...);
|
||||
|
||||
inline uint16 swap16(uint16 x)
|
||||
{
|
||||
return((x >> 8) | (x << 8));
|
||||
}
|
||||
|
||||
#include "OutBuffer.h"
|
||||
|
||||
// TODO: reference additional headers your program requires here
|
||||
// stdafx.h : include file for standard system include files,
|
||||
// or project specific include files that are used frequently, but
|
||||
// are changed infrequently
|
||||
//
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "targetver.h"
|
||||
|
||||
#include <stdio.h>
|
||||
#include <tchar.h>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
typedef unsigned char uint8;
|
||||
typedef unsigned short uint16;
|
||||
typedef unsigned int uint32;
|
||||
typedef unsigned long long uint64;
|
||||
typedef unsigned int uint;
|
||||
|
||||
typedef signed char sint8;
|
||||
typedef signed short sint16;
|
||||
typedef signed int sint32;
|
||||
typedef signed long long sint64;
|
||||
|
||||
extern uint16 FetchOpcode();
|
||||
extern void ErrorLog(const char* _fmt, ...);
|
||||
|
||||
inline uint16 swap16(uint16 x)
|
||||
{
|
||||
return((x >> 8) | (x << 8));
|
||||
}
|
||||
|
||||
#include "OutBuffer.h"
|
||||
|
||||
// TODO: reference additional headers your program requires here
|
||||
|
||||
@ -1,13 +1,13 @@
|
||||
#pragma once
|
||||
|
||||
// The following macros define the minimum required platform. The minimum required platform
|
||||
// is the earliest version of Windows, Internet Explorer etc. that has the necessary features to run
|
||||
// your application. The macros work by enabling all features available on platform versions up to and
|
||||
// including the version specified.
|
||||
|
||||
// Modify the following defines if you have to target a platform prior to the ones specified below.
|
||||
// Refer to MSDN for the latest info on corresponding values for different platforms.
|
||||
#ifndef _WIN32_WINNT // Specifies that the minimum required platform is Windows Vista.
|
||||
#define _WIN32_WINNT 0x0600 // Change this to the appropriate value to target other versions of Windows.
|
||||
#endif
|
||||
|
||||
#pragma once
|
||||
|
||||
// The following macros define the minimum required platform. The minimum required platform
|
||||
// is the earliest version of Windows, Internet Explorer etc. that has the necessary features to run
|
||||
// your application. The macros work by enabling all features available on platform versions up to and
|
||||
// including the version specified.
|
||||
|
||||
// Modify the following defines if you have to target a platform prior to the ones specified below.
|
||||
// Refer to MSDN for the latest info on corresponding values for different platforms.
|
||||
#ifndef _WIN32_WINNT // Specifies that the minimum required platform is Windows Vista.
|
||||
#define _WIN32_WINNT 0x0600 // Change this to the appropriate value to target other versions of Windows.
|
||||
#endif
|
||||
|
||||
|
||||
@ -1,436 +1,436 @@
|
||||
/*
|
||||
ROM functions used:
|
||||
0x8000 dsp reset
|
||||
0x8078 wait for CMBH & 0x8000
|
||||
0x807e wait for DMBH & 0x8000
|
||||
0x808b dump DRAM/IRAM to mainmem
|
||||
0x80b5 boot new ucode
|
||||
0x80bc boot new ucode without ACC clearing by ROM
|
||||
|
||||
For the rest, this ucode is just calling the last few instructions
|
||||
from huge functions in ROM - some kind of obfuscation?
|
||||
|
||||
0x81f4
|
||||
81f4 b51e mulxac'mv $AX0.H, $AX1.L, $ACC1 : $AX1.H, $AC0.M
|
||||
81f5 9909 asr16'ir $ACC1 : $AR1
|
||||
81f6 1b7f srri @$AR3, $AC1.M
|
||||
81f7 812b clr's $ACC0 : @$AR3, $AC1.L
|
||||
0x8458
|
||||
8458 b51e mulxac'mv $AX0.H, $AX1.L, $ACC1 : $AX1.H, $AC0.M
|
||||
8459 9900 asr16 $ACC1
|
||||
845a 1b7f srri @$AR3, $AC1.M
|
||||
845b 812b clr's $ACC0 : @$AR3, $AC1.L
|
||||
0x8723
|
||||
8723 3300 xorr $AC1.M, $AX1.H
|
||||
8724 1adf srrd @$AR2, $AC1.M
|
||||
0x8809
|
||||
8809 392e orr'sn $AC1.M, $AX0.H : @$AR2, $AC1.L
|
||||
880a 1b5f srri @$AR2, $AC1.M
|
||||
0x88e5
|
||||
88e5 387a orr'l $AC0.M, $AX0.H : $AC1.M, @$AR2
|
||||
88e6 18dd lrrd $AC1.L, @$AR2
|
||||
88e7 4c05 add'dr $ACC0, $ACC1 : $AR1
|
||||
88e8 1b5e srri @$AR2, $AC0.M
|
||||
88e9 1a5c srr @$AR2, $AC0.L
|
||||
*/
|
||||
|
||||
0000 0000 nop
|
||||
0001 0000 nop
|
||||
0002 0000 nop
|
||||
0003 0000 nop
|
||||
0004 0000 nop
|
||||
0005 0000 nop
|
||||
0006 0000 nop
|
||||
0007 0000 nop
|
||||
0008 0000 nop
|
||||
0009 0000 nop
|
||||
000a 0000 nop
|
||||
000b 0000 nop
|
||||
000c 0000 nop
|
||||
000d 0021 halt
|
||||
000e 02ff rti
|
||||
000f 0021 halt
|
||||
|
||||
0010 1306 sbset #0x06
|
||||
0011 1203 sbclr #0x03
|
||||
0012 1204 sbclr #0x04
|
||||
0013 1305 sbset #0x05
|
||||
0014 0092 00ff lri $CR, #0x00ff
|
||||
0016 0088 ffff lri $WR0, #0xffff
|
||||
0018 0089 ffff lri $WR1, #0xffff
|
||||
001a 008a ffff lri $WR2, #0xffff
|
||||
001c 008b ffff lri $WR3, #0xffff
|
||||
001e 8f00 set40
|
||||
001f 8b00 m0
|
||||
0020 8c00 clr15
|
||||
0021 02bf 807e call 0x807e // loop until dsp->cpu mailbox is empty
|
||||
0023 16fc dcd1 si @DMBH, #0xdcd1
|
||||
0025 16fd 0000 si @DMBL, #0x0000 // sendmail 0xdcd10000
|
||||
0027 16fb 0001 si @DIRQ, #0x0001
|
||||
|
||||
// wait for cpu mail == 0xabbaxxxx
|
||||
0029 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
002b 24ff lrs $AC0.L, @CMBL
|
||||
002c 0280 abba cmpi $AC0.M, #0xabba
|
||||
002e 0294 0029 jnz 0x0029
|
||||
|
||||
// wait for cpu mail
|
||||
0030 8e00 set16
|
||||
0031 02bf 8078 call 0x8078
|
||||
|
||||
0033 20ff lrs $AX0.L, @CMBL
|
||||
0034 0240 0fff andi $AC0.M, #0x0fff
|
||||
0036 1f5e mrr $AX0.H, $AC0.M
|
||||
0037 009b 0000 lri $AX1.H, #0x0000 // DSP-dram addr
|
||||
0039 0099 0020 lri $AX1.L, #0x0020 // length (20 bytes = 10 words, word 9 and 10 are addr where result should DMA'd to in main mem)
|
||||
003b 0087 0000 lri $IX3, #0x0000 // there will be no ucode/iram upload
|
||||
003d 0080 0041 lri $AR0, #0x0041 // return addr after dram upload
|
||||
003f 029f 80bc jmp 0x80bc // DRAM upload !!
|
||||
// $AX0.H-$AX0.L - CPU(PPC) addr = mail & 0x0fffffff
|
||||
// upload data from mainmem do dsp dram and jump to 0x41 after that
|
||||
|
||||
0041 02bf 008c call 008c_BigCrazyFunction() // <<------------- main crap is here!!!!!!!!!
|
||||
0043 02bf 807e call 0x807e // loop until dsp->cpu mailbox is empty
|
||||
|
||||
0045 16fc dcd1 si @DMBH, #0xdcd1
|
||||
0047 16fd 0003 si @DMBL, #0x0003 // sendmail 0xdcd10003 (aka... calc is over, result is in main mem now)
|
||||
0049 16fb 0001 si @DIRQ, #0x0001
|
||||
004b 8f00 set40
|
||||
|
||||
004c 02bf 8078 call 0x8078
|
||||
004e 0280 cdd1 cmpi $AC0.M, #0xcdd1
|
||||
0050 0294 004c jnz 0x004c
|
||||
|
||||
0052 26ff lrs $AC0.M, @CMBL
|
||||
0053 0280 0001 cmpi $AC0.M, #0x0001
|
||||
0055 0295 005e jz 0x005e // if cpu->dsp mail was 0xcdd10001 -> 005e_PrepareBootUcode()
|
||||
|
||||
0057 0280 0002 cmpi $AC0.M, #0x0002
|
||||
0059 0295 8000 jz 0x8000 // if cpu->dsp mail was 0xcdd10002 -> dsp reset ( jmp to irom(0x8000))
|
||||
|
||||
005b 029f 004c jmp 0x004c // wait for next mail from cpu
|
||||
005d 0021 halt
|
||||
|
||||
void 005e_PrepareBootUcode()
|
||||
{
|
||||
005e 8e00 set16
|
||||
005f 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
0061 24ff lrs $AC0.L, @CMBL
|
||||
0062 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
0064 24ff lrs $AC0.L, @CMBL
|
||||
0065 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
0067 24ff lrs $AC0.L, @CMBL
|
||||
0068 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
006a 00c5 ffff lr $IX1, @CMBL
|
||||
006c 0240 0fff andi $AC0.M, #0x0fff
|
||||
006e 1c9e mrr $IX0, $AC0.M
|
||||
006f 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
0071 00c7 ffff lr $IX3, @CMBL
|
||||
0073 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
0075 00c6 ffff lr $IX2, @CMBL
|
||||
0077 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
0079 00c0 ffff lr $AR0, @CMBL
|
||||
007b 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
007d 20ff lrs $AX0.L, @CMBL
|
||||
007e 0240 0fff andi $AC0.M, #0x0fff
|
||||
0080 1f5e mrr $AX0.H, $AC0.M
|
||||
0081 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
0083 21ff lrs $AX1.L, @CMBL
|
||||
0084 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
0086 23ff lrs $AX1.H, @CMBL
|
||||
0087 1205 sbclr #0x05
|
||||
0088 1206 sbclr #0x06
|
||||
0089 029f 80b5 jmp 80b5_BootUcode()
|
||||
008b 0021 halt
|
||||
}
|
||||
|
||||
// does some crazy stuff with data at dram @0x3/0x5/0x6/0x7 with help of some values from drom :)
|
||||
// result is @0x22,@0x23 and written back to main memory to dmem-0x08:dmem-0x09
|
||||
void 008c_BigCrazyFunction()
|
||||
{
|
||||
008c 8100 clr $ACC0
|
||||
008d 0081 0010 lri $AR1, #0x0010
|
||||
008f 1020 loopi #0x20
|
||||
0090 1b3e srri @$AR1, $AC0.M
|
||||
0091 00df 1456 lr $AC1.M, @0x1456
|
||||
0093 0340 ffd0 andi $AC1.M, #0xffd0
|
||||
0095 8417 clrp'mv : $AX1.L, $AC1.M
|
||||
0096 0080 0000 lri $AR0, #0x0000
|
||||
0098 0086 0000 lri $IX2, #0x0000
|
||||
009a 0082 001f lri $AR2, #0x001f
|
||||
009c 00de 15f6 lr $AC0.M, @0x15f6
|
||||
009e 1408 lsl $ACC0, #8
|
||||
009f 00df 1766 lr $AC1.M, @0x1766
|
||||
00a1 0340 00ff andi $AC1.M, #0x00ff
|
||||
00a3 1f5f mrr $AX0.H, $AC1.M
|
||||
00a4 02bf 88e5 call 0x88e5
|
||||
88e5 387a orr'l $AC0.M, $AX0.H : $AC1.M, @$AR2
|
||||
88e6 18dd lrrd $AC1.L, @$AR2
|
||||
88e7 4c05 add'dr $ACC0, $ACC1 : $AR1
|
||||
88e8 1b5e srri @$AR2, $AC0.M
|
||||
88e9 1a5c srr @$AR2, $AC0.L
|
||||
00a6 1f1c mrr $AX0.L, $AC0.L
|
||||
00a7 811e clr'mv $ACC0 : $AX1.H, $AC0.M
|
||||
00a8 191e lrri $AC0.M, @$AR0
|
||||
00a9 1478 lsr $ACC0, #-8
|
||||
00aa 1ffc mrr $AC1.M, $AC0.L
|
||||
00ab 1f5e mrr $AX0.H, $AC0.M
|
||||
00ac 02bf 8809 call 0x8809
|
||||
8809 392e orr'sn $AC1.M, $AX0.H : @$AR2, $AC1.L
|
||||
880a 1b5f srri @$AR2, $AC1.M
|
||||
00ae 02bf 8723 call 0x8723
|
||||
8723 3300 xorr $AC1.M, $AX1.H
|
||||
8724 1adf srrd @$AR2, $AC1.M
|
||||
00b0 0006 dar $AR2
|
||||
00b1 8106 clr'dr $ACC0 : $AR2
|
||||
00b2 00de 166c lr $AC0.M, @0x166c
|
||||
00b4 1404 lsl $ACC0, #4
|
||||
00b5 0240 ff00 andi $AC0.M, #0xff00
|
||||
00b7 00df 1231 lr $AC1.M, @0x1231
|
||||
00b9 1578 lsr $ACC1, #-8
|
||||
00ba 0340 00ff andi $AC1.M, #0x00ff
|
||||
00bc 1f5f mrr $AX0.H, $AC1.M
|
||||
00bd 02bf 88e5 call 0x88e5
|
||||
88e5 387a orr'l $AC0.M, $AX0.H : $AC1.M, @$AR2
|
||||
88e6 18dd lrrd $AC1.L, @$AR2
|
||||
88e7 4c05 add'dr $ACC0, $ACC1 : $AR1
|
||||
88e8 1b5e srri @$AR2, $AC0.M
|
||||
88e9 1a5c srr @$AR2, $AC0.L
|
||||
00bf 1f1c mrr $AX0.L, $AC0.L
|
||||
00c0 811e clr'mv $ACC0 : $AX1.H, $AC0.M
|
||||
00c1 191e lrri $AC0.M, @$AR0
|
||||
00c2 1478 lsr $ACC0, #-8
|
||||
00c3 1ffc mrr $AC1.M, $AC0.L
|
||||
00c4 1f5e mrr $AX0.H, $AC0.M
|
||||
00c5 02bf 8809 call 0x8809
|
||||
8809 392e orr'sn $AC1.M, $AX0.H : @$AR2, $AC1.L
|
||||
880a 1b5f srri @$AR2, $AC1.M
|
||||
00c7 02bf 8723 call 0x8723
|
||||
8723 3300 xorr $AC1.M, $AX1.H
|
||||
8724 1adf srrd @$AR2, $AC1.M
|
||||
00c9 8100 clr $ACC0
|
||||
00ca 8900 clr $ACC1
|
||||
00cb 00d1 0005 lr $AC1.H, @0x0005
|
||||
00cd 9900 asr16 $ACC1
|
||||
00ce 8200 cmp
|
||||
00cf 0295 00e5 jz 0x00e5
|
||||
|
||||
00d1 0291 00f3 jl 0x00f3
|
||||
|
||||
00d3 0082 0010 lri $AR2, #0x0010
|
||||
00d5 0086 0001 lri $IX2, #0x0001
|
||||
00d7 00d0 171b lr $AC0.H, @0x171b
|
||||
00d9 9100 asr16 $ACC0
|
||||
00da 7d00 neg $ACC1
|
||||
00db 4d00 add $ACC1, $ACC0
|
||||
00dc 1501 lsl $ACC1, #1
|
||||
00dd 1f5f mrr $AX0.H, $AC1.M
|
||||
00de 00df 0003 lr $AC1.M, @0x0003
|
||||
00e0 1504 lsl $ACC1, #4
|
||||
00e1 02bf 8809 call 0x8809
|
||||
8809 392e orr'sn $AC1.M, $AX0.H : @$AR2, $AC1.L
|
||||
880a 1b5f srri @$AR2, $AC1.M
|
||||
00e3 029f 0102 jmp 0x0102
|
||||
|
||||
:
|
||||
00e5 0082 0011 lri $AR2, #0x0011
|
||||
00e7 00df 0003 lr $AC1.M, @0x0003
|
||||
00e9 1501 lsl $ACC1, #1
|
||||
00ea 1f5f mrr $AX0.H, $AC1.M
|
||||
00eb 00de 1043 lr $AC0.M, @0x1043
|
||||
00ed 0240 fff0 andi $AC0.M, #0xfff0
|
||||
00ef 02bf 88e5 call 0x88e5
|
||||
88e5 387a orr'l $AC0.M, $AX0.H : $AC1.M, @$AR2
|
||||
88e6 18dd lrrd $AC1.L, @$AR2
|
||||
88e7 4c05 add'dr $ACC0, $ACC1 : $AR1
|
||||
88e8 1b5e srri @$AR2, $AC0.M
|
||||
88e9 1a5c srr @$AR2, $AC0.L
|
||||
00f1 029f 0102 jmp 0x0102
|
||||
|
||||
:
|
||||
00f3 0082 0010 lri $AR2, #0x0010
|
||||
00f5 0086 0001 lri $IX2, #0x0001
|
||||
00f7 00d0 1285 lr $AC0.H, @0x1285
|
||||
00f9 9100 asr16 $ACC0
|
||||
00fa 4d00 add $ACC1, $ACC0
|
||||
00fb 1501 lsl $ACC1, #1
|
||||
00fc 00de 0003 lr $AC0.M, @0x0003
|
||||
00fe 1404 lsl $ACC0, #4
|
||||
00ff 1f5e mrr $AX0.H, $AC0.M
|
||||
0100 02bf 8809 call 0x8809
|
||||
8809 392e orr'sn $AC1.M, $AX0.H : @$AR2, $AC1.L
|
||||
880a 1b5f srri @$AR2, $AC1.M
|
||||
|
||||
:
|
||||
0102 0083 0013 lri $AR3, #0x0013
|
||||
0104 1b7e srri @$AR3, $AC0.M
|
||||
0105 8923 clr's $ACC1 : @$AR3, $AC0.L
|
||||
0106 0083 0013 lri $AR3, #0x0013
|
||||
0108 00df 0007 lr $AC1.M, @0x0007
|
||||
010a 00de 11b8 lr $AC0.M, @0x11b8
|
||||
010c 0240 fff0 andi $AC0.M, #0xfff0
|
||||
010e 1f5e mrr $AX0.H, $AC0.M
|
||||
010f 02bf 81f4 call 0x81f4
|
||||
81f4 b51e mulxac'mv $AX0.H, $AX1.L, $ACC1 : $AX1.H, $AC0.M
|
||||
81f5 9909 asr16'ir $ACC1 : $AR1
|
||||
81f6 1b7f srri @$AR3, $AC1.M
|
||||
81f7 812b clr's $ACC0 : @$AR3, $AC1.L
|
||||
0111 f100 lsl16 $ACC1
|
||||
0112 02bf 8458 call 0x8458
|
||||
8458 b51e mulxac'mv $AX0.H, $AX1.L, $ACC1 : $AX1.H, $AC0.M
|
||||
8459 9900 asr16 $ACC1
|
||||
845a 1b7f srri @$AR3, $AC1.M
|
||||
845b 812b clr's $ACC0 : @$AR3, $AC1.L
|
||||
0114 8f00 set40
|
||||
0115 0082 0015 lri $AR2, #0x0015
|
||||
0117 00de 0006 lr $AC0.M, @0x0006
|
||||
0119 00da 165b lr $AX0.H, @0x165b
|
||||
011b 02bf 88e5 call 0x88e5
|
||||
88e5 387a orr'l $AC0.M, $AX0.H : $AC1.M, @$AR2
|
||||
88e6 18dd lrrd $AC1.L, @$AR2
|
||||
88e7 4c05 add'dr $ACC0, $ACC1 : $AR1
|
||||
88e8 1b5e srri @$AR2, $AC0.M
|
||||
88e9 1a5c srr @$AR2, $AC0.L
|
||||
011d 14fd asr $ACC0, #-3
|
||||
011e 1403 lsl $ACC0, #3
|
||||
011f 1b5e srri @$AR2, $AC0.M
|
||||
0120 1b5c srri @$AR2, $AC0.L
|
||||
0121 0082 0016 lri $AR2, #0x0016
|
||||
0123 00de 1723 lr $AC0.M, @0x1723
|
||||
0125 14f4 asr $ACC0, #-12
|
||||
0126 00da 166b lr $AX0.H, @0x166b
|
||||
0128 02bf 88e5 call 0x88e5
|
||||
88e5 387a orr'l $AC0.M, $AX0.H : $AC1.M, @$AR2
|
||||
88e6 18dd lrrd $AC1.L, @$AR2
|
||||
88e7 4c05 add'dr $ACC0, $ACC1 : $AR1
|
||||
88e8 1b5e srri @$AR2, $AC0.M
|
||||
88e9 1a5c srr @$AR2, $AC0.L
|
||||
012a b100 tst $ACC0
|
||||
012b 0290 012e jge 0x012e
|
||||
|
||||
012d 8100 clr $ACC0
|
||||
|
||||
:
|
||||
012e 14fd asr $ACC0, #-3
|
||||
012f 8e00 set16
|
||||
0130 00df 1491 lr $AC1.M, @0x1491
|
||||
0132 0340 d0f0 andi $AC1.M, #0xd0f0
|
||||
0134 1cbf mrr $IX1, $AC1.M
|
||||
0135 00df 1468 lr $AC1.M, @0x1468
|
||||
0137 00d1 11fc lr $AC1.H, @0x11fc
|
||||
0139 157c lsr $ACC1, #-4
|
||||
013a 1cdf mrr $IX2, $AC1.M
|
||||
013b 00d1 11b8 lr $AC1.H, @0x11b8
|
||||
013d 9900 asr16 $ACC1
|
||||
013e 1418 lsl $ACC0, #24
|
||||
013f 1478 lsr $ACC0, #-8
|
||||
0140 1f5e mrr $AX0.H, $AC0.M
|
||||
0141 1ffe mrr $AC1.M, $AC0.M
|
||||
0142 1f65 mrr $AX1.H, $IX1
|
||||
0143 3600 andr $AC0.M, $AX1.H
|
||||
0144 1402 lsl $ACC0, #2
|
||||
0145 1f66 mrr $AX1.H, $IX2
|
||||
0146 3700 andr $AC1.M, $AX1.H
|
||||
0147 1501 lsl $ACC1, #1
|
||||
0148 4c00 add $ACC0, $ACC1
|
||||
0149 1518 lsl $ACC1, #24
|
||||
014a 9900 asr16 $ACC1
|
||||
014b 3500 andr $AC1.M, $AX0.H
|
||||
014c 4c00 add $ACC0, $ACC1
|
||||
014d 00df 0012 lr $AC1.M, @0x0012
|
||||
014f 3f00 orc $AC1.M, $AC0.M
|
||||
0150 00ff 0012 sr @0x0012, $AC1.M
|
||||
0152 1470 lsr $ACC0, #-16
|
||||
0153 00df 0011 lr $AC1.M, @0x0011
|
||||
0155 3f00 orc $AC1.M, $AC0.M
|
||||
0156 00ff 0011 sr @0x0011, $AC1.M
|
||||
0158 1fa5 mrr $AC1.L, $IX1
|
||||
0159 1501 lsl $ACC1, #1
|
||||
015a 1fe6 mrr $AC1.M, $IX2
|
||||
015b f100 lsl16 $ACC1
|
||||
015c 15f8 asr $ACC1, #-8
|
||||
015d f500 lsr16 $ACC1
|
||||
015e 1f5f mrr $AX0.H, $AC1.M
|
||||
015f 1f7d mrr $AX1.H, $AC1.L
|
||||
0160 8100 clr $ACC0
|
||||
0161 00de 0011 lr $AC0.M, @0x0011
|
||||
0163 3400 andr $AC0.M, $AX0.H
|
||||
0164 8900 clr $ACC1
|
||||
0165 00df 0012 lr $AC1.M, @0x0012
|
||||
0167 3500 andr $AC1.M, $AX0.H
|
||||
0168 4c00 add $ACC0, $ACC1
|
||||
0169 00df 0012 lr $AC1.M, @0x0012
|
||||
016b 1578 lsr $ACC1, #-8
|
||||
016c 4c00 add $ACC0, $ACC1
|
||||
016d 8900 clr $ACC1
|
||||
016e 1ffe mrr $AC1.M, $AC0.M
|
||||
016f 1508 lsl $ACC1, #8
|
||||
0170 3b00 orr $AC1.M, $AX1.H
|
||||
0171 00de 0011 lr $AC0.M, @0x0011
|
||||
0173 3e00 orc $AC0.M, $AC1.M
|
||||
0174 00df 0012 lr $AC1.M, @0x0012
|
||||
0176 3b00 orr $AC1.M, $AX1.H
|
||||
0177 1cbf mrr $IX1, $AC1.M
|
||||
0178 00da 15f1 lr $AX0.H, @0x15f1
|
||||
017a 3500 andr $AC1.M, $AX0.H
|
||||
017b 0295 0192 jz 0x0192
|
||||
if () {
|
||||
|
||||
017d 00df 10e2 lr $AC1.M, @0x10e2
|
||||
017f 1508 lsl $ACC1, #8
|
||||
0180 1f5f mrr $AX0.H, $AC1.M
|
||||
0181 00df 103b lr $AC1.M, @0x103b
|
||||
0183 7900 decm $AC1.M
|
||||
0184 3900 orr $AC1.M, $AX0.H
|
||||
0185 3080 xorc $AC0.M, $AC1.M
|
||||
0186 00fe 0022 sr @0x0022, $AC0.M
|
||||
0188 00dc 1229 lr $AC0.L, @0x1229
|
||||
018a 00dd 11f8 lr $AC1.L, @0x11f8
|
||||
018c 5c00 sub $ACC0, $ACC1
|
||||
018d f000 lsl16 $ACC0
|
||||
018e 1fe5 mrr $AC1.M, $IX1
|
||||
018f 3080 xorc $AC0.M, $AC1.M
|
||||
0190 029f 01a5 jmp 0x01a5
|
||||
|
||||
} else {
|
||||
|
||||
0192 00df 10ca lr $AC1.M, @0x10ca
|
||||
0194 1508 lsl $ACC1, #8
|
||||
0195 1f5f mrr $AX0.H, $AC1.M
|
||||
0196 00df 1043 lr $AC1.M, @0x1043
|
||||
0198 7500 incm $AC1.M
|
||||
0199 3900 orr $AC1.M, $AX0.H
|
||||
019a 3080 xorc $AC0.M, $AC1.M
|
||||
019b 00fe 0022 sr @0x0022, $AC0.M
|
||||
019d 00dc 1259 lr $AC0.L, @0x1259
|
||||
019f 00dd 16fe lr $AC1.L, @0x16fe
|
||||
01a1 4c00 add $ACC0, $ACC1
|
||||
01a2 f000 lsl16 $ACC0
|
||||
01a3 1fe5 mrr $AC1.M, $IX1
|
||||
01a4 3080 xorc $AC0.M, $AC1.M
|
||||
}
|
||||
|
||||
01a5 00fe 0023 sr @0x0023, $AC0.M
|
||||
// this is where result is written to main memory
|
||||
// dsp mem 0x20-0x23 (8 bytes) are written back, because only values @22 and @23 were modified result is 32bit
|
||||
01a7 00da 0008 lr $AX0.H, @0x0008 // cpu addr high
|
||||
01a9 00d8 0009 lr $AX0.L, @0x0009 // cpu addr low
|
||||
01ab 009b 0020 lri $AX1.H, #0x0020 // dsp addr
|
||||
01ad 0099 0008 lri $AX1.L, #0x0008 // length
|
||||
01af 0087 0000 lri $IX3, #0x0000 // there will be no iram dma
|
||||
01b1 02bf 808b call 0x808b // dram->cpu <<<--- important!!
|
||||
01b3 02df ret
|
||||
}
|
||||
|
||||
01b4 0000 nop
|
||||
01b5 0000 nop
|
||||
01b6 0000 nop
|
||||
01b7 0000 nop
|
||||
01b8 0000 nop
|
||||
01b9 0000 nop
|
||||
01ba 0000 nop
|
||||
01bb 0000 nop
|
||||
01bc 0000 nop
|
||||
01bd 0000 nop
|
||||
01be 0000 nop
|
||||
01bf 0000 nop
|
||||
/*
|
||||
ROM functions used:
|
||||
0x8000 dsp reset
|
||||
0x8078 wait for CMBH & 0x8000
|
||||
0x807e wait for DMBH & 0x8000
|
||||
0x808b dump DRAM/IRAM to mainmem
|
||||
0x80b5 boot new ucode
|
||||
0x80bc boot new ucode without ACC clearing by ROM
|
||||
|
||||
For the rest, this ucode is just calling the last few instructions
|
||||
from huge functions in ROM - some kind of obfuscation?
|
||||
|
||||
0x81f4
|
||||
81f4 b51e mulxac'mv $AX0.H, $AX1.L, $ACC1 : $AX1.H, $AC0.M
|
||||
81f5 9909 asr16'ir $ACC1 : $AR1
|
||||
81f6 1b7f srri @$AR3, $AC1.M
|
||||
81f7 812b clr's $ACC0 : @$AR3, $AC1.L
|
||||
0x8458
|
||||
8458 b51e mulxac'mv $AX0.H, $AX1.L, $ACC1 : $AX1.H, $AC0.M
|
||||
8459 9900 asr16 $ACC1
|
||||
845a 1b7f srri @$AR3, $AC1.M
|
||||
845b 812b clr's $ACC0 : @$AR3, $AC1.L
|
||||
0x8723
|
||||
8723 3300 xorr $AC1.M, $AX1.H
|
||||
8724 1adf srrd @$AR2, $AC1.M
|
||||
0x8809
|
||||
8809 392e orr'sn $AC1.M, $AX0.H : @$AR2, $AC1.L
|
||||
880a 1b5f srri @$AR2, $AC1.M
|
||||
0x88e5
|
||||
88e5 387a orr'l $AC0.M, $AX0.H : $AC1.M, @$AR2
|
||||
88e6 18dd lrrd $AC1.L, @$AR2
|
||||
88e7 4c05 add'dr $ACC0, $ACC1 : $AR1
|
||||
88e8 1b5e srri @$AR2, $AC0.M
|
||||
88e9 1a5c srr @$AR2, $AC0.L
|
||||
*/
|
||||
|
||||
0000 0000 nop
|
||||
0001 0000 nop
|
||||
0002 0000 nop
|
||||
0003 0000 nop
|
||||
0004 0000 nop
|
||||
0005 0000 nop
|
||||
0006 0000 nop
|
||||
0007 0000 nop
|
||||
0008 0000 nop
|
||||
0009 0000 nop
|
||||
000a 0000 nop
|
||||
000b 0000 nop
|
||||
000c 0000 nop
|
||||
000d 0021 halt
|
||||
000e 02ff rti
|
||||
000f 0021 halt
|
||||
|
||||
0010 1306 sbset #0x06
|
||||
0011 1203 sbclr #0x03
|
||||
0012 1204 sbclr #0x04
|
||||
0013 1305 sbset #0x05
|
||||
0014 0092 00ff lri $CR, #0x00ff
|
||||
0016 0088 ffff lri $WR0, #0xffff
|
||||
0018 0089 ffff lri $WR1, #0xffff
|
||||
001a 008a ffff lri $WR2, #0xffff
|
||||
001c 008b ffff lri $WR3, #0xffff
|
||||
001e 8f00 set40
|
||||
001f 8b00 m0
|
||||
0020 8c00 clr15
|
||||
0021 02bf 807e call 0x807e // loop until dsp->cpu mailbox is empty
|
||||
0023 16fc dcd1 si @DMBH, #0xdcd1
|
||||
0025 16fd 0000 si @DMBL, #0x0000 // sendmail 0xdcd10000
|
||||
0027 16fb 0001 si @DIRQ, #0x0001
|
||||
|
||||
// wait for cpu mail == 0xabbaxxxx
|
||||
0029 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
002b 24ff lrs $AC0.L, @CMBL
|
||||
002c 0280 abba cmpi $AC0.M, #0xabba
|
||||
002e 0294 0029 jnz 0x0029
|
||||
|
||||
// wait for cpu mail
|
||||
0030 8e00 set16
|
||||
0031 02bf 8078 call 0x8078
|
||||
|
||||
0033 20ff lrs $AX0.L, @CMBL
|
||||
0034 0240 0fff andi $AC0.M, #0x0fff
|
||||
0036 1f5e mrr $AX0.H, $AC0.M
|
||||
0037 009b 0000 lri $AX1.H, #0x0000 // DSP-dram addr
|
||||
0039 0099 0020 lri $AX1.L, #0x0020 // length (20 bytes = 10 words, word 9 and 10 are addr where result should DMA'd to in main mem)
|
||||
003b 0087 0000 lri $IX3, #0x0000 // there will be no ucode/iram upload
|
||||
003d 0080 0041 lri $AR0, #0x0041 // return addr after dram upload
|
||||
003f 029f 80bc jmp 0x80bc // DRAM upload !!
|
||||
// $AX0.H-$AX0.L - CPU(PPC) addr = mail & 0x0fffffff
|
||||
// upload data from mainmem do dsp dram and jump to 0x41 after that
|
||||
|
||||
0041 02bf 008c call 008c_BigCrazyFunction() // <<------------- main crap is here!!!!!!!!!
|
||||
0043 02bf 807e call 0x807e // loop until dsp->cpu mailbox is empty
|
||||
|
||||
0045 16fc dcd1 si @DMBH, #0xdcd1
|
||||
0047 16fd 0003 si @DMBL, #0x0003 // sendmail 0xdcd10003 (aka... calc is over, result is in main mem now)
|
||||
0049 16fb 0001 si @DIRQ, #0x0001
|
||||
004b 8f00 set40
|
||||
|
||||
004c 02bf 8078 call 0x8078
|
||||
004e 0280 cdd1 cmpi $AC0.M, #0xcdd1
|
||||
0050 0294 004c jnz 0x004c
|
||||
|
||||
0052 26ff lrs $AC0.M, @CMBL
|
||||
0053 0280 0001 cmpi $AC0.M, #0x0001
|
||||
0055 0295 005e jz 0x005e // if cpu->dsp mail was 0xcdd10001 -> 005e_PrepareBootUcode()
|
||||
|
||||
0057 0280 0002 cmpi $AC0.M, #0x0002
|
||||
0059 0295 8000 jz 0x8000 // if cpu->dsp mail was 0xcdd10002 -> dsp reset ( jmp to irom(0x8000))
|
||||
|
||||
005b 029f 004c jmp 0x004c // wait for next mail from cpu
|
||||
005d 0021 halt
|
||||
|
||||
void 005e_PrepareBootUcode()
|
||||
{
|
||||
005e 8e00 set16
|
||||
005f 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
0061 24ff lrs $AC0.L, @CMBL
|
||||
0062 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
0064 24ff lrs $AC0.L, @CMBL
|
||||
0065 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
0067 24ff lrs $AC0.L, @CMBL
|
||||
0068 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
006a 00c5 ffff lr $IX1, @CMBL
|
||||
006c 0240 0fff andi $AC0.M, #0x0fff
|
||||
006e 1c9e mrr $IX0, $AC0.M
|
||||
006f 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
0071 00c7 ffff lr $IX3, @CMBL
|
||||
0073 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
0075 00c6 ffff lr $IX2, @CMBL
|
||||
0077 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
0079 00c0 ffff lr $AR0, @CMBL
|
||||
007b 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
007d 20ff lrs $AX0.L, @CMBL
|
||||
007e 0240 0fff andi $AC0.M, #0x0fff
|
||||
0080 1f5e mrr $AX0.H, $AC0.M
|
||||
0081 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
0083 21ff lrs $AX1.L, @CMBL
|
||||
0084 02bf 8078 call 0x8078 // wait for cpu mail
|
||||
0086 23ff lrs $AX1.H, @CMBL
|
||||
0087 1205 sbclr #0x05
|
||||
0088 1206 sbclr #0x06
|
||||
0089 029f 80b5 jmp 80b5_BootUcode()
|
||||
008b 0021 halt
|
||||
}
|
||||
|
||||
// does some crazy stuff with data at dram @0x3/0x5/0x6/0x7 with help of some values from drom :)
|
||||
// result is @0x22,@0x23 and written back to main memory to dmem-0x08:dmem-0x09
|
||||
void 008c_BigCrazyFunction()
|
||||
{
|
||||
008c 8100 clr $ACC0
|
||||
008d 0081 0010 lri $AR1, #0x0010
|
||||
008f 1020 loopi #0x20
|
||||
0090 1b3e srri @$AR1, $AC0.M
|
||||
0091 00df 1456 lr $AC1.M, @0x1456
|
||||
0093 0340 ffd0 andi $AC1.M, #0xffd0
|
||||
0095 8417 clrp'mv : $AX1.L, $AC1.M
|
||||
0096 0080 0000 lri $AR0, #0x0000
|
||||
0098 0086 0000 lri $IX2, #0x0000
|
||||
009a 0082 001f lri $AR2, #0x001f
|
||||
009c 00de 15f6 lr $AC0.M, @0x15f6
|
||||
009e 1408 lsl $ACC0, #8
|
||||
009f 00df 1766 lr $AC1.M, @0x1766
|
||||
00a1 0340 00ff andi $AC1.M, #0x00ff
|
||||
00a3 1f5f mrr $AX0.H, $AC1.M
|
||||
00a4 02bf 88e5 call 0x88e5
|
||||
88e5 387a orr'l $AC0.M, $AX0.H : $AC1.M, @$AR2
|
||||
88e6 18dd lrrd $AC1.L, @$AR2
|
||||
88e7 4c05 add'dr $ACC0, $ACC1 : $AR1
|
||||
88e8 1b5e srri @$AR2, $AC0.M
|
||||
88e9 1a5c srr @$AR2, $AC0.L
|
||||
00a6 1f1c mrr $AX0.L, $AC0.L
|
||||
00a7 811e clr'mv $ACC0 : $AX1.H, $AC0.M
|
||||
00a8 191e lrri $AC0.M, @$AR0
|
||||
00a9 1478 lsr $ACC0, #-8
|
||||
00aa 1ffc mrr $AC1.M, $AC0.L
|
||||
00ab 1f5e mrr $AX0.H, $AC0.M
|
||||
00ac 02bf 8809 call 0x8809
|
||||
8809 392e orr'sn $AC1.M, $AX0.H : @$AR2, $AC1.L
|
||||
880a 1b5f srri @$AR2, $AC1.M
|
||||
00ae 02bf 8723 call 0x8723
|
||||
8723 3300 xorr $AC1.M, $AX1.H
|
||||
8724 1adf srrd @$AR2, $AC1.M
|
||||
00b0 0006 dar $AR2
|
||||
00b1 8106 clr'dr $ACC0 : $AR2
|
||||
00b2 00de 166c lr $AC0.M, @0x166c
|
||||
00b4 1404 lsl $ACC0, #4
|
||||
00b5 0240 ff00 andi $AC0.M, #0xff00
|
||||
00b7 00df 1231 lr $AC1.M, @0x1231
|
||||
00b9 1578 lsr $ACC1, #-8
|
||||
00ba 0340 00ff andi $AC1.M, #0x00ff
|
||||
00bc 1f5f mrr $AX0.H, $AC1.M
|
||||
00bd 02bf 88e5 call 0x88e5
|
||||
88e5 387a orr'l $AC0.M, $AX0.H : $AC1.M, @$AR2
|
||||
88e6 18dd lrrd $AC1.L, @$AR2
|
||||
88e7 4c05 add'dr $ACC0, $ACC1 : $AR1
|
||||
88e8 1b5e srri @$AR2, $AC0.M
|
||||
88e9 1a5c srr @$AR2, $AC0.L
|
||||
00bf 1f1c mrr $AX0.L, $AC0.L
|
||||
00c0 811e clr'mv $ACC0 : $AX1.H, $AC0.M
|
||||
00c1 191e lrri $AC0.M, @$AR0
|
||||
00c2 1478 lsr $ACC0, #-8
|
||||
00c3 1ffc mrr $AC1.M, $AC0.L
|
||||
00c4 1f5e mrr $AX0.H, $AC0.M
|
||||
00c5 02bf 8809 call 0x8809
|
||||
8809 392e orr'sn $AC1.M, $AX0.H : @$AR2, $AC1.L
|
||||
880a 1b5f srri @$AR2, $AC1.M
|
||||
00c7 02bf 8723 call 0x8723
|
||||
8723 3300 xorr $AC1.M, $AX1.H
|
||||
8724 1adf srrd @$AR2, $AC1.M
|
||||
00c9 8100 clr $ACC0
|
||||
00ca 8900 clr $ACC1
|
||||
00cb 00d1 0005 lr $AC1.H, @0x0005
|
||||
00cd 9900 asr16 $ACC1
|
||||
00ce 8200 cmp
|
||||
00cf 0295 00e5 jz 0x00e5
|
||||
|
||||
00d1 0291 00f3 jl 0x00f3
|
||||
|
||||
00d3 0082 0010 lri $AR2, #0x0010
|
||||
00d5 0086 0001 lri $IX2, #0x0001
|
||||
00d7 00d0 171b lr $AC0.H, @0x171b
|
||||
00d9 9100 asr16 $ACC0
|
||||
00da 7d00 neg $ACC1
|
||||
00db 4d00 add $ACC1, $ACC0
|
||||
00dc 1501 lsl $ACC1, #1
|
||||
00dd 1f5f mrr $AX0.H, $AC1.M
|
||||
00de 00df 0003 lr $AC1.M, @0x0003
|
||||
00e0 1504 lsl $ACC1, #4
|
||||
00e1 02bf 8809 call 0x8809
|
||||
8809 392e orr'sn $AC1.M, $AX0.H : @$AR2, $AC1.L
|
||||
880a 1b5f srri @$AR2, $AC1.M
|
||||
00e3 029f 0102 jmp 0x0102
|
||||
|
||||
:
|
||||
00e5 0082 0011 lri $AR2, #0x0011
|
||||
00e7 00df 0003 lr $AC1.M, @0x0003
|
||||
00e9 1501 lsl $ACC1, #1
|
||||
00ea 1f5f mrr $AX0.H, $AC1.M
|
||||
00eb 00de 1043 lr $AC0.M, @0x1043
|
||||
00ed 0240 fff0 andi $AC0.M, #0xfff0
|
||||
00ef 02bf 88e5 call 0x88e5
|
||||
88e5 387a orr'l $AC0.M, $AX0.H : $AC1.M, @$AR2
|
||||
88e6 18dd lrrd $AC1.L, @$AR2
|
||||
88e7 4c05 add'dr $ACC0, $ACC1 : $AR1
|
||||
88e8 1b5e srri @$AR2, $AC0.M
|
||||
88e9 1a5c srr @$AR2, $AC0.L
|
||||
00f1 029f 0102 jmp 0x0102
|
||||
|
||||
:
|
||||
00f3 0082 0010 lri $AR2, #0x0010
|
||||
00f5 0086 0001 lri $IX2, #0x0001
|
||||
00f7 00d0 1285 lr $AC0.H, @0x1285
|
||||
00f9 9100 asr16 $ACC0
|
||||
00fa 4d00 add $ACC1, $ACC0
|
||||
00fb 1501 lsl $ACC1, #1
|
||||
00fc 00de 0003 lr $AC0.M, @0x0003
|
||||
00fe 1404 lsl $ACC0, #4
|
||||
00ff 1f5e mrr $AX0.H, $AC0.M
|
||||
0100 02bf 8809 call 0x8809
|
||||
8809 392e orr'sn $AC1.M, $AX0.H : @$AR2, $AC1.L
|
||||
880a 1b5f srri @$AR2, $AC1.M
|
||||
|
||||
:
|
||||
0102 0083 0013 lri $AR3, #0x0013
|
||||
0104 1b7e srri @$AR3, $AC0.M
|
||||
0105 8923 clr's $ACC1 : @$AR3, $AC0.L
|
||||
0106 0083 0013 lri $AR3, #0x0013
|
||||
0108 00df 0007 lr $AC1.M, @0x0007
|
||||
010a 00de 11b8 lr $AC0.M, @0x11b8
|
||||
010c 0240 fff0 andi $AC0.M, #0xfff0
|
||||
010e 1f5e mrr $AX0.H, $AC0.M
|
||||
010f 02bf 81f4 call 0x81f4
|
||||
81f4 b51e mulxac'mv $AX0.H, $AX1.L, $ACC1 : $AX1.H, $AC0.M
|
||||
81f5 9909 asr16'ir $ACC1 : $AR1
|
||||
81f6 1b7f srri @$AR3, $AC1.M
|
||||
81f7 812b clr's $ACC0 : @$AR3, $AC1.L
|
||||
0111 f100 lsl16 $ACC1
|
||||
0112 02bf 8458 call 0x8458
|
||||
8458 b51e mulxac'mv $AX0.H, $AX1.L, $ACC1 : $AX1.H, $AC0.M
|
||||
8459 9900 asr16 $ACC1
|
||||
845a 1b7f srri @$AR3, $AC1.M
|
||||
845b 812b clr's $ACC0 : @$AR3, $AC1.L
|
||||
0114 8f00 set40
|
||||
0115 0082 0015 lri $AR2, #0x0015
|
||||
0117 00de 0006 lr $AC0.M, @0x0006
|
||||
0119 00da 165b lr $AX0.H, @0x165b
|
||||
011b 02bf 88e5 call 0x88e5
|
||||
88e5 387a orr'l $AC0.M, $AX0.H : $AC1.M, @$AR2
|
||||
88e6 18dd lrrd $AC1.L, @$AR2
|
||||
88e7 4c05 add'dr $ACC0, $ACC1 : $AR1
|
||||
88e8 1b5e srri @$AR2, $AC0.M
|
||||
88e9 1a5c srr @$AR2, $AC0.L
|
||||
011d 14fd asr $ACC0, #-3
|
||||
011e 1403 lsl $ACC0, #3
|
||||
011f 1b5e srri @$AR2, $AC0.M
|
||||
0120 1b5c srri @$AR2, $AC0.L
|
||||
0121 0082 0016 lri $AR2, #0x0016
|
||||
0123 00de 1723 lr $AC0.M, @0x1723
|
||||
0125 14f4 asr $ACC0, #-12
|
||||
0126 00da 166b lr $AX0.H, @0x166b
|
||||
0128 02bf 88e5 call 0x88e5
|
||||
88e5 387a orr'l $AC0.M, $AX0.H : $AC1.M, @$AR2
|
||||
88e6 18dd lrrd $AC1.L, @$AR2
|
||||
88e7 4c05 add'dr $ACC0, $ACC1 : $AR1
|
||||
88e8 1b5e srri @$AR2, $AC0.M
|
||||
88e9 1a5c srr @$AR2, $AC0.L
|
||||
012a b100 tst $ACC0
|
||||
012b 0290 012e jge 0x012e
|
||||
|
||||
012d 8100 clr $ACC0
|
||||
|
||||
:
|
||||
012e 14fd asr $ACC0, #-3
|
||||
012f 8e00 set16
|
||||
0130 00df 1491 lr $AC1.M, @0x1491
|
||||
0132 0340 d0f0 andi $AC1.M, #0xd0f0
|
||||
0134 1cbf mrr $IX1, $AC1.M
|
||||
0135 00df 1468 lr $AC1.M, @0x1468
|
||||
0137 00d1 11fc lr $AC1.H, @0x11fc
|
||||
0139 157c lsr $ACC1, #-4
|
||||
013a 1cdf mrr $IX2, $AC1.M
|
||||
013b 00d1 11b8 lr $AC1.H, @0x11b8
|
||||
013d 9900 asr16 $ACC1
|
||||
013e 1418 lsl $ACC0, #24
|
||||
013f 1478 lsr $ACC0, #-8
|
||||
0140 1f5e mrr $AX0.H, $AC0.M
|
||||
0141 1ffe mrr $AC1.M, $AC0.M
|
||||
0142 1f65 mrr $AX1.H, $IX1
|
||||
0143 3600 andr $AC0.M, $AX1.H
|
||||
0144 1402 lsl $ACC0, #2
|
||||
0145 1f66 mrr $AX1.H, $IX2
|
||||
0146 3700 andr $AC1.M, $AX1.H
|
||||
0147 1501 lsl $ACC1, #1
|
||||
0148 4c00 add $ACC0, $ACC1
|
||||
0149 1518 lsl $ACC1, #24
|
||||
014a 9900 asr16 $ACC1
|
||||
014b 3500 andr $AC1.M, $AX0.H
|
||||
014c 4c00 add $ACC0, $ACC1
|
||||
014d 00df 0012 lr $AC1.M, @0x0012
|
||||
014f 3f00 orc $AC1.M, $AC0.M
|
||||
0150 00ff 0012 sr @0x0012, $AC1.M
|
||||
0152 1470 lsr $ACC0, #-16
|
||||
0153 00df 0011 lr $AC1.M, @0x0011
|
||||
0155 3f00 orc $AC1.M, $AC0.M
|
||||
0156 00ff 0011 sr @0x0011, $AC1.M
|
||||
0158 1fa5 mrr $AC1.L, $IX1
|
||||
0159 1501 lsl $ACC1, #1
|
||||
015a 1fe6 mrr $AC1.M, $IX2
|
||||
015b f100 lsl16 $ACC1
|
||||
015c 15f8 asr $ACC1, #-8
|
||||
015d f500 lsr16 $ACC1
|
||||
015e 1f5f mrr $AX0.H, $AC1.M
|
||||
015f 1f7d mrr $AX1.H, $AC1.L
|
||||
0160 8100 clr $ACC0
|
||||
0161 00de 0011 lr $AC0.M, @0x0011
|
||||
0163 3400 andr $AC0.M, $AX0.H
|
||||
0164 8900 clr $ACC1
|
||||
0165 00df 0012 lr $AC1.M, @0x0012
|
||||
0167 3500 andr $AC1.M, $AX0.H
|
||||
0168 4c00 add $ACC0, $ACC1
|
||||
0169 00df 0012 lr $AC1.M, @0x0012
|
||||
016b 1578 lsr $ACC1, #-8
|
||||
016c 4c00 add $ACC0, $ACC1
|
||||
016d 8900 clr $ACC1
|
||||
016e 1ffe mrr $AC1.M, $AC0.M
|
||||
016f 1508 lsl $ACC1, #8
|
||||
0170 3b00 orr $AC1.M, $AX1.H
|
||||
0171 00de 0011 lr $AC0.M, @0x0011
|
||||
0173 3e00 orc $AC0.M, $AC1.M
|
||||
0174 00df 0012 lr $AC1.M, @0x0012
|
||||
0176 3b00 orr $AC1.M, $AX1.H
|
||||
0177 1cbf mrr $IX1, $AC1.M
|
||||
0178 00da 15f1 lr $AX0.H, @0x15f1
|
||||
017a 3500 andr $AC1.M, $AX0.H
|
||||
017b 0295 0192 jz 0x0192
|
||||
if () {
|
||||
|
||||
017d 00df 10e2 lr $AC1.M, @0x10e2
|
||||
017f 1508 lsl $ACC1, #8
|
||||
0180 1f5f mrr $AX0.H, $AC1.M
|
||||
0181 00df 103b lr $AC1.M, @0x103b
|
||||
0183 7900 decm $AC1.M
|
||||
0184 3900 orr $AC1.M, $AX0.H
|
||||
0185 3080 xorc $AC0.M, $AC1.M
|
||||
0186 00fe 0022 sr @0x0022, $AC0.M
|
||||
0188 00dc 1229 lr $AC0.L, @0x1229
|
||||
018a 00dd 11f8 lr $AC1.L, @0x11f8
|
||||
018c 5c00 sub $ACC0, $ACC1
|
||||
018d f000 lsl16 $ACC0
|
||||
018e 1fe5 mrr $AC1.M, $IX1
|
||||
018f 3080 xorc $AC0.M, $AC1.M
|
||||
0190 029f 01a5 jmp 0x01a5
|
||||
|
||||
} else {
|
||||
|
||||
0192 00df 10ca lr $AC1.M, @0x10ca
|
||||
0194 1508 lsl $ACC1, #8
|
||||
0195 1f5f mrr $AX0.H, $AC1.M
|
||||
0196 00df 1043 lr $AC1.M, @0x1043
|
||||
0198 7500 incm $AC1.M
|
||||
0199 3900 orr $AC1.M, $AX0.H
|
||||
019a 3080 xorc $AC0.M, $AC1.M
|
||||
019b 00fe 0022 sr @0x0022, $AC0.M
|
||||
019d 00dc 1259 lr $AC0.L, @0x1259
|
||||
019f 00dd 16fe lr $AC1.L, @0x16fe
|
||||
01a1 4c00 add $ACC0, $ACC1
|
||||
01a2 f000 lsl16 $ACC0
|
||||
01a3 1fe5 mrr $AC1.M, $IX1
|
||||
01a4 3080 xorc $AC0.M, $AC1.M
|
||||
}
|
||||
|
||||
01a5 00fe 0023 sr @0x0023, $AC0.M
|
||||
// this is where result is written to main memory
|
||||
// dsp mem 0x20-0x23 (8 bytes) are written back, because only values @22 and @23 were modified result is 32bit
|
||||
01a7 00da 0008 lr $AX0.H, @0x0008 // cpu addr high
|
||||
01a9 00d8 0009 lr $AX0.L, @0x0009 // cpu addr low
|
||||
01ab 009b 0020 lri $AX1.H, #0x0020 // dsp addr
|
||||
01ad 0099 0008 lri $AX1.L, #0x0008 // length
|
||||
01af 0087 0000 lri $IX3, #0x0000 // there will be no iram dma
|
||||
01b1 02bf 808b call 0x808b // dram->cpu <<<--- important!!
|
||||
01b3 02df ret
|
||||
}
|
||||
|
||||
01b4 0000 nop
|
||||
01b5 0000 nop
|
||||
01b6 0000 nop
|
||||
01b7 0000 nop
|
||||
01b8 0000 nop
|
||||
01b9 0000 nop
|
||||
01ba 0000 nop
|
||||
01bb 0000 nop
|
||||
01bc 0000 nop
|
||||
01bd 0000 nop
|
||||
01be 0000 nop
|
||||
01bf 0000 nop
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
844
docs/DSP/wwdsp.c
844
docs/DSP/wwdsp.c
@ -1,423 +1,423 @@
|
||||
/* important variables */
|
||||
short mem[0x1000];
|
||||
#define v_0341 mem[0x0341] /* op#2 saves a copy of 344 here */
|
||||
#define v_0343 mem[0x0343] /* message type? */
|
||||
#define v_0344 mem[0x0344] /* low byte of first word of message */
|
||||
#define v_0345 mem[0x0345] /* copy of second word of message */
|
||||
#define a_0346 mem[0x0346] /* buffer for message contents, size unknown */
|
||||
#define v_034e mem[0x034e] /* init to 0, later set to most recent value written in a_04fc */
|
||||
|
||||
#define v_0350 mem[0x0350] /* init to 0x0280 (write location of messages) */
|
||||
#define v_0351 mem[0x0351] /* init to 0x0280 (read location?) */
|
||||
#define v_0352 mem[0x0352] /* init to 0 (number of messages pending?) */
|
||||
#define v_0355 mem[0x0355] /* used by op#2, init to 0 */
|
||||
#define a_0356 (mem+0x0356) /* message contents */
|
||||
|
||||
#define a_0388 (mem+0x388) /* where op 2 keeps its message */
|
||||
#define a_038e (mem+0x38e) /* op#2 saves a copy of 345 here */
|
||||
|
||||
#define a_03a8 (mem+0x3a8) /* where op#2 dmas in its data, at least 0x80 */
|
||||
|
||||
#define v_03fa mem[0x03fa] /* temp for ax0.h during exception */
|
||||
#define v_03fb mem[0x03fb] /* temp for ar0 during exception */
|
||||
#define v_03fc mem[0x03fc] /* temp for r08 during exception */
|
||||
#define v_03fd mem[0x03fd] /* temp for ac0.h during exception */
|
||||
#define v_03fe mem[0x03fe] /* temp for ac0.m during exception */
|
||||
#define v_03ff mem[0x03ff] /* temp for ac0.l during exception */
|
||||
|
||||
#define a_04e8 (mem+0x04e8) /* 4 element array */
|
||||
#define a_04ec (mem+0x04ec) /* 4 element array (empty) */
|
||||
#define a_04f0 (mem+0x04f0) /* 4 element array */
|
||||
#define a_04f4 (mem+0x04f4) /* 4 element array (empty) */
|
||||
#define a_04fc (mem+0x04fc) /* 16 element array, written by messages */
|
||||
#define a_09a0 (mem+0x09a0) /* 0x50 element array, used by op#2, cleared */
|
||||
#define a_0a00 (mem+0x0a00) /* 0x50 element array, used by op#2, cleared */
|
||||
#define a_0b00 (mem+0x0b00) /* array from 0x0b00-0x0bff, involves accelerator? */
|
||||
#define a_0ca0 (mem+0x0ca0) /* 0x50 element array, used by op#2, cleared */
|
||||
#define a_0d00 (mem+0x0d00) /* 0x50 element array, used by op#2, cleared */
|
||||
#define a_0d60 (mem+0x0d60) /* 0x50 element array, used by op#2, cleared */
|
||||
#define a_0f40 (mem+0x0f40) /* 0x50 element array, used by op#2, cleared */
|
||||
|
||||
|
||||
|
||||
/* reset exception vector 0x0000 */
|
||||
void main() {
|
||||
/* JMP 0x0012 */
|
||||
/* various inits */
|
||||
SBCLR(5); /* disable interrupts? */
|
||||
fcn_0057(); /* init hardware stuff */
|
||||
for(ac1.m=0x1000,ac0.m=0;ac1.m>0;ac1.m--) mem[ac0.m++]=0; /* clear all vars */
|
||||
fcn_0688(); /* init some vars */
|
||||
fcn_04c0(); /* set something up related to the accelerator at a_0b00 */
|
||||
fcn_0e14(); /* set up a table */
|
||||
fcn_066a(0); /* send a message */
|
||||
fcn_0674(0x1111); /* send a message */
|
||||
v_034e=0;
|
||||
SBSET(5); /* enable interrupts? */
|
||||
|
||||
/* jump to 0x06c5 */
|
||||
mainloop:
|
||||
while (v_0352) ; /* while no messages pending */
|
||||
|
||||
SBCLR(5); /* do not distrub */
|
||||
v_0352--; /* important that this be atomic */
|
||||
SBSET(5);
|
||||
|
||||
t=v_0351;
|
||||
size=mem[t++];
|
||||
if (!(size&0x8000)) { /* size > 0x7fff invalid */
|
||||
if (size==0) { /* die on message of length 0? */
|
||||
/* jump to 0x06f5 */
|
||||
/* jump to 0x05f0 */
|
||||
|
||||
/* TODO: analysis of HALT */
|
||||
HALT();
|
||||
}
|
||||
for (i=size,j=0;i>0;i--) {
|
||||
a_0356[j++]=mem[t++];
|
||||
a_0356[j++]=mem[t++];
|
||||
}
|
||||
v_0351=t;
|
||||
|
||||
/* jump to 0x002f */
|
||||
/* actual command handling */
|
||||
v_0345=a_0356[1];
|
||||
v_0344=a_0356[0]&0x00ff;
|
||||
v_0343=(a_0346[0]>>7)&0x7e;
|
||||
|
||||
/* jump table at 0x75 used here */
|
||||
switch (v_0343>>1) {
|
||||
|
||||
// 0x43
|
||||
case 0:
|
||||
case 10:
|
||||
case 11:
|
||||
case 12:
|
||||
case 14:
|
||||
case 15:
|
||||
/* invalid command? */
|
||||
config=0x00ff;
|
||||
fcn_066a(0x04); /* send off a message */
|
||||
fcn_0674(a_0356[0]); /* send first word of command as a message */
|
||||
goto mainloop;
|
||||
break;
|
||||
case 1:
|
||||
/* jmp 0x0095 */
|
||||
break;
|
||||
|
||||
case 2:
|
||||
/* jmp 0x0243 */
|
||||
sub_0243();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
/* jmp 0x0073 */
|
||||
break;
|
||||
|
||||
case 4:
|
||||
/* jmp 0x580 */
|
||||
break;
|
||||
|
||||
case 5:
|
||||
/* jmp 0x592 */
|
||||
break;
|
||||
|
||||
case 6:
|
||||
/* jmp 0x469 */
|
||||
break;
|
||||
|
||||
case 7:
|
||||
/* jmp 0x41d */
|
||||
break;
|
||||
|
||||
case 8: /* mix */
|
||||
/* jmp 0x0485 */
|
||||
fcn_0067(fcn_0067(0x0346)); /* read message twice? */
|
||||
/* take in the two buffers to mix */
|
||||
fcn_0525(mem[0x344],mem[0x346],mem[0x347],0x400); /* size, addrH, addrL, dsp addr */
|
||||
fcn_0525(mem[0x344],mem[0x348],mem[0x349],0x800);
|
||||
S16(); /* saturate all adds, multiplies to 16 bits? */
|
||||
|
||||
i=mem[0x0344];
|
||||
src1=0x400;
|
||||
src2=0x800;
|
||||
scale=mem[0x345];
|
||||
|
||||
prod=scale*mem[src2++];
|
||||
val2=mem[src2++];
|
||||
do {
|
||||
val1=mem[src1];
|
||||
val1+=prod;
|
||||
prod=scale*val2;
|
||||
mem[src1]=val1;
|
||||
val2=mem[src2];
|
||||
src1++;
|
||||
src2++;
|
||||
} while (--i);
|
||||
|
||||
S40();
|
||||
|
||||
/* dma out mixed buf */
|
||||
fcn_0523(mem[0x344],mem[0x346],mem[0x347],0x400);
|
||||
|
||||
break;
|
||||
|
||||
case 9:
|
||||
/* jmp 0x44d */
|
||||
break;
|
||||
|
||||
case 13:
|
||||
/* jmp 0x00b2 */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
v_0351=t;
|
||||
|
||||
goto mainloop;
|
||||
}
|
||||
|
||||
/* message in MBOX exception vector? 0x000e */
|
||||
void exception() {
|
||||
/* JMP 0x05b8 */
|
||||
|
||||
SBCLR(5);
|
||||
S40();
|
||||
/* save ax0.h,ac0.h,ac0.m, and ac0.l */
|
||||
|
||||
if ((tH=register_fffe)&0x8000) { /* CPU mailbox H */
|
||||
if (!(tsize=register_ffff)) { /* CPU mailbox L */
|
||||
/* empty message? */
|
||||
while (!((tH=register_fffe)&0x8000)) ;
|
||||
tH&=0xf;
|
||||
v_034e=(tH+1)<<4;
|
||||
a_04fc[tH]=register_ffff;
|
||||
} else { /* nonempty message? */
|
||||
/* jump to 0x0692 */
|
||||
/* save ar0, r08 */
|
||||
t=v_0350;
|
||||
mem[t++]=tsize;
|
||||
|
||||
do {
|
||||
while (!((tH=register_fffe)&0x8000)) ;
|
||||
mem[t++]=tH;
|
||||
mem[t++]=register_ffff;
|
||||
} while (--tsize);
|
||||
|
||||
v_0350=t;
|
||||
v_0352++;
|
||||
/* restore ar0, r08 */
|
||||
|
||||
/* jump to 0x05e6 */
|
||||
}
|
||||
} else { /* interrupt without message? */
|
||||
/* jump to 0x06b9 */
|
||||
/* save ar0, r08 */
|
||||
mem[v_0350]=0; /* empty message */
|
||||
/* jump to 0x06ab */
|
||||
v_0350++;
|
||||
v_0352++;
|
||||
/* restore ar0, r08 */
|
||||
|
||||
/* jump to 0x05e6 */
|
||||
}
|
||||
|
||||
/* 0x05e6 */
|
||||
|
||||
/* restore ax0.h,ac0.h,ac0.m, and ac0.l */
|
||||
SBSET(5);
|
||||
/* RTI */
|
||||
}
|
||||
|
||||
/* set up some registers */
|
||||
void fcn_0057() {
|
||||
SBCLR(2);
|
||||
SBCLR(3);
|
||||
SBCLR(4);
|
||||
SBCLR(6);
|
||||
S40(); /* 40-bit mode */
|
||||
CLR15();
|
||||
M0(); /* don't multiply result by 2 */
|
||||
r08=-1;
|
||||
r09=-1;
|
||||
r0a=-1;
|
||||
r0b=-1;
|
||||
config=0xff;
|
||||
}
|
||||
|
||||
void fcn_0688() {
|
||||
v_0350=0x0280;
|
||||
v_0351=0x0280;
|
||||
v_0352=0;
|
||||
}
|
||||
|
||||
void fcn_04c0() {
|
||||
config=0xff;
|
||||
for(i=0xff,ar0=0xb00;i>0;i--) mem[ar0++]=0;
|
||||
mem[ar0++]=0; /* get the last one */
|
||||
fcn_0573(0x0b00,0x0100,0);
|
||||
}
|
||||
|
||||
/* a=an address in ac1.m, l=a length in ar0, v=a value? in ac0.m */
|
||||
void fcn_0573(short a, short l, short v) {
|
||||
fcn_0561(a,l,0x0001);
|
||||
}
|
||||
|
||||
/* a=an address in ac1.m, l=a length in ar0, v=a value? in ac0.m, f is a flag? in ac0.h */
|
||||
/* return is in ax0.h */
|
||||
short fcn_0561(short a, short l, short v, short f) {
|
||||
register_ffd1=0x0a; /* unknown reg, accel? */
|
||||
register_ffd6=-1; /* accel end addr H */
|
||||
register_ffd7=-1; /* accel end addr L */
|
||||
register_ffd8=v>>1; /*
|
||||
register_ffd9=?; /* has a value from way back? */
|
||||
|
||||
return f;
|
||||
}
|
||||
|
||||
/* initializes some tables that look useful... */
|
||||
void fcn_0e14() {
|
||||
a_04e8[0]=0x8240;
|
||||
a_04e8[1]=0x7fff;
|
||||
a_04e8[2]=0x7dbf;
|
||||
a_04e8[3]=0x843f;
|
||||
a_04f0[0]=0xb23b;
|
||||
a_04f0[1]=0x7fff;
|
||||
a_04f0[2]=0x4dc4;
|
||||
a_04f0[3]=0xd808;
|
||||
a_04ec[0]=a_04ec[1]=a_04ec[2]=a_04ec[3]=0;
|
||||
a_04f4[0]=a_04f4[1]=a_04f4[2]=a_04f4[3]=0;
|
||||
}
|
||||
|
||||
/* send a message via DSP MBOX */
|
||||
void fcn_066a(short m) {
|
||||
fcn_0682(); /* wait for empty mbox */
|
||||
register_fffc=0xdcd1;
|
||||
register_fffd=m;
|
||||
register_fffb=1; /* IRQ */
|
||||
fcn_0682();
|
||||
}
|
||||
|
||||
/* wait for dsp mbox empty */
|
||||
void fcn_0682() {
|
||||
while (register_fffc&0x8000);
|
||||
}
|
||||
|
||||
void fcn_0674(short m) {
|
||||
fcn_0682();
|
||||
register_fffc=0xf355;
|
||||
register_fffd=m;
|
||||
fcn_0682();
|
||||
}
|
||||
|
||||
/* a=address in ar0 */
|
||||
/* fetch a message body (up to zero)? */
|
||||
short fcn_0067(short a) {
|
||||
i=0x0357;
|
||||
j=a;
|
||||
do {
|
||||
mem[j++]=mem[i++];
|
||||
mem[j++]=mem[i];
|
||||
} while (mem[i++]);
|
||||
return a;
|
||||
}
|
||||
|
||||
/* dma in, I assume */
|
||||
/* size=words to transfer in ar0, addrL=low word of RAM address in ac0.l, addrH=high word of RAM address in ac0.m, dspaddr=dsp address in ac1.m */
|
||||
void fcn_0525(short size, short addrH, short addrL, short dspaddr) {
|
||||
register_ffcd=dspaddr; /* dsp address */
|
||||
register_ffc9=0; /* direction: ram->dsp */
|
||||
register_ffce=addrH; /* memory address H */
|
||||
register_ffcf=addrL; /* memory address L */
|
||||
register_ffcb=size<<1; /* bytes to transfer (size must be in words) */
|
||||
fcn_0536(); /* dma wait */
|
||||
}
|
||||
|
||||
/* dma wait? */
|
||||
void fcn_0536() {
|
||||
while (!(register_ffc9&4));
|
||||
}
|
||||
|
||||
/* dma out, I assume */
|
||||
/* size=words to transfer in ar0, addrL=low word of RAM address is ac0.l, addrH=high word of RAM address in ac0.m, dspaddr=dsp address in ac1.m */
|
||||
/* shares code with fcn_0525 */
|
||||
void fcn_0523(short size, short addrH, short addrL, shot dspaddr) {
|
||||
register_ffcd=dspaddr;
|
||||
/* jump back into 0525 */
|
||||
register_ffc9=1; /* direction dsp->ram */
|
||||
register_ffce=addrH;
|
||||
register_ffcf=addrL;
|
||||
register_ffcb=size<<1;
|
||||
fcn_0536();
|
||||
}
|
||||
|
||||
/* huge subroutine, op #2 */
|
||||
void sub_0243() {
|
||||
fcn_0067(0x0388); /* called in an indirect manner... */
|
||||
v_0341=v_0344; /* low byte first word of message */
|
||||
v_038e=v_0345;
|
||||
v_0355=0;
|
||||
fcn_022a(); /* get stuffs */
|
||||
fcn_05a4(); /* write to accel */
|
||||
|
||||
for (i=v_0341;i>0i--) {
|
||||
fcn_0102();
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
void fcn_022a() {
|
||||
/* something else must set 386, 387 */
|
||||
fcn_0525(0x0040,v_0386,v_0387,0x03a8);
|
||||
}
|
||||
|
||||
void fcn_05a4() {
|
||||
register_ffd4=-1;
|
||||
register_ffd5=-1;
|
||||
register_ffd6=-1;
|
||||
register_ffd7=-1;
|
||||
}
|
||||
|
||||
void fcn_0102() {
|
||||
for (i=0;i<0x50;i++) a_0d00[i]=0;
|
||||
for (i=0;i<0x50;i++) a_0d60[i]=0;
|
||||
fcn_0e3f();
|
||||
for (i=0;i<0x50;i++) a_0ca0[i]=0;
|
||||
for (i=0;i<0x50;i++) a_0f40[i]=0;
|
||||
for (i=0;i<0x50;i++) a_0fa0[i]=0;
|
||||
for (i=0;i<0x50;i++) a_0a00[i]=0;
|
||||
for (i=0;i<0x50;i++) a_09a0[i]=0;
|
||||
}
|
||||
|
||||
void fcn_0e3f() {
|
||||
fcn_00fa(0x0f40,0x0b00,0x50,0x6784);
|
||||
fcn_0ba4(0x04e8,0x0b00,0x04ec);
|
||||
}
|
||||
|
||||
/* addr1=address in ar0, addr2=address in ar3, size=size of table at addr1 in ac1.m, val=in ax0.l */
|
||||
void fcn_00fa(short addr1, short addr2, short size, short val) {
|
||||
M2(); /* all multiplications 2x */
|
||||
|
||||
tmp=mem[addr1++];
|
||||
prod=val*tmp*2;
|
||||
tmp=mem[addr1++];
|
||||
ac0.m=prod;
|
||||
prod=val*tmp*2;
|
||||
tmp=mem[addr1++];
|
||||
|
||||
do {
|
||||
ac0.m=prod;
|
||||
prod=val*tmp*2;
|
||||
mem[addr2]=ac0.m;
|
||||
tmp=mem[addr1];
|
||||
addr1++;
|
||||
addr2++;
|
||||
} while (--size);
|
||||
|
||||
M0();
|
||||
}
|
||||
|
||||
/* addr1=address in ar0 (source 4 element table?), addr2=address in ar1 (accelerator?), addr3=address in ar2 (destination 4 element table?) */
|
||||
void fcn_00ba4(short addr1, short addr2, short addr3) {
|
||||
|
||||
/* important variables */
|
||||
short mem[0x1000];
|
||||
#define v_0341 mem[0x0341] /* op#2 saves a copy of 344 here */
|
||||
#define v_0343 mem[0x0343] /* message type? */
|
||||
#define v_0344 mem[0x0344] /* low byte of first word of message */
|
||||
#define v_0345 mem[0x0345] /* copy of second word of message */
|
||||
#define a_0346 mem[0x0346] /* buffer for message contents, size unknown */
|
||||
#define v_034e mem[0x034e] /* init to 0, later set to most recent value written in a_04fc */
|
||||
|
||||
#define v_0350 mem[0x0350] /* init to 0x0280 (write location of messages) */
|
||||
#define v_0351 mem[0x0351] /* init to 0x0280 (read location?) */
|
||||
#define v_0352 mem[0x0352] /* init to 0 (number of messages pending?) */
|
||||
#define v_0355 mem[0x0355] /* used by op#2, init to 0 */
|
||||
#define a_0356 (mem+0x0356) /* message contents */
|
||||
|
||||
#define a_0388 (mem+0x388) /* where op 2 keeps its message */
|
||||
#define a_038e (mem+0x38e) /* op#2 saves a copy of 345 here */
|
||||
|
||||
#define a_03a8 (mem+0x3a8) /* where op#2 dmas in its data, at least 0x80 */
|
||||
|
||||
#define v_03fa mem[0x03fa] /* temp for ax0.h during exception */
|
||||
#define v_03fb mem[0x03fb] /* temp for ar0 during exception */
|
||||
#define v_03fc mem[0x03fc] /* temp for r08 during exception */
|
||||
#define v_03fd mem[0x03fd] /* temp for ac0.h during exception */
|
||||
#define v_03fe mem[0x03fe] /* temp for ac0.m during exception */
|
||||
#define v_03ff mem[0x03ff] /* temp for ac0.l during exception */
|
||||
|
||||
#define a_04e8 (mem+0x04e8) /* 4 element array */
|
||||
#define a_04ec (mem+0x04ec) /* 4 element array (empty) */
|
||||
#define a_04f0 (mem+0x04f0) /* 4 element array */
|
||||
#define a_04f4 (mem+0x04f4) /* 4 element array (empty) */
|
||||
#define a_04fc (mem+0x04fc) /* 16 element array, written by messages */
|
||||
#define a_09a0 (mem+0x09a0) /* 0x50 element array, used by op#2, cleared */
|
||||
#define a_0a00 (mem+0x0a00) /* 0x50 element array, used by op#2, cleared */
|
||||
#define a_0b00 (mem+0x0b00) /* array from 0x0b00-0x0bff, involves accelerator? */
|
||||
#define a_0ca0 (mem+0x0ca0) /* 0x50 element array, used by op#2, cleared */
|
||||
#define a_0d00 (mem+0x0d00) /* 0x50 element array, used by op#2, cleared */
|
||||
#define a_0d60 (mem+0x0d60) /* 0x50 element array, used by op#2, cleared */
|
||||
#define a_0f40 (mem+0x0f40) /* 0x50 element array, used by op#2, cleared */
|
||||
|
||||
|
||||
|
||||
/* reset exception vector 0x0000 */
|
||||
void main() {
|
||||
/* JMP 0x0012 */
|
||||
/* various inits */
|
||||
SBCLR(5); /* disable interrupts? */
|
||||
fcn_0057(); /* init hardware stuff */
|
||||
for(ac1.m=0x1000,ac0.m=0;ac1.m>0;ac1.m--) mem[ac0.m++]=0; /* clear all vars */
|
||||
fcn_0688(); /* init some vars */
|
||||
fcn_04c0(); /* set something up related to the accelerator at a_0b00 */
|
||||
fcn_0e14(); /* set up a table */
|
||||
fcn_066a(0); /* send a message */
|
||||
fcn_0674(0x1111); /* send a message */
|
||||
v_034e=0;
|
||||
SBSET(5); /* enable interrupts? */
|
||||
|
||||
/* jump to 0x06c5 */
|
||||
mainloop:
|
||||
while (v_0352) ; /* while no messages pending */
|
||||
|
||||
SBCLR(5); /* do not distrub */
|
||||
v_0352--; /* important that this be atomic */
|
||||
SBSET(5);
|
||||
|
||||
t=v_0351;
|
||||
size=mem[t++];
|
||||
if (!(size&0x8000)) { /* size > 0x7fff invalid */
|
||||
if (size==0) { /* die on message of length 0? */
|
||||
/* jump to 0x06f5 */
|
||||
/* jump to 0x05f0 */
|
||||
|
||||
/* TODO: analysis of HALT */
|
||||
HALT();
|
||||
}
|
||||
for (i=size,j=0;i>0;i--) {
|
||||
a_0356[j++]=mem[t++];
|
||||
a_0356[j++]=mem[t++];
|
||||
}
|
||||
v_0351=t;
|
||||
|
||||
/* jump to 0x002f */
|
||||
/* actual command handling */
|
||||
v_0345=a_0356[1];
|
||||
v_0344=a_0356[0]&0x00ff;
|
||||
v_0343=(a_0346[0]>>7)&0x7e;
|
||||
|
||||
/* jump table at 0x75 used here */
|
||||
switch (v_0343>>1) {
|
||||
|
||||
// 0x43
|
||||
case 0:
|
||||
case 10:
|
||||
case 11:
|
||||
case 12:
|
||||
case 14:
|
||||
case 15:
|
||||
/* invalid command? */
|
||||
config=0x00ff;
|
||||
fcn_066a(0x04); /* send off a message */
|
||||
fcn_0674(a_0356[0]); /* send first word of command as a message */
|
||||
goto mainloop;
|
||||
break;
|
||||
case 1:
|
||||
/* jmp 0x0095 */
|
||||
break;
|
||||
|
||||
case 2:
|
||||
/* jmp 0x0243 */
|
||||
sub_0243();
|
||||
break;
|
||||
|
||||
case 3:
|
||||
/* jmp 0x0073 */
|
||||
break;
|
||||
|
||||
case 4:
|
||||
/* jmp 0x580 */
|
||||
break;
|
||||
|
||||
case 5:
|
||||
/* jmp 0x592 */
|
||||
break;
|
||||
|
||||
case 6:
|
||||
/* jmp 0x469 */
|
||||
break;
|
||||
|
||||
case 7:
|
||||
/* jmp 0x41d */
|
||||
break;
|
||||
|
||||
case 8: /* mix */
|
||||
/* jmp 0x0485 */
|
||||
fcn_0067(fcn_0067(0x0346)); /* read message twice? */
|
||||
/* take in the two buffers to mix */
|
||||
fcn_0525(mem[0x344],mem[0x346],mem[0x347],0x400); /* size, addrH, addrL, dsp addr */
|
||||
fcn_0525(mem[0x344],mem[0x348],mem[0x349],0x800);
|
||||
S16(); /* saturate all adds, multiplies to 16 bits? */
|
||||
|
||||
i=mem[0x0344];
|
||||
src1=0x400;
|
||||
src2=0x800;
|
||||
scale=mem[0x345];
|
||||
|
||||
prod=scale*mem[src2++];
|
||||
val2=mem[src2++];
|
||||
do {
|
||||
val1=mem[src1];
|
||||
val1+=prod;
|
||||
prod=scale*val2;
|
||||
mem[src1]=val1;
|
||||
val2=mem[src2];
|
||||
src1++;
|
||||
src2++;
|
||||
} while (--i);
|
||||
|
||||
S40();
|
||||
|
||||
/* dma out mixed buf */
|
||||
fcn_0523(mem[0x344],mem[0x346],mem[0x347],0x400);
|
||||
|
||||
break;
|
||||
|
||||
case 9:
|
||||
/* jmp 0x44d */
|
||||
break;
|
||||
|
||||
case 13:
|
||||
/* jmp 0x00b2 */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
v_0351=t;
|
||||
|
||||
goto mainloop;
|
||||
}
|
||||
|
||||
/* message in MBOX exception vector? 0x000e */
|
||||
void exception() {
|
||||
/* JMP 0x05b8 */
|
||||
|
||||
SBCLR(5);
|
||||
S40();
|
||||
/* save ax0.h,ac0.h,ac0.m, and ac0.l */
|
||||
|
||||
if ((tH=register_fffe)&0x8000) { /* CPU mailbox H */
|
||||
if (!(tsize=register_ffff)) { /* CPU mailbox L */
|
||||
/* empty message? */
|
||||
while (!((tH=register_fffe)&0x8000)) ;
|
||||
tH&=0xf;
|
||||
v_034e=(tH+1)<<4;
|
||||
a_04fc[tH]=register_ffff;
|
||||
} else { /* nonempty message? */
|
||||
/* jump to 0x0692 */
|
||||
/* save ar0, r08 */
|
||||
t=v_0350;
|
||||
mem[t++]=tsize;
|
||||
|
||||
do {
|
||||
while (!((tH=register_fffe)&0x8000)) ;
|
||||
mem[t++]=tH;
|
||||
mem[t++]=register_ffff;
|
||||
} while (--tsize);
|
||||
|
||||
v_0350=t;
|
||||
v_0352++;
|
||||
/* restore ar0, r08 */
|
||||
|
||||
/* jump to 0x05e6 */
|
||||
}
|
||||
} else { /* interrupt without message? */
|
||||
/* jump to 0x06b9 */
|
||||
/* save ar0, r08 */
|
||||
mem[v_0350]=0; /* empty message */
|
||||
/* jump to 0x06ab */
|
||||
v_0350++;
|
||||
v_0352++;
|
||||
/* restore ar0, r08 */
|
||||
|
||||
/* jump to 0x05e6 */
|
||||
}
|
||||
|
||||
/* 0x05e6 */
|
||||
|
||||
/* restore ax0.h,ac0.h,ac0.m, and ac0.l */
|
||||
SBSET(5);
|
||||
/* RTI */
|
||||
}
|
||||
|
||||
/* set up some registers */
|
||||
void fcn_0057() {
|
||||
SBCLR(2);
|
||||
SBCLR(3);
|
||||
SBCLR(4);
|
||||
SBCLR(6);
|
||||
S40(); /* 40-bit mode */
|
||||
CLR15();
|
||||
M0(); /* don't multiply result by 2 */
|
||||
r08=-1;
|
||||
r09=-1;
|
||||
r0a=-1;
|
||||
r0b=-1;
|
||||
config=0xff;
|
||||
}
|
||||
|
||||
void fcn_0688() {
|
||||
v_0350=0x0280;
|
||||
v_0351=0x0280;
|
||||
v_0352=0;
|
||||
}
|
||||
|
||||
void fcn_04c0() {
|
||||
config=0xff;
|
||||
for(i=0xff,ar0=0xb00;i>0;i--) mem[ar0++]=0;
|
||||
mem[ar0++]=0; /* get the last one */
|
||||
fcn_0573(0x0b00,0x0100,0);
|
||||
}
|
||||
|
||||
/* a=an address in ac1.m, l=a length in ar0, v=a value? in ac0.m */
|
||||
void fcn_0573(short a, short l, short v) {
|
||||
fcn_0561(a,l,0x0001);
|
||||
}
|
||||
|
||||
/* a=an address in ac1.m, l=a length in ar0, v=a value? in ac0.m, f is a flag? in ac0.h */
|
||||
/* return is in ax0.h */
|
||||
short fcn_0561(short a, short l, short v, short f) {
|
||||
register_ffd1=0x0a; /* unknown reg, accel? */
|
||||
register_ffd6=-1; /* accel end addr H */
|
||||
register_ffd7=-1; /* accel end addr L */
|
||||
register_ffd8=v>>1; /*
|
||||
register_ffd9=?; /* has a value from way back? */
|
||||
|
||||
return f;
|
||||
}
|
||||
|
||||
/* initializes some tables that look useful... */
|
||||
void fcn_0e14() {
|
||||
a_04e8[0]=0x8240;
|
||||
a_04e8[1]=0x7fff;
|
||||
a_04e8[2]=0x7dbf;
|
||||
a_04e8[3]=0x843f;
|
||||
a_04f0[0]=0xb23b;
|
||||
a_04f0[1]=0x7fff;
|
||||
a_04f0[2]=0x4dc4;
|
||||
a_04f0[3]=0xd808;
|
||||
a_04ec[0]=a_04ec[1]=a_04ec[2]=a_04ec[3]=0;
|
||||
a_04f4[0]=a_04f4[1]=a_04f4[2]=a_04f4[3]=0;
|
||||
}
|
||||
|
||||
/* send a message via DSP MBOX */
|
||||
void fcn_066a(short m) {
|
||||
fcn_0682(); /* wait for empty mbox */
|
||||
register_fffc=0xdcd1;
|
||||
register_fffd=m;
|
||||
register_fffb=1; /* IRQ */
|
||||
fcn_0682();
|
||||
}
|
||||
|
||||
/* wait for dsp mbox empty */
|
||||
void fcn_0682() {
|
||||
while (register_fffc&0x8000);
|
||||
}
|
||||
|
||||
void fcn_0674(short m) {
|
||||
fcn_0682();
|
||||
register_fffc=0xf355;
|
||||
register_fffd=m;
|
||||
fcn_0682();
|
||||
}
|
||||
|
||||
/* a=address in ar0 */
|
||||
/* fetch a message body (up to zero)? */
|
||||
short fcn_0067(short a) {
|
||||
i=0x0357;
|
||||
j=a;
|
||||
do {
|
||||
mem[j++]=mem[i++];
|
||||
mem[j++]=mem[i];
|
||||
} while (mem[i++]);
|
||||
return a;
|
||||
}
|
||||
|
||||
/* dma in, I assume */
|
||||
/* size=words to transfer in ar0, addrL=low word of RAM address in ac0.l, addrH=high word of RAM address in ac0.m, dspaddr=dsp address in ac1.m */
|
||||
void fcn_0525(short size, short addrH, short addrL, short dspaddr) {
|
||||
register_ffcd=dspaddr; /* dsp address */
|
||||
register_ffc9=0; /* direction: ram->dsp */
|
||||
register_ffce=addrH; /* memory address H */
|
||||
register_ffcf=addrL; /* memory address L */
|
||||
register_ffcb=size<<1; /* bytes to transfer (size must be in words) */
|
||||
fcn_0536(); /* dma wait */
|
||||
}
|
||||
|
||||
/* dma wait? */
|
||||
void fcn_0536() {
|
||||
while (!(register_ffc9&4));
|
||||
}
|
||||
|
||||
/* dma out, I assume */
|
||||
/* size=words to transfer in ar0, addrL=low word of RAM address is ac0.l, addrH=high word of RAM address in ac0.m, dspaddr=dsp address in ac1.m */
|
||||
/* shares code with fcn_0525 */
|
||||
void fcn_0523(short size, short addrH, short addrL, shot dspaddr) {
|
||||
register_ffcd=dspaddr;
|
||||
/* jump back into 0525 */
|
||||
register_ffc9=1; /* direction dsp->ram */
|
||||
register_ffce=addrH;
|
||||
register_ffcf=addrL;
|
||||
register_ffcb=size<<1;
|
||||
fcn_0536();
|
||||
}
|
||||
|
||||
/* huge subroutine, op #2 */
|
||||
void sub_0243() {
|
||||
fcn_0067(0x0388); /* called in an indirect manner... */
|
||||
v_0341=v_0344; /* low byte first word of message */
|
||||
v_038e=v_0345;
|
||||
v_0355=0;
|
||||
fcn_022a(); /* get stuffs */
|
||||
fcn_05a4(); /* write to accel */
|
||||
|
||||
for (i=v_0341;i>0i--) {
|
||||
fcn_0102();
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
void fcn_022a() {
|
||||
/* something else must set 386, 387 */
|
||||
fcn_0525(0x0040,v_0386,v_0387,0x03a8);
|
||||
}
|
||||
|
||||
void fcn_05a4() {
|
||||
register_ffd4=-1;
|
||||
register_ffd5=-1;
|
||||
register_ffd6=-1;
|
||||
register_ffd7=-1;
|
||||
}
|
||||
|
||||
void fcn_0102() {
|
||||
for (i=0;i<0x50;i++) a_0d00[i]=0;
|
||||
for (i=0;i<0x50;i++) a_0d60[i]=0;
|
||||
fcn_0e3f();
|
||||
for (i=0;i<0x50;i++) a_0ca0[i]=0;
|
||||
for (i=0;i<0x50;i++) a_0f40[i]=0;
|
||||
for (i=0;i<0x50;i++) a_0fa0[i]=0;
|
||||
for (i=0;i<0x50;i++) a_0a00[i]=0;
|
||||
for (i=0;i<0x50;i++) a_09a0[i]=0;
|
||||
}
|
||||
|
||||
void fcn_0e3f() {
|
||||
fcn_00fa(0x0f40,0x0b00,0x50,0x6784);
|
||||
fcn_0ba4(0x04e8,0x0b00,0x04ec);
|
||||
}
|
||||
|
||||
/* addr1=address in ar0, addr2=address in ar3, size=size of table at addr1 in ac1.m, val=in ax0.l */
|
||||
void fcn_00fa(short addr1, short addr2, short size, short val) {
|
||||
M2(); /* all multiplications 2x */
|
||||
|
||||
tmp=mem[addr1++];
|
||||
prod=val*tmp*2;
|
||||
tmp=mem[addr1++];
|
||||
ac0.m=prod;
|
||||
prod=val*tmp*2;
|
||||
tmp=mem[addr1++];
|
||||
|
||||
do {
|
||||
ac0.m=prod;
|
||||
prod=val*tmp*2;
|
||||
mem[addr2]=ac0.m;
|
||||
tmp=mem[addr1];
|
||||
addr1++;
|
||||
addr2++;
|
||||
} while (--size);
|
||||
|
||||
M0();
|
||||
}
|
||||
|
||||
/* addr1=address in ar0 (source 4 element table?), addr2=address in ar1 (accelerator?), addr3=address in ar2 (destination 4 element table?) */
|
||||
void fcn_00ba4(short addr1, short addr2, short addr3) {
|
||||
|
||||
}
|
||||
Reference in New Issue
Block a user