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docs/DSP: Fix typo with arithmetic instructions that take a 16-bit immediate
These instructions used an 'r' in their bit list, but a 'd' in the operands.
This commit is contained in:
@ -45,7 +45,7 @@ void Interpreter::clrl(const UDSPInstruction opc)
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//----
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// ANDCF $acD.m, #I
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// 0000 001r 1100 0000
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// 0000 001d 1100 0000
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// iiii iiii iiii iiii
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// Set logic zero (LZ) flag in status register $sr if result of logic AND of
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// accumulator mid part $acD.m with immediate value I is equal to I.
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@ -61,7 +61,7 @@ void Interpreter::andcf(const UDSPInstruction opc)
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}
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// ANDF $acD.m, #I
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// 0000 001r 1010 0000
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// 0000 001d 1010 0000
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// iiii iiii iiii iiii
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// Set logic zero (LZ) flag in status register $sr if result of logical AND
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// operation of accumulator mid part $acD.m with immediate value I is equal
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@ -144,7 +144,7 @@ void Interpreter::cmpaxh(const UDSPInstruction opc)
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}
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// CMPI $amD, #I
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// 0000 001r 1000 0000
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// 0000 001d 1000 0000
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// iiii iiii iiii iiii
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// Compares mid accumulator $acD.hm ($amD) with sign extended immediate value I.
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// Although flags are being set regarding whole accumulator register.
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@ -320,7 +320,7 @@ void Interpreter::notc(const UDSPInstruction opc)
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}
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// XORI $acD.m, #I
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// 0000 001r 0010 0000
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// 0000 001d 0010 0000
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// iiii iiii iiii iiii
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// Logic exclusive or (XOR) of accumulator mid part $acD.m with
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// immediate value I.
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@ -337,7 +337,7 @@ void Interpreter::xori(const UDSPInstruction opc)
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}
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// ANDI $acD.m, #I
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// 0000 001r 0100 0000
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// 0000 001d 0100 0000
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// iiii iiii iiii iiii
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// Logic AND of accumulator mid part $acD.m with immediate value I.
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//
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@ -354,7 +354,7 @@ void Interpreter::andi(const UDSPInstruction opc)
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}
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// ORI $acD.m, #I
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// 0000 001r 0110 0000
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// 0000 001d 0110 0000
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// iiii iiii iiii iiii
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// Logic OR of accumulator mid part $acD.m with immediate value I.
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//
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@ -489,8 +489,8 @@ void Interpreter::addaxl(const UDSPInstruction opc)
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UpdateSR64Add(acc, acx, GetLongAcc(dreg));
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}
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// ADDI $amR, #I
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// 0000 001r 0000 0000
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// ADDI $amD, #I
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// 0000 001d 0000 0000
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// iiii iiii iiii iiii
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// Adds immediate (16-bit sign extended) to mid accumulator $acD.hm.
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//
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@ -53,7 +53,7 @@ void DSPEmitter::clrl(const UDSPInstruction opc)
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//----
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// ANDCF $acD.m, #I
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// 0000 001r 1100 0000
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// 0000 001d 1100 0000
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// iiii iiii iiii iiii
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// Set logic zero (LZ) flag in status register $sr if result of logic AND of
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// accumulator mid part $acD.m with immediate value I is equal to I.
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@ -88,7 +88,7 @@ void DSPEmitter::andcf(const UDSPInstruction opc)
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}
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// ANDF $acD.m, #I
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// 0000 001r 1010 0000
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// 0000 001d 1010 0000
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// iiii iiii iiii iiii
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// Set logic zero (LZ) flag in status register $sr if result of logical AND
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// operation of accumulator mid part $acD.m with immediate value I is equal
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@ -221,7 +221,7 @@ void DSPEmitter::cmpaxh(const UDSPInstruction opc)
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}
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// CMPI $amD, #I
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// 0000 001r 1000 0000
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// 0000 001d 1000 0000
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// iiii iiii iiii iiii
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// Compares mid accumulator $acD.hm ($amD) with sign extended immediate value I.
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// Although flags are being set regarding whole accumulator register.
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@ -458,7 +458,7 @@ void DSPEmitter::notc(const UDSPInstruction opc)
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}
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// XORI $acD.m, #I
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// 0000 001r 0010 0000
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// 0000 001d 0010 0000
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// iiii iiii iiii iiii
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// Logic exclusive or (XOR) of accumulator mid part $acD.m with
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// immediate value I.
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@ -482,7 +482,7 @@ void DSPEmitter::xori(const UDSPInstruction opc)
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}
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// ANDI $acD.m, #I
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// 0000 001r 0100 0000
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// 0000 001d 0100 0000
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// iiii iiii iiii iiii
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// Logic AND of accumulator mid part $acD.m with immediate value I.
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//
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@ -505,7 +505,7 @@ void DSPEmitter::andi(const UDSPInstruction opc)
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}
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// ORI $acD.m, #I
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// 0000 001r 0110 0000
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// 0000 001d 0110 0000
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// iiii iiii iiii iiii
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// Logic OR of accumulator mid part $acD.m with immediate value I.
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//
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@ -686,8 +686,8 @@ void DSPEmitter::addaxl(const UDSPInstruction opc)
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}
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}
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// ADDI $amR, #I
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// 0000 001r 0000 0000
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// ADDI $amD, #I
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// 0000 001d 0000 0000
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// iiii iiii iiii iiii
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// Adds immediate (16-bit sign extended) to mid accumulator $acD.hm.
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//
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