piwalker/dolphin
1
0
Fork 0
mirror of https://github.com/dolphin-emu/dolphin.git synced 2024-11-14 21:37:52 -07:00
Code Issues Actions Packages Projects Releases Wiki Activity

Merge pull request #4823 from lioncash/tlb

Browse Source 
PowerPC: Rename tlb_entry struct to TLBEntry
This commit is contained in:
Matthew Parlane 2017-02-06 00:59:39 +13:00 committed by GitHub
commit 4df22e03ca
2 changed files with 31 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
Source/Core/Core/PowerPC/MMU.cpp
View File

@ -971,49 +971,50 @@ enum TLBLookupResult
static TLBLookupResult LookupTLBPageAddress(const XCheckTLBFlag flag, const u32 vpa, u32* paddr) static TLBLookupResult LookupTLBPageAddress(const XCheckTLBFlag flag, const u32 vpa, u32* paddr)
{ {
u32 tag = vpa >> HW_PAGE_INDEX_SHIFT; const u32 tag = vpa >> HW_PAGE_INDEX_SHIFT;
PowerPC::tlb_entry* tlbe = &PowerPC::ppcState.tlb[IsOpcodeFlag(flag)][tag & HW_PAGE_INDEX_MASK]; TLBEntry& tlbe = ppcState.tlb[IsOpcodeFlag(flag)][tag & HW_PAGE_INDEX_MASK];
if (tlbe->tag[0] == tag)
if (tlbe.tag[0] == tag)
{ {
// Check if C bit requires updating // Check if C bit requires updating
if (flag == FLAG_WRITE) if (flag == FLAG_WRITE)
{ {
UPTE2 PTE2; UPTE2 PTE2;
PTE2.Hex = tlbe->pte[0]; PTE2.Hex = tlbe.pte[0];
if (PTE2.C == 0) if (PTE2.C == 0)
{ {
PTE2.C = 1; PTE2.C = 1;
tlbe->pte[0] = PTE2.Hex; tlbe.pte[0] = PTE2.Hex;
return TLB_UPDATE_C; return TLB_UPDATE_C;
} }
} }
if (!IsNoExceptionFlag(flag)) if (!IsNoExceptionFlag(flag))
tlbe->recent = 0; tlbe.recent = 0;
*paddr = tlbe->paddr[0] | (vpa & 0xfff); *paddr = tlbe.paddr[0] | (vpa & 0xfff);
return TLB_FOUND; return TLB_FOUND;
} }
if (tlbe->tag[1] == tag) if (tlbe.tag[1] == tag)
{ {
// Check if C bit requires updating // Check if C bit requires updating
if (flag == FLAG_WRITE) if (flag == FLAG_WRITE)
{ {
UPTE2 PTE2; UPTE2 PTE2;
PTE2.Hex = tlbe->pte[1]; PTE2.Hex = tlbe.pte[1];
if (PTE2.C == 0) if (PTE2.C == 0)
{ {
PTE2.C = 1; PTE2.C = 1;
tlbe->pte[1] = PTE2.Hex; tlbe.pte[1] = PTE2.Hex;
return TLB_UPDATE_C; return TLB_UPDATE_C;
} }
} }
if (!IsNoExceptionFlag(flag)) if (!IsNoExceptionFlag(flag))
tlbe->recent = 1; tlbe.recent = 1;
*paddr = tlbe->paddr[1] | (vpa & 0xfff); *paddr = tlbe.paddr[1] | (vpa & 0xfff);
return TLB_FOUND; return TLB_FOUND;
} }
@ -1025,25 +1026,26 @@ static void UpdateTLBEntry(const XCheckTLBFlag flag, UPTE2 PTE2, const u32 addre
if (IsNoExceptionFlag(flag)) if (IsNoExceptionFlag(flag))
return; return;
int tag = address >> HW_PAGE_INDEX_SHIFT; const int tag = address >> HW_PAGE_INDEX_SHIFT;
PowerPC::tlb_entry* tlbe = &PowerPC::ppcState.tlb[IsOpcodeFlag(flag)][tag & HW_PAGE_INDEX_MASK]; TLBEntry& tlbe = ppcState.tlb[IsOpcodeFlag(flag)][tag & HW_PAGE_INDEX_MASK];
int index = tlbe->recent == 0 && tlbe->tag[0] != TLB_TAG_INVALID; const int index = tlbe.recent == 0 && tlbe.tag[0] != TLB_TAG_INVALID;
tlbe->recent = index; tlbe.recent = index;
tlbe->paddr[index] = PTE2.RPN << HW_PAGE_INDEX_SHIFT; tlbe.paddr[index] = PTE2.RPN << HW_PAGE_INDEX_SHIFT;
tlbe->pte[index] = PTE2.Hex; tlbe.pte[index] = PTE2.Hex;
tlbe->tag[index] = tag; tlbe.tag[index] = tag;
} }
void InvalidateTLBEntry(u32 address) void InvalidateTLBEntry(u32 address)
{ {
PowerPC::tlb_entry* tlbe = const u32 entry_index = (address >> HW_PAGE_INDEX_SHIFT) & HW_PAGE_INDEX_MASK;
&PowerPC::ppcState.tlb[0][(address >> HW_PAGE_INDEX_SHIFT) & HW_PAGE_INDEX_MASK];
tlbe->tag[0] = TLB_TAG_INVALID; TLBEntry& tlbe = ppcState.tlb[0][entry_index];
tlbe->tag[1] = TLB_TAG_INVALID; tlbe.tag[0] = TLB_TAG_INVALID;
PowerPC::tlb_entry* tlbe_i = tlbe.tag[1] = TLB_TAG_INVALID;
&PowerPC::ppcState.tlb[1][(address >> HW_PAGE_INDEX_SHIFT) & HW_PAGE_INDEX_MASK];
tlbe_i->tag[0] = TLB_TAG_INVALID; TLBEntry& tlbe_i = ppcState.tlb[1][entry_index];
tlbe_i->tag[1] = TLB_TAG_INVALID; tlbe_i.tag[0] = TLB_TAG_INVALID;
tlbe_i.tag[1] = TLB_TAG_INVALID;
} }
// Page Address Translation // Page Address Translation

4
Source/Core/Core/PowerPC/PowerPC.h
View File

@ -42,7 +42,7 @@ enum class CoreMode
#define TLB_WAYS 2 #define TLB_WAYS 2
#define TLB_TAG_INVALID 0xffffffff #define TLB_TAG_INVALID 0xffffffff
struct tlb_entry struct TLBEntry
{ {
u32 tag[TLB_WAYS] = {TLB_TAG_INVALID, TLB_TAG_INVALID}; u32 tag[TLB_WAYS] = {TLB_TAG_INVALID, TLB_TAG_INVALID};
u32 paddr[TLB_WAYS] = {}; u32 paddr[TLB_WAYS] = {};
@ -114,7 +114,7 @@ struct PowerPCState
// Storage for the stack pointer of the BLR optimization. // Storage for the stack pointer of the BLR optimization.
u8* stored_stack_pointer; u8* stored_stack_pointer;
std::array<std::array<tlb_entry, TLB_SIZE / TLB_WAYS>, NUM_TLBS> tlb; std::array<std::array<TLBEntry, TLB_SIZE / TLB_WAYS>, NUM_TLBS> tlb;
u32 pagetable_base; u32 pagetable_base;
u32 pagetable_hashmask; u32 pagetable_hashmask;