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Assert: Uppercase assertion macros

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Macros should be all upper-cased. This is also kind of a wart that's
been sticking out for quite a while now (we avoid prefixing
underscores).
This commit is contained in:
Lioncash
2018-03-14 20:34:35 -04:00
parent 19d97f3fd9
commit 50a476c371
135 changed files with 719 additions and 741 deletions
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312
Source/Core/Common/Arm64Emitter.cpp
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@ -210,7 +210,7 @@ bool IsImmLogical(uint64_t value, unsigned int width, unsigned int* n, unsigned
int multiplier_idx = CountLeadingZeros(d, kXRegSizeInBits) - 57;
// Ensure that the index to the multipliers array is within bounds.
_dbg_assert_(DYNA_REC,
DEBUG_ASSERT(DYNA_REC,
(multiplier_idx >= 0) && (static_cast<size_t>(multiplier_idx) < multipliers.size()));
uint64_t multiplier = multipliers[multiplier_idx];
@ -481,13 +481,13 @@ void ARM64XEmitter::EncodeCompareBranchInst(u32 op, ARM64Reg Rt, const void* ptr
bool b64Bit = Is64Bit(Rt);
s64 distance = (s64)ptr - (s64)m_code;
_assert_msg_(DYNA_REC, !(distance & 0x3), "%s: distance must be a multiple of 4: %" PRIx64,
__FUNCTION__, distance);
ASSERT_MSG(DYNA_REC, !(distance & 0x3), "%s: distance must be a multiple of 4: %" PRIx64,
__FUNCTION__, distance);
distance >>= 2;
_assert_msg_(DYNA_REC, distance >= -0x40000 && distance <= 0x3FFFF,
"%s: Received too large distance: %" PRIx64, __FUNCTION__, distance);
ASSERT_MSG(DYNA_REC, distance >= -0x40000 && distance <= 0x3FFFF,
"%s: Received too large distance: %" PRIx64, __FUNCTION__, distance);
Rt = DecodeReg(Rt);
Write32((b64Bit << 31) | (0x34 << 24) | (op << 24) | (((u32)distance << 5) & 0xFFFFE0) | Rt);
@ -498,13 +498,13 @@ void ARM64XEmitter::EncodeTestBranchInst(u32 op, ARM64Reg Rt, u8 bits, const voi
bool b64Bit = Is64Bit(Rt);
s64 distance = (s64)ptr - (s64)m_code;
_assert_msg_(DYNA_REC, !(distance & 0x3), "%s: distance must be a multiple of 4: %" PRIx64,
__FUNCTION__, distance);
ASSERT_MSG(DYNA_REC, !(distance & 0x3), "%s: distance must be a multiple of 4: %" PRIx64,
__FUNCTION__, distance);
distance >>= 2;
_assert_msg_(DYNA_REC, distance >= -0x3FFF && distance < 0x3FFF,
"%s: Received too large distance: %" PRIx64, __FUNCTION__, distance);
ASSERT_MSG(DYNA_REC, distance >= -0x3FFF && distance < 0x3FFF,
"%s: Received too large distance: %" PRIx64, __FUNCTION__, distance);
Rt = DecodeReg(Rt);
Write32((b64Bit << 31) | (0x36 << 24) | (op << 24) | (bits << 19) |
@ -515,13 +515,13 @@ void ARM64XEmitter::EncodeUnconditionalBranchInst(u32 op, const void* ptr)
{
s64 distance = (s64)ptr - s64(m_code);
_assert_msg_(DYNA_REC, !(distance & 0x3), "%s: distance must be a multiple of 4: %" PRIx64,
__FUNCTION__, distance);
ASSERT_MSG(DYNA_REC, !(distance & 0x3), "%s: distance must be a multiple of 4: %" PRIx64,
__FUNCTION__, distance);
distance >>= 2;
_assert_msg_(DYNA_REC, distance >= -0x2000000LL && distance <= 0x1FFFFFFLL,
"%s: Received too large distance: %" PRIx64, __FUNCTION__, distance);
ASSERT_MSG(DYNA_REC, distance >= -0x2000000LL && distance <= 0x1FFFFFFLL,
"%s: Received too large distance: %" PRIx64, __FUNCTION__, distance);
Write32((op << 31) | (0x5 << 26) | (distance & 0x3FFFFFF));
}
@ -534,8 +534,8 @@ void ARM64XEmitter::EncodeUnconditionalBranchInst(u32 opc, u32 op2, u32 op3, u32
void ARM64XEmitter::EncodeExceptionInst(u32 instenc, u32 imm)
{
_assert_msg_(DYNA_REC, !(imm & ~0xFFFF), "%s: Exception instruction too large immediate: %d",
__FUNCTION__, imm);
ASSERT_MSG(DYNA_REC, !(imm & ~0xFFFF), "%s: Exception instruction too large immediate: %d",
__FUNCTION__, imm);
Write32((0xD4 << 24) | (ExcEnc[instenc][0] << 21) | (imm << 5) | (ExcEnc[instenc][1] << 2) |
ExcEnc[instenc][2]);
@ -574,10 +574,10 @@ void ARM64XEmitter::EncodeCondCompareImmInst(u32 op, ARM64Reg Rn, u32 imm, u32 n
{
bool b64Bit = Is64Bit(Rn);
_assert_msg_(DYNA_REC, !(imm & ~0x1F), "%s: too large immediate: %d", __FUNCTION__, imm)
_assert_msg_(DYNA_REC, !(nzcv & ~0xF), "%s: Flags out of range: %d", __FUNCTION__, nzcv)
ASSERT_MSG(DYNA_REC, !(imm & ~0x1F), "%s: too large immediate: %d", __FUNCTION__, imm);
ASSERT_MSG(DYNA_REC, !(nzcv & ~0xF), "%s: Flags out of range: %d", __FUNCTION__, nzcv);
Rn = DecodeReg(Rn);
Rn = DecodeReg(Rn);
Write32((b64Bit << 31) | (op << 30) | (1 << 29) | (0xD2 << 21) | (imm << 16) | (cond << 12) |
(1 << 11) | (Rn << 5) | nzcv);
}
@ -587,9 +587,9 @@ void ARM64XEmitter::EncodeCondCompareRegInst(u32 op, ARM64Reg Rn, ARM64Reg Rm, u
{
bool b64Bit = Is64Bit(Rm);
_assert_msg_(DYNA_REC, !(nzcv & ~0xF), "%s: Flags out of range: %d", __FUNCTION__, nzcv)
ASSERT_MSG(DYNA_REC, !(nzcv & ~0xF), "%s: Flags out of range: %d", __FUNCTION__, nzcv);
Rm = DecodeReg(Rm);
Rm = DecodeReg(Rm);
Rn = DecodeReg(Rn);
Write32((b64Bit << 31) | (op << 30) | (1 << 29) | (0xD2 << 21) | (Rm << 16) | (cond << 12) |
(Rn << 5) | nzcv);
@ -658,7 +658,7 @@ void ARM64XEmitter::EncodeLoadRegisterInst(u32 bitop, ARM64Reg Rt, u32 imm)
bool b64Bit = Is64Bit(Rt);
bool bVec = IsVector(Rt);
_assert_msg_(DYNA_REC, !(imm & 0xFFFFF), "%s: offset too large %d", __FUNCTION__, imm);
ASSERT_MSG(DYNA_REC, !(imm & 0xFFFFF), "%s: offset too large %d", __FUNCTION__, imm);
Rt = DecodeReg(Rt);
if (b64Bit && bitop != 0x2) // LDRSW(0x2) uses 64bit reg, doesn't have 64bit bit set
@ -692,7 +692,7 @@ void ARM64XEmitter::EncodeLoadStorePairedInst(u32 op, ARM64Reg Rt, ARM64Reg Rt2,
else
imm >>= 2;
_assert_msg_(DYNA_REC, !(imm & ~0xF), "%s: offset too large %d", __FUNCTION__, imm);
ASSERT_MSG(DYNA_REC, !(imm & ~0xF), "%s: offset too large %d", __FUNCTION__, imm);
u32 opc = 0;
if (b128Bit)
@ -715,7 +715,7 @@ void ARM64XEmitter::EncodeLoadStoreIndexedInst(u32 op, u32 op2, ARM64Reg Rt, ARM
u32 offset = imm & 0x1FF;
_assert_msg_(DYNA_REC, !(imm < -256 || imm > 255), "%s: offset too large %d", __FUNCTION__, imm);
ASSERT_MSG(DYNA_REC, !(imm < -256 || imm > 255), "%s: offset too large %d", __FUNCTION__, imm);
Rt = DecodeReg(Rt);
Rn = DecodeReg(Rn);
@ -735,10 +735,10 @@ void ARM64XEmitter::EncodeLoadStoreIndexedInst(u32 op, ARM64Reg Rt, ARM64Reg Rn,
else if (size == 16)
imm >>= 1;
_assert_msg_(DYNA_REC, imm >= 0, "%s(INDEX_UNSIGNED): offset must be positive %d", __FUNCTION__,
imm);
_assert_msg_(DYNA_REC, !(imm & ~0xFFF), "%s(INDEX_UNSIGNED): offset too large %d", __FUNCTION__,
imm);
ASSERT_MSG(DYNA_REC, imm >= 0, "%s(INDEX_UNSIGNED): offset must be positive %d", __FUNCTION__,
imm);
ASSERT_MSG(DYNA_REC, !(imm & ~0xFFF), "%s(INDEX_UNSIGNED): offset too large %d", __FUNCTION__,
imm);
Rt = DecodeReg(Rt);
Rn = DecodeReg(Rn);
@ -749,7 +749,7 @@ void ARM64XEmitter::EncodeMOVWideInst(u32 op, ARM64Reg Rd, u32 imm, ShiftAmount
{
bool b64Bit = Is64Bit(Rd);
_assert_msg_(DYNA_REC, !(imm & ~0xFFFF), "%s: immediate out of range: %d", __FUNCTION__, imm);
ASSERT_MSG(DYNA_REC, !(imm & ~0xFFFF), "%s: immediate out of range: %d", __FUNCTION__, imm);
Rd = DecodeReg(Rd);
Write32((b64Bit << 31) | (op << 29) | (0x25 << 23) | (pos << 21) | (imm << 5) | Rd);
@ -781,7 +781,7 @@ void ARM64XEmitter::EncodeAddSubImmInst(u32 op, bool flags, u32 shift, u32 imm,
{
bool b64Bit = Is64Bit(Rd);
_assert_msg_(DYNA_REC, !(imm & ~0xFFF), "%s: immediate too large: %x", __FUNCTION__, imm);
ASSERT_MSG(DYNA_REC, !(imm & ~0xFFF), "%s: immediate too large: %x", __FUNCTION__, imm);
Rd = DecodeReg(Rd);
Rn = DecodeReg(Rn);
@ -821,7 +821,7 @@ void ARM64XEmitter::EncodeLoadStorePair(u32 op, u32 load, IndexType type, ARM64R
type_encode = 0b011;
break;
case INDEX_UNSIGNED:
_assert_msg_(DYNA_REC, false, "%s doesn't support INDEX_UNSIGNED!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, false, "%s doesn't support INDEX_UNSIGNED!", __FUNCTION__);
break;
}
@ -851,8 +851,8 @@ void ARM64XEmitter::EncodeAddressInst(u32 op, ARM64Reg Rd, s32 imm)
void ARM64XEmitter::EncodeLoadStoreUnscaled(u32 size, u32 op, ARM64Reg Rt, ARM64Reg Rn, s32 imm)
{
_assert_msg_(DYNA_REC, !(imm < -256 || imm > 255), "%s received too large offset: %d",
__FUNCTION__, imm);
ASSERT_MSG(DYNA_REC, !(imm < -256 || imm > 255), "%s received too large offset: %d", __FUNCTION__,
imm);
Rt = DecodeReg(Rt);
Rn = DecodeReg(Rn);
@ -903,42 +903,37 @@ void ARM64XEmitter::SetJumpTarget(FixupBranch const& branch)
Not = true;
case 0: // CBZ
{
_assert_msg_(DYNA_REC, IsInRangeImm19(distance),
"%s(%d): Received too large distance: %" PRIx64, __FUNCTION__, branch.type,
distance);
ASSERT_MSG(DYNA_REC, IsInRangeImm19(distance), "%s(%d): Received too large distance: %" PRIx64,
__FUNCTION__, branch.type, distance);
bool b64Bit = Is64Bit(branch.reg);
ARM64Reg reg = DecodeReg(branch.reg);
inst = (b64Bit << 31) | (0x1A << 25) | (Not << 24) | (MaskImm19(distance) << 5) | reg;
}
break;
case 2: // B (conditional)
_assert_msg_(DYNA_REC, IsInRangeImm19(distance),
"%s(%d): Received too large distance: %" PRIx64, __FUNCTION__, branch.type,
distance);
ASSERT_MSG(DYNA_REC, IsInRangeImm19(distance), "%s(%d): Received too large distance: %" PRIx64,
__FUNCTION__, branch.type, distance);
inst = (0x2A << 25) | (MaskImm19(distance) << 5) | branch.cond;
break;
case 4: // TBNZ
Not = true;
case 3: // TBZ
{
_assert_msg_(DYNA_REC, IsInRangeImm14(distance),
"%s(%d): Received too large distance: %" PRIx64, __FUNCTION__, branch.type,
distance);
ASSERT_MSG(DYNA_REC, IsInRangeImm14(distance), "%s(%d): Received too large distance: %" PRIx64,
__FUNCTION__, branch.type, distance);
ARM64Reg reg = DecodeReg(branch.reg);
inst = ((branch.bit & 0x20) << 26) | (0x1B << 25) | (Not << 24) | ((branch.bit & 0x1F) << 19) |
(MaskImm14(distance) << 5) | reg;
}
break;
case 5: // B (uncoditional)
_assert_msg_(DYNA_REC, IsInRangeImm26(distance),
"%s(%d): Received too large distance: %" PRIx64, __FUNCTION__, branch.type,
distance);
ASSERT_MSG(DYNA_REC, IsInRangeImm26(distance), "%s(%d): Received too large distance: %" PRIx64,
__FUNCTION__, branch.type, distance);
inst = (0x5 << 26) | MaskImm26(distance);
break;
case 6: // BL (unconditional)
_assert_msg_(DYNA_REC, IsInRangeImm26(distance),
"%s(%d): Received too large distance: %" PRIx64, __FUNCTION__, branch.type,
distance);
ASSERT_MSG(DYNA_REC, IsInRangeImm26(distance), "%s(%d): Received too large distance: %" PRIx64,
__FUNCTION__, branch.type, distance);
inst = (0x25 << 26) | MaskImm26(distance);
break;
}
@ -1026,9 +1021,9 @@ void ARM64XEmitter::B(CCFlags cond, const void* ptr)
distance >>= 2;
_assert_msg_(DYNA_REC, IsInRangeImm19(distance),
"%s: Received too large distance: %p->%p %" PRIi64 " %" PRIx64, __FUNCTION__, m_code,
ptr, distance, distance);
ASSERT_MSG(DYNA_REC, IsInRangeImm19(distance),
"%s: Received too large distance: %p->%p %" PRIi64 " %" PRIx64, __FUNCTION__, m_code,
ptr, distance, distance);
Write32((0x54 << 24) | (MaskImm19(distance) << 5) | cond);
}
@ -1151,7 +1146,7 @@ void ARM64XEmitter::_MSR(PStateField field, u8 imm)
op2 = 7;
break;
default:
_assert_msg_(DYNA_REC, false, "Invalid PStateField to do a imm move to");
ASSERT_MSG(DYNA_REC, false, "Invalid PStateField to do a imm move to");
break;
}
EncodeSystemInst(0, op1, 4, imm, op2, WSP);
@ -1197,7 +1192,7 @@ static void GetSystemReg(PStateField field, int& o0, int& op1, int& CRn, int& CR
op2 = 0;
break;
default:
_assert_msg_(DYNA_REC, false, "Invalid PStateField to do a register move from/to");
ASSERT_MSG(DYNA_REC, false, "Invalid PStateField to do a register move from/to");
break;
}
}
@ -1205,7 +1200,7 @@ static void GetSystemReg(PStateField field, int& o0, int& op1, int& CRn, int& CR
void ARM64XEmitter::_MSR(PStateField field, ARM64Reg Rt)
{
int o0 = 0, op1 = 0, CRn = 0, CRm = 0, op2 = 0;
_assert_msg_(DYNA_REC, Is64Bit(Rt), "MSR: Rt must be 64-bit");
ASSERT_MSG(DYNA_REC, Is64Bit(Rt), "MSR: Rt must be 64-bit");
GetSystemReg(field, o0, op1, CRn, CRm, op2);
EncodeSystemInst(o0, op1, CRn, CRm, op2, DecodeReg(Rt));
}
@ -1213,14 +1208,14 @@ void ARM64XEmitter::_MSR(PStateField field, ARM64Reg Rt)
void ARM64XEmitter::MRS(ARM64Reg Rt, PStateField field)
{
int o0 = 0, op1 = 0, CRn = 0, CRm = 0, op2 = 0;
_assert_msg_(DYNA_REC, Is64Bit(Rt), "MRS: Rt must be 64-bit");
ASSERT_MSG(DYNA_REC, Is64Bit(Rt), "MRS: Rt must be 64-bit");
GetSystemReg(field, o0, op1, CRn, CRm, op2);
EncodeSystemInst(o0 | 4, op1, CRn, CRm, op2, DecodeReg(Rt));
}
void ARM64XEmitter::CNTVCT(Arm64Gen::ARM64Reg Rt)
{
_assert_msg_(DYNA_REC, Is64Bit(Rt), "CNTVCT: Rt must be 64-bit");
ASSERT_MSG(DYNA_REC, Is64Bit(Rt), "CNTVCT: Rt must be 64-bit");
// MRS <Xt>, CNTVCT_EL0 ; Read CNTVCT_EL0 into Xt
EncodeSystemInst(3 | 4, 3, 0xe, 0, 2, DecodeReg(Rt));
@ -1542,7 +1537,7 @@ void ARM64XEmitter::MOV(ARM64Reg Rd, ARM64Reg Rm)
if (IsGPR(Rd) && IsGPR(Rm))
ORR(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, ArithOption(Rm, ST_LSL, 0));
else
_assert_msg_(DYNA_REC, false, "Non-GPRs not supported in MOV");
ASSERT_MSG(DYNA_REC, false, "Non-GPRs not supported in MOV");
}
void ARM64XEmitter::MVN(ARM64Reg Rd, ARM64Reg Rm)
{
@ -1643,17 +1638,17 @@ void ARM64XEmitter::UBFM(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms)
void ARM64XEmitter::BFI(ARM64Reg Rd, ARM64Reg Rn, u32 lsb, u32 width)
{
u32 size = Is64Bit(Rn) ? 64 : 32;
_assert_msg_(DYNA_REC, (lsb + width) <= size,
"%s passed lsb %d and width %d which is greater than the register size!",
__FUNCTION__, lsb, width);
ASSERT_MSG(DYNA_REC, (lsb + width) <= size,
"%s passed lsb %d and width %d which is greater than the register size!", __FUNCTION__,
lsb, width);
EncodeBitfieldMOVInst(1, Rd, Rn, (size - lsb) % size, width - 1);
}
void ARM64XEmitter::UBFIZ(ARM64Reg Rd, ARM64Reg Rn, u32 lsb, u32 width)
{
u32 size = Is64Bit(Rn) ? 64 : 32;
_assert_msg_(DYNA_REC, (lsb + width) <= size,
"%s passed lsb %d and width %d which is greater than the register size!",
__FUNCTION__, lsb, width);
ASSERT_MSG(DYNA_REC, (lsb + width) <= size,
"%s passed lsb %d and width %d which is greater than the register size!", __FUNCTION__,
lsb, width);
EncodeBitfieldMOVInst(2, Rd, Rn, (size - lsb) % size, width - 1);
}
void ARM64XEmitter::EXTR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, u32 shift)
@ -1675,7 +1670,7 @@ void ARM64XEmitter::SXTH(ARM64Reg Rd, ARM64Reg Rn)
}
void ARM64XEmitter::SXTW(ARM64Reg Rd, ARM64Reg Rn)
{
_assert_msg_(DYNA_REC, Is64Bit(Rd), "%s requires 64bit register as destination", __FUNCTION__);
ASSERT_MSG(DYNA_REC, Is64Bit(Rd), "%s requires 64bit register as destination", __FUNCTION__);
SBFM(Rd, Rn, 0, 31);
}
void ARM64XEmitter::UXTB(ARM64Reg Rd, ARM64Reg Rn)
@ -1966,7 +1961,7 @@ void ARM64XEmitter::LDUR(ARM64Reg Rt, ARM64Reg Rn, s32 imm)
}
void ARM64XEmitter::LDURSW(ARM64Reg Rt, ARM64Reg Rn, s32 imm)
{
_assert_msg_(DYNA_REC, !Is64Bit(Rt), "%s must have a 64bit destination register!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, !Is64Bit(Rt), "%s must have a 64bit destination register!", __FUNCTION__);
EncodeLoadStoreUnscaled(2, 2, Rt, Rn, imm);
}
@ -2117,7 +2112,7 @@ void ARM64XEmitter::ABI_PushRegisters(BitSet32 registers)
for (int i = 0; i < (num_regs - 1) / 2; i++)
STP(INDEX_SIGNED, (ARM64Reg)(X0 + *it++), (ARM64Reg)(X0 + *it++), SP, 16 * (i + 1));
_assert_msg_(DYNA_REC, it == registers.end(), "%s registers don't match.", __FUNCTION__);
ASSERT_MSG(DYNA_REC, it == registers.end(), "%s registers don't match.", __FUNCTION__);
}
void ARM64XEmitter::ABI_PopRegisters(BitSet32 registers, BitSet32 ignore_mask)
@ -2148,7 +2143,7 @@ void ARM64XEmitter::ABI_PopRegisters(BitSet32 registers, BitSet32 ignore_mask)
else
LDP(INDEX_POST, first, second, SP, stack_size);
_assert_msg_(DYNA_REC, it == registers.end(), "%s registers don't match.", __FUNCTION__);
ASSERT_MSG(DYNA_REC, it == registers.end(), "%s registers don't match.", __FUNCTION__);
}
// Float Emitter
@ -2173,11 +2168,11 @@ void ARM64FloatEmitter::EmitLoadStoreImmediate(u8 size, u32 opc, IndexType type,
if (type == INDEX_UNSIGNED)
{
_assert_msg_(DYNA_REC, !(imm & ((size - 1) >> 3)),
"%s(INDEX_UNSIGNED) immediate offset must be aligned to size! (%d) (%p)",
__FUNCTION__, imm, m_emit->GetCodePtr());
_assert_msg_(DYNA_REC, imm >= 0, "%s(INDEX_UNSIGNED) immediate offset must be positive!",
__FUNCTION__);
ASSERT_MSG(DYNA_REC, !(imm & ((size - 1) >> 3)),
"%s(INDEX_UNSIGNED) immediate offset must be aligned to size! (%d) (%p)",
__FUNCTION__, imm, m_emit->GetCodePtr());
ASSERT_MSG(DYNA_REC, imm >= 0, "%s(INDEX_UNSIGNED) immediate offset must be positive!",
__FUNCTION__);
if (size == 16)
imm >>= 1;
else if (size == 32)
@ -2190,8 +2185,8 @@ void ARM64FloatEmitter::EmitLoadStoreImmediate(u8 size, u32 opc, IndexType type,
}
else
{
_assert_msg_(DYNA_REC, !(imm < -256 || imm > 255),
"%s immediate offset must be within range of -256 to 256!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, !(imm < -256 || imm > 255),
"%s immediate offset must be within range of -256 to 256!", __FUNCTION__);
encoded_imm = (imm & 0x1FF) << 2;
if (type == INDEX_POST)
encoded_imm |= 1;
@ -2206,8 +2201,7 @@ void ARM64FloatEmitter::EmitLoadStoreImmediate(u8 size, u32 opc, IndexType type,
void ARM64FloatEmitter::EmitScalar2Source(bool M, bool S, u32 type, u32 opcode, ARM64Reg Rd,
ARM64Reg Rn, ARM64Reg Rm)
{
_assert_msg_(DYNA_REC, !IsQuad(Rd), "%s only supports double and single registers!",
__FUNCTION__);
ASSERT_MSG(DYNA_REC, !IsQuad(Rd), "%s only supports double and single registers!", __FUNCTION__);
Rd = DecodeReg(Rd);
Rn = DecodeReg(Rn);
Rm = DecodeReg(Rm);
@ -2219,7 +2213,7 @@ void ARM64FloatEmitter::EmitScalar2Source(bool M, bool S, u32 type, u32 opcode,
void ARM64FloatEmitter::EmitThreeSame(bool U, u32 size, u32 opcode, ARM64Reg Rd, ARM64Reg Rn,
ARM64Reg Rm)
{
_assert_msg_(DYNA_REC, !IsSingle(Rd), "%s doesn't support singles!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, !IsSingle(Rd), "%s doesn't support singles!", __FUNCTION__);
bool quad = IsQuad(Rd);
Rd = DecodeReg(Rd);
Rn = DecodeReg(Rn);
@ -2240,7 +2234,7 @@ void ARM64FloatEmitter::EmitCopy(bool Q, u32 op, u32 imm5, u32 imm4, ARM64Reg Rd
void ARM64FloatEmitter::Emit2RegMisc(bool Q, bool U, u32 size, u32 opcode, ARM64Reg Rd, ARM64Reg Rn)
{
_assert_msg_(DYNA_REC, !IsSingle(Rd), "%s doesn't support singles!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, !IsSingle(Rd), "%s doesn't support singles!", __FUNCTION__);
Rd = DecodeReg(Rd);
Rn = DecodeReg(Rn);
@ -2251,7 +2245,7 @@ void ARM64FloatEmitter::Emit2RegMisc(bool Q, bool U, u32 size, u32 opcode, ARM64
void ARM64FloatEmitter::EmitLoadStoreSingleStructure(bool L, bool R, u32 opcode, bool S, u32 size,
ARM64Reg Rt, ARM64Reg Rn)
{
_assert_msg_(DYNA_REC, !IsSingle(Rt), "%s doesn't support singles!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, !IsSingle(Rt), "%s doesn't support singles!", __FUNCTION__);
bool quad = IsQuad(Rt);
Rt = DecodeReg(Rt);
Rn = DecodeReg(Rn);
@ -2263,7 +2257,7 @@ void ARM64FloatEmitter::EmitLoadStoreSingleStructure(bool L, bool R, u32 opcode,
void ARM64FloatEmitter::EmitLoadStoreSingleStructure(bool L, bool R, u32 opcode, bool S, u32 size,
ARM64Reg Rt, ARM64Reg Rn, ARM64Reg Rm)
{
_assert_msg_(DYNA_REC, !IsSingle(Rt), "%s doesn't support singles!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, !IsSingle(Rt), "%s doesn't support singles!", __FUNCTION__);
bool quad = IsQuad(Rt);
Rt = DecodeReg(Rt);
Rn = DecodeReg(Rn);
@ -2275,7 +2269,7 @@ void ARM64FloatEmitter::EmitLoadStoreSingleStructure(bool L, bool R, u32 opcode,
void ARM64FloatEmitter::Emit1Source(bool M, bool S, u32 type, u32 opcode, ARM64Reg Rd, ARM64Reg Rn)
{
_assert_msg_(DYNA_REC, !IsQuad(Rd), "%s doesn't support vector!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, !IsQuad(Rd), "%s doesn't support vector!", __FUNCTION__);
Rd = DecodeReg(Rd);
Rn = DecodeReg(Rn);
@ -2286,7 +2280,7 @@ void ARM64FloatEmitter::Emit1Source(bool M, bool S, u32 type, u32 opcode, ARM64R
void ARM64FloatEmitter::EmitConversion(bool sf, bool S, u32 type, u32 rmode, u32 opcode,
ARM64Reg Rd, ARM64Reg Rn)
{
_assert_msg_(DYNA_REC, Rn <= SP, "%s only supports GPR as source!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, Rn <= SP, "%s only supports GPR as source!", __FUNCTION__);
Rd = DecodeReg(Rd);
Rn = DecodeReg(Rn);
@ -2297,7 +2291,7 @@ void ARM64FloatEmitter::EmitConversion(bool sf, bool S, u32 type, u32 rmode, u32
void ARM64FloatEmitter::EmitConvertScalarToInt(ARM64Reg Rd, ARM64Reg Rn, RoundingMode round,
bool sign)
{
_dbg_assert_msg_(DYNA_REC, IsScalar(Rn), "fcvts: Rn must be floating point");
DEBUG_ASSERT_MSG(DYNA_REC, IsScalar(Rn), "fcvts: Rn must be floating point");
if (IsGPR(Rd))
{
// Use the encoding that transfers the result to a GPR.
@ -2382,7 +2376,7 @@ void ARM64FloatEmitter::EmitConversion2(bool sf, bool S, bool direction, u32 typ
void ARM64FloatEmitter::EmitCompare(bool M, bool S, u32 op, u32 opcode2, ARM64Reg Rn, ARM64Reg Rm)
{
_assert_msg_(DYNA_REC, !IsQuad(Rn), "%s doesn't support vector!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, !IsQuad(Rn), "%s doesn't support vector!", __FUNCTION__);
bool is_double = IsDouble(Rn);
Rn = DecodeReg(Rn);
@ -2395,7 +2389,7 @@ void ARM64FloatEmitter::EmitCompare(bool M, bool S, u32 op, u32 opcode2, ARM64Re
void ARM64FloatEmitter::EmitCondSelect(bool M, bool S, CCFlags cond, ARM64Reg Rd, ARM64Reg Rn,
ARM64Reg Rm)
{
_assert_msg_(DYNA_REC, !IsQuad(Rd), "%s doesn't support vector!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, !IsQuad(Rd), "%s doesn't support vector!", __FUNCTION__);
bool is_double = IsDouble(Rd);
Rd = DecodeReg(Rd);
@ -2408,7 +2402,7 @@ void ARM64FloatEmitter::EmitCondSelect(bool M, bool S, CCFlags cond, ARM64Reg Rd
void ARM64FloatEmitter::EmitPermute(u32 size, u32 op, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
{
_assert_msg_(DYNA_REC, !IsSingle(Rd), "%s doesn't support singles!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, !IsSingle(Rd), "%s doesn't support singles!", __FUNCTION__);
bool quad = IsQuad(Rd);
@ -2430,7 +2424,7 @@ void ARM64FloatEmitter::EmitPermute(u32 size, u32 op, ARM64Reg Rd, ARM64Reg Rn,
void ARM64FloatEmitter::EmitScalarImm(bool M, bool S, u32 type, u32 imm5, ARM64Reg Rd, u32 imm8)
{
_assert_msg_(DYNA_REC, !IsQuad(Rd), "%s doesn't support vector!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, !IsQuad(Rd), "%s doesn't support vector!", __FUNCTION__);
bool is_double = !IsSingle(Rd);
@ -2443,7 +2437,7 @@ void ARM64FloatEmitter::EmitScalarImm(bool M, bool S, u32 type, u32 imm5, ARM64R
void ARM64FloatEmitter::EmitShiftImm(bool Q, bool U, u32 immh, u32 immb, u32 opcode, ARM64Reg Rd,
ARM64Reg Rn)
{
_assert_msg_(DYNA_REC, immh, "%s bad encoding! Can't have zero immh", __FUNCTION__);
ASSERT_MSG(DYNA_REC, immh, "%s bad encoding! Can't have zero immh", __FUNCTION__);
Rd = DecodeReg(Rd);
Rn = DecodeReg(Rn);
@ -2506,7 +2500,7 @@ void ARM64FloatEmitter::EmitLoadStoreMultipleStructurePost(u32 size, bool L, u32
void ARM64FloatEmitter::EmitScalar1Source(bool M, bool S, u32 type, u32 opcode, ARM64Reg Rd,
ARM64Reg Rn)
{
_assert_msg_(DYNA_REC, !IsQuad(Rd), "%s doesn't support vector!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, !IsQuad(Rd), "%s doesn't support vector!", __FUNCTION__);
Rd = DecodeReg(Rd);
Rn = DecodeReg(Rn);
@ -2530,8 +2524,8 @@ void ARM64FloatEmitter::EmitVectorxElement(bool U, u32 size, bool L, u32 opcode,
void ARM64FloatEmitter::EmitLoadStoreUnscaled(u32 size, u32 op, ARM64Reg Rt, ARM64Reg Rn, s32 imm)
{
_assert_msg_(DYNA_REC, !(imm < -256 || imm > 255), "%s received too large offset: %d",
__FUNCTION__, imm);
ASSERT_MSG(DYNA_REC, !(imm < -256 || imm > 255), "%s received too large offset: %d", __FUNCTION__,
imm);
Rt = DecodeReg(Rt);
Rn = DecodeReg(Rn);
@ -2556,25 +2550,25 @@ void ARM64FloatEmitter::EncodeLoadStorePair(u32 size, bool load, IndexType type,
type_encode = 0b011;
break;
case INDEX_UNSIGNED:
_assert_msg_(DYNA_REC, false, "%s doesn't support INDEX_UNSIGNED!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, false, "%s doesn't support INDEX_UNSIGNED!", __FUNCTION__);
break;
}
if (size == 128)
{
_assert_msg_(DYNA_REC, !(imm & 0xF), "%s received invalid offset 0x%x!", __FUNCTION__, imm);
ASSERT_MSG(DYNA_REC, !(imm & 0xF), "%s received invalid offset 0x%x!", __FUNCTION__, imm);
opc = 2;
imm >>= 4;
}
else if (size == 64)
{
_assert_msg_(DYNA_REC, !(imm & 0x7), "%s received invalid offset 0x%x!", __FUNCTION__, imm);
ASSERT_MSG(DYNA_REC, !(imm & 0x7), "%s received invalid offset 0x%x!", __FUNCTION__, imm);
opc = 1;
imm >>= 3;
}
else if (size == 32)
{
_assert_msg_(DYNA_REC, !(imm & 0x3), "%s received invalid offset 0x%x!", __FUNCTION__, imm);
ASSERT_MSG(DYNA_REC, !(imm & 0x3), "%s received invalid offset 0x%x!", __FUNCTION__, imm);
opc = 0;
imm >>= 2;
}
@ -2590,8 +2584,8 @@ void ARM64FloatEmitter::EncodeLoadStorePair(u32 size, bool load, IndexType type,
void ARM64FloatEmitter::EncodeLoadStoreRegisterOffset(u32 size, bool load, ARM64Reg Rt, ARM64Reg Rn,
ArithOption Rm)
{
_assert_msg_(DYNA_REC, Rm.GetType() == ArithOption::TYPE_EXTENDEDREG,
"%s must contain an extended reg as Rm!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, Rm.GetType() == ArithOption::TYPE_EXTENDEDREG,
"%s must contain an extended reg as Rm!", __FUNCTION__);
u32 encoded_size = 0;
u32 encoded_op = 0;
@ -2952,8 +2946,8 @@ void ARM64FloatEmitter::ST1(u8 size, ARM64Reg Rt, u8 index, ARM64Reg Rn, ARM64Re
// Loadstore multiple structure
void ARM64FloatEmitter::LD1(u8 size, u8 count, ARM64Reg Rt, ARM64Reg Rn)
{
_assert_msg_(DYNA_REC, !(count == 0 || count > 4), "%s must have a count of 1 to 4 registers!",
__FUNCTION__);
ASSERT_MSG(DYNA_REC, !(count == 0 || count > 4), "%s must have a count of 1 to 4 registers!",
__FUNCTION__);
u32 opcode = 0;
if (count == 1)
opcode = 0b111;
@ -2968,9 +2962,9 @@ void ARM64FloatEmitter::LD1(u8 size, u8 count, ARM64Reg Rt, ARM64Reg Rn)
void ARM64FloatEmitter::LD1(u8 size, u8 count, IndexType type, ARM64Reg Rt, ARM64Reg Rn,
ARM64Reg Rm)
{
_assert_msg_(DYNA_REC, !(count == 0 || count > 4), "%s must have a count of 1 to 4 registers!",
__FUNCTION__);
_assert_msg_(DYNA_REC, type == INDEX_POST, "%s only supports post indexing!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, !(count == 0 || count > 4), "%s must have a count of 1 to 4 registers!",
__FUNCTION__);
ASSERT_MSG(DYNA_REC, type == INDEX_POST, "%s only supports post indexing!", __FUNCTION__);
u32 opcode = 0;
if (count == 1)
@ -2985,8 +2979,8 @@ void ARM64FloatEmitter::LD1(u8 size, u8 count, IndexType type, ARM64Reg Rt, ARM6
}
void ARM64FloatEmitter::ST1(u8 size, u8 count, ARM64Reg Rt, ARM64Reg Rn)
{
_assert_msg_(DYNA_REC, !(count == 0 || count > 4), "%s must have a count of 1 to 4 registers!",
__FUNCTION__);
ASSERT_MSG(DYNA_REC, !(count == 0 || count > 4), "%s must have a count of 1 to 4 registers!",
__FUNCTION__);
u32 opcode = 0;
if (count == 1)
opcode = 0b111;
@ -3001,9 +2995,9 @@ void ARM64FloatEmitter::ST1(u8 size, u8 count, ARM64Reg Rt, ARM64Reg Rn)
void ARM64FloatEmitter::ST1(u8 size, u8 count, IndexType type, ARM64Reg Rt, ARM64Reg Rn,
ARM64Reg Rm)
{
_assert_msg_(DYNA_REC, !(count == 0 || count > 4), "%s must have a count of 1 to 4 registers!",
__FUNCTION__);
_assert_msg_(DYNA_REC, type == INDEX_POST, "%s only supports post indexing!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, !(count == 0 || count > 4), "%s must have a count of 1 to 4 registers!",
__FUNCTION__);
ASSERT_MSG(DYNA_REC, type == INDEX_POST, "%s only supports post indexing!", __FUNCTION__);
u32 opcode = 0;
if (count == 1)
@ -3026,7 +3020,7 @@ void ARM64FloatEmitter::FMOV(ARM64Reg Rd, ARM64Reg Rn, bool top)
}
else
{
_assert_msg_(DYNA_REC, !IsQuad(Rd) && !IsQuad(Rn), "FMOV can't move to/from quads");
ASSERT_MSG(DYNA_REC, !IsQuad(Rd) && !IsQuad(Rn), "FMOV can't move to/from quads");
int rmode = 0;
int opcode = 6;
int sf = 0;
@ -3042,7 +3036,7 @@ void ARM64FloatEmitter::FMOV(ARM64Reg Rd, ARM64Reg Rn, bool top)
else
{
// TODO
_assert_msg_(DYNA_REC, 0, "FMOV: Unhandled case");
ASSERT_MSG(DYNA_REC, 0, "FMOV: Unhandled case");
}
Rd = DecodeReg(Rd);
Rn = DecodeReg(Rn);
@ -3405,9 +3399,9 @@ void ARM64FloatEmitter::INS(u8 size, ARM64Reg Rd, u8 index1, ARM64Reg Rn, u8 ind
void ARM64FloatEmitter::UMOV(u8 size, ARM64Reg Rd, ARM64Reg Rn, u8 index)
{
bool b64Bit = Is64Bit(Rd);
_assert_msg_(DYNA_REC, Rd < SP, "%s destination must be a GPR!", __FUNCTION__);
_assert_msg_(DYNA_REC, !(b64Bit && size != 64),
"%s must have a size of 64 when destination is 64bit!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, Rd < SP, "%s destination must be a GPR!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, !(b64Bit && size != 64),
"%s must have a size of 64 when destination is 64bit!", __FUNCTION__);
u32 imm5 = 0;
if (size == 8)
@ -3436,9 +3430,8 @@ void ARM64FloatEmitter::UMOV(u8 size, ARM64Reg Rd, ARM64Reg Rn, u8 index)
void ARM64FloatEmitter::SMOV(u8 size, ARM64Reg Rd, ARM64Reg Rn, u8 index)
{
bool b64Bit = Is64Bit(Rd);
_assert_msg_(DYNA_REC, Rd < SP, "%s destination must be a GPR!", __FUNCTION__);
_assert_msg_(DYNA_REC, size != 64, "%s doesn't support 64bit destination. Use UMOV!",
__FUNCTION__);
ASSERT_MSG(DYNA_REC, Rd < SP, "%s destination must be a GPR!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, size != 64, "%s doesn't support 64bit destination. Use UMOV!", __FUNCTION__);
u32 imm5 = 0;
if (size == 8)
@ -3670,8 +3663,8 @@ void ARM64FloatEmitter::UXTL2(u8 src_size, ARM64Reg Rd, ARM64Reg Rn)
void ARM64FloatEmitter::SSHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper)
{
_assert_msg_(DYNA_REC, shift < src_size, "%s shift amount must less than the element size!",
__FUNCTION__);
ASSERT_MSG(DYNA_REC, shift < src_size, "%s shift amount must less than the element size!",
__FUNCTION__);
u32 immh = 0;
u32 immb = shift & 0xFFF;
@ -3693,8 +3686,8 @@ void ARM64FloatEmitter::SSHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift,
void ARM64FloatEmitter::USHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper)
{
_assert_msg_(DYNA_REC, shift < src_size, "%s shift amount must less than the element size!",
__FUNCTION__);
ASSERT_MSG(DYNA_REC, shift < src_size, "%s shift amount must less than the element size!",
__FUNCTION__);
u32 immh = 0;
u32 immb = shift & 0xFFF;
@ -3716,8 +3709,8 @@ void ARM64FloatEmitter::USHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift,
void ARM64FloatEmitter::SHRN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper)
{
_assert_msg_(DYNA_REC, shift < dest_size, "%s shift amount must less than the element size!",
__FUNCTION__);
ASSERT_MSG(DYNA_REC, shift < dest_size, "%s shift amount must less than the element size!",
__FUNCTION__);
u32 immh = 0;
u32 immb = shift & 0xFFF;
@ -3750,8 +3743,8 @@ void ARM64FloatEmitter::UXTL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, bool upper)
// vector x indexed element
void ARM64FloatEmitter::FMUL(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, u8 index)
{
_assert_msg_(DYNA_REC, size == 32 || size == 64, "%s only supports 32bit or 64bit size!",
__FUNCTION__);
ASSERT_MSG(DYNA_REC, size == 32 || size == 64, "%s only supports 32bit or 64bit size!",
__FUNCTION__);
bool L = false;
bool H = false;
@ -3770,8 +3763,8 @@ void ARM64FloatEmitter::FMUL(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, u8
void ARM64FloatEmitter::FMLA(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, u8 index)
{
_assert_msg_(DYNA_REC, size == 32 || size == 64, "%s only supports 32bit or 64bit size!",
__FUNCTION__);
ASSERT_MSG(DYNA_REC, size == 32 || size == 64, "%s only supports 32bit or 64bit size!",
__FUNCTION__);
bool L = false;
bool H = false;
@ -3797,26 +3790,24 @@ void ARM64FloatEmitter::MOVI(u8 size, ARM64Reg Rd, u64 imm, u8 shift)
u8 abcdefgh = imm & 0xFF;
if (size == 8)
{
_assert_msg_(DYNA_REC, shift == 0, "%s(size8) doesn't support shift!", __FUNCTION__);
_assert_msg_(DYNA_REC, !(imm & ~0xFFULL), "%s(size8) only supports 8bit values!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, shift == 0, "%s(size8) doesn't support shift!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, !(imm & ~0xFFULL), "%s(size8) only supports 8bit values!", __FUNCTION__);
}
else if (size == 16)
{
_assert_msg_(DYNA_REC, shift == 0 || shift == 8, "%s(size16) only supports shift of {0, 8}!",
__FUNCTION__);
_assert_msg_(DYNA_REC, !(imm & ~0xFFULL), "%s(size16) only supports 8bit values!",
__FUNCTION__);
ASSERT_MSG(DYNA_REC, shift == 0 || shift == 8, "%s(size16) only supports shift of {0, 8}!",
__FUNCTION__);
ASSERT_MSG(DYNA_REC, !(imm & ~0xFFULL), "%s(size16) only supports 8bit values!", __FUNCTION__);
if (shift == 8)
cmode |= 2;
}
else if (size == 32)
{
_assert_msg_(DYNA_REC, shift == 0 || shift == 8 || shift == 16 || shift == 24,
"%s(size32) only supports shift of {0, 8, 16, 24}!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, shift == 0 || shift == 8 || shift == 16 || shift == 24,
"%s(size32) only supports shift of {0, 8, 16, 24}!", __FUNCTION__);
// XXX: Implement support for MOVI - shifting ones variant
_assert_msg_(DYNA_REC, !(imm & ~0xFFULL), "%s(size32) only supports 8bit values!",
__FUNCTION__);
ASSERT_MSG(DYNA_REC, !(imm & ~0xFFULL), "%s(size32) only supports 8bit values!", __FUNCTION__);
switch (shift)
{
case 8:
@ -3834,7 +3825,7 @@ void ARM64FloatEmitter::MOVI(u8 size, ARM64Reg Rd, u64 imm, u8 shift)
}
else // 64
{
_assert_msg_(DYNA_REC, shift == 0, "%s(size64) doesn't support shift!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, shift == 0, "%s(size64) doesn't support shift!", __FUNCTION__);
op = 1;
cmode = 0xE;
@ -3842,8 +3833,7 @@ void ARM64FloatEmitter::MOVI(u8 size, ARM64Reg Rd, u64 imm, u8 shift)
for (int i = 0; i < 8; ++i)
{
u8 tmp = (imm >> (i << 3)) & 0xFF;
_assert_msg_(DYNA_REC, tmp == 0xFF || tmp == 0, "%s(size64) Invalid immediate!",
__FUNCTION__);
ASSERT_MSG(DYNA_REC, tmp == 0xFF || tmp == 0, "%s(size64) Invalid immediate!", __FUNCTION__);
if (tmp == 0xFF)
abcdefgh |= (1 << i);
}
@ -3858,16 +3848,16 @@ void ARM64FloatEmitter::BIC(u8 size, ARM64Reg Rd, u8 imm, u8 shift)
u8 op = 1;
if (size == 16)
{
_assert_msg_(DYNA_REC, shift == 0 || shift == 8, "%s(size16) only supports shift of {0, 8}!",
__FUNCTION__);
ASSERT_MSG(DYNA_REC, shift == 0 || shift == 8, "%s(size16) only supports shift of {0, 8}!",
__FUNCTION__);
if (shift == 8)
cmode |= 2;
}
else if (size == 32)
{
_assert_msg_(DYNA_REC, shift == 0 || shift == 8 || shift == 16 || shift == 24,
"%s(size32) only supports shift of {0, 8, 16, 24}!", __FUNCTION__);
ASSERT_MSG(DYNA_REC, shift == 0 || shift == 8 || shift == 16 || shift == 24,
"%s(size32) only supports shift of {0, 8, 16, 24}!", __FUNCTION__);
// XXX: Implement support for MOVI - shifting ones variant
switch (shift)
{
@ -3885,7 +3875,9 @@ void ARM64FloatEmitter::BIC(u8 size, ARM64Reg Rd, u8 imm, u8 shift)
}
}
else
_assert_msg_(DYNA_REC, false, "%s only supports size of {16, 32}!", __FUNCTION__);
{
ASSERT_MSG(DYNA_REC, false, "%s only supports size of {16, 32}!", __FUNCTION__);
}
EncodeModImm(Q, op, cmode, 0, Rd, imm);
}
@ -4065,9 +4057,9 @@ void ARM64XEmitter::ANDI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch)
}
else
{
_assert_msg_(DYNA_REC, scratch != INVALID_REG,
"ANDI2R - failed to construct logical immediate value from %08x, need scratch",
(u32)imm);
ASSERT_MSG(DYNA_REC, scratch != INVALID_REG,
"ANDI2R - failed to construct logical immediate value from %08x, need scratch",
(u32)imm);
MOVI2R(scratch, imm);
AND(Rd, Rn, scratch);
}
@ -4082,9 +4074,9 @@ void ARM64XEmitter::ORRI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch)
}
else
{
_assert_msg_(DYNA_REC, scratch != INVALID_REG,
"ORRI2R - failed to construct logical immediate value from %08x, need scratch",
(u32)imm);
ASSERT_MSG(DYNA_REC, scratch != INVALID_REG,
"ORRI2R - failed to construct logical immediate value from %08x, need scratch",
(u32)imm);
MOVI2R(scratch, imm);
ORR(Rd, Rn, scratch);
}
@ -4099,9 +4091,9 @@ void ARM64XEmitter::EORI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch)
}
else
{
_assert_msg_(DYNA_REC, scratch != INVALID_REG,
"EORI2R - failed to construct logical immediate value from %08x, need scratch",
(u32)imm);
ASSERT_MSG(DYNA_REC, scratch != INVALID_REG,
"EORI2R - failed to construct logical immediate value from %08x, need scratch",
(u32)imm);
MOVI2R(scratch, imm);
EOR(Rd, Rn, scratch);
}
@ -4116,9 +4108,9 @@ void ARM64XEmitter::ANDSI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch)
}
else
{
_assert_msg_(DYNA_REC, scratch != INVALID_REG,
"ANDSI2R - failed to construct logical immediate value from %08x, need scratch",
(u32)imm);
ASSERT_MSG(DYNA_REC, scratch != INVALID_REG,
"ANDSI2R - failed to construct logical immediate value from %08x, need scratch",
(u32)imm);
MOVI2R(scratch, imm);
ANDS(Rd, Rn, scratch);
}
@ -4190,9 +4182,9 @@ void ARM64XEmitter::ADDI2R_internal(ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool nega
return;
}
_assert_msg_(DYNA_REC, has_scratch,
"ADDI2R - failed to construct arithmetic immediate value from %08x, need scratch",
(u32)imm);
ASSERT_MSG(DYNA_REC, has_scratch,
"ADDI2R - failed to construct arithmetic immediate value from %08x, need scratch",
(u32)imm);
negative ^= MOVI2R2(scratch, imm, imm_neg);
switch ((negative << 1) | flags)
@ -4338,7 +4330,7 @@ bool FPImm8FromFloat(float value, uint8_t* immOut)
void ARM64FloatEmitter::MOVI2F(ARM64Reg Rd, float value, ARM64Reg scratch, bool negate)
{
_assert_msg_(DYNA_REC, !IsDouble(Rd), "MOVI2F does not yet support double precision");
ASSERT_MSG(DYNA_REC, !IsDouble(Rd), "MOVI2F does not yet support double precision");
uint8_t imm8;
if (value == 0.0)
{
@ -4354,8 +4346,8 @@ void ARM64FloatEmitter::MOVI2F(ARM64Reg Rd, float value, ARM64Reg scratch, bool
}
else
{
_assert_msg_(DYNA_REC, scratch != INVALID_REG,
"Failed to find a way to generate FP immediate %f without scratch", value);
ASSERT_MSG(DYNA_REC, scratch != INVALID_REG,
"Failed to find a way to generate FP immediate %f without scratch", value);
u32 ival;
if (negate)
value = -value;

4
Source/Core/Common/Arm64Emitter.h
View File

@ -490,7 +490,7 @@ public:
return (m_shifttype << 22) | (m_shift << 10);
break;
default:
_dbg_assert_msg_(DYNA_REC, false, "Invalid type in GetData");
DEBUG_ASSERT_MSG(DYNA_REC, false, "Invalid type in GetData");
break;
}
return 0;
@ -846,7 +846,7 @@ public:
template <class P>
void MOVP2R(ARM64Reg Rd, P* ptr)
{
_assert_msg_(DYNA_REC, Is64Bit(Rd), "Can't store pointers in 32-bit registers");
ASSERT_MSG(DYNA_REC, Is64Bit(Rd), "Can't store pointers in 32-bit registers");
MOVI2R(Rd, (uintptr_t)ptr);
}

20
Source/Core/Common/Assert.h
View File

@ -10,14 +10,14 @@
#include "Common/MsgHandler.h"
#ifdef _WIN32
#define _assert_msg_(_t_, _a_, _fmt_, ...) \
#define ASSERT_MSG(_t_, _a_, _fmt_, ...) \
if (!(_a_)) \
{ \
if (!PanicYesNo(_fmt_ "\n\nIgnore and continue?", __VA_ARGS__)) \
Crash(); \
}
#define _dbg_assert_msg_(_t_, _a_, _msg_, ...) \
#define DEBUG_ASSERT_MSG(_t_, _a_, _msg_, ...) \
if (MAX_LOGLEVEL >= LogTypes::LOG_LEVELS::LDEBUG && !(_a_)) \
{ \
ERROR_LOG(_t_, _msg_, __VA_ARGS__); \
@ -25,14 +25,14 @@
Crash(); \
}
#else
#define _assert_msg_(_t_, _a_, _fmt_, ...) \
#define ASSERT_MSG(_t_, _a_, _fmt_, ...) \
if (!(_a_)) \
{ \
if (!PanicYesNo(_fmt_, ##__VA_ARGS__)) \
Crash(); \
}
#define _dbg_assert_msg_(_t_, _a_, _msg_, ...) \
#define DEBUG_ASSERT_MSG(_t_, _a_, _msg_, ...) \
if (MAX_LOGLEVEL >= LogTypes::LOG_LEVELS::LDEBUG && !(_a_)) \
{ \
ERROR_LOG(_t_, _msg_, ##__VA_ARGS__); \
@ -41,11 +41,11 @@
}
#endif
#define _assert_(_a_) \
_assert_msg_(MASTER_LOG, _a_, \
_trans("An error occurred.\n\n Line: %d\n File: %s\n\nIgnore and continue?"), \
__LINE__, __FILE__)
#define ASSERT(_a_) \
ASSERT_MSG(MASTER_LOG, _a_, \
_trans("An error occurred.\n\n Line: %d\n File: %s\n\nIgnore and continue?"), \
__LINE__, __FILE__)
#define _dbg_assert_(_t_, _a_) \
#define DEBUG_ASSERT(_t_, _a_) \
if (MAX_LOGLEVEL >= LogTypes::LOG_LEVELS::LDEBUG) \
_assert_(_a_)
ASSERT(_a_)

2
Source/Core/Common/ChunkFile.h
View File

@ -285,7 +285,7 @@ private:
break;
case MODE_VERIFY:
_dbg_assert_msg_(COMMON, !memcmp(data, *ptr, size),
DEBUG_ASSERT_MSG(COMMON, !memcmp(data, *ptr, size),
"Savestate verification failure: buf %p != %p (size %u).\n", data, *ptr,
size);
break;

6
Source/Core/Common/CodeBlock.h
View File

@ -67,7 +67,7 @@ public:
// Call this when shutting down. Don't rely on the destructor, even though it'll do the job.
void FreeCodeSpace()
{
_assert_(!m_is_child);
ASSERT(!m_is_child);
Common::FreeMemoryPages(region, total_region_size);
region = nullptr;
region_size = 0;
@ -87,7 +87,7 @@ public:
void ResetCodePtr() { T::SetCodePtr(region); }
size_t GetSpaceLeft() const
{
_assert_(static_cast<size_t>(T::GetCodePtr() - region) < region_size);
ASSERT(static_cast<size_t>(T::GetCodePtr() - region) < region_size);
return region_size - (T::GetCodePtr() - region);
}
@ -100,7 +100,7 @@ public:
bool HasChildren() const { return region_size != total_region_size; }
u8* AllocChildCodeSpace(size_t child_size)
{
_assert_msg_(DYNA_REG, child_size < GetSpaceLeft(), "Insufficient space for child allocation.");
ASSERT_MSG(DYNA_REG, child_size < GetSpaceLeft(), "Insufficient space for child allocation.");
u8* child_region = region + region_size - child_size;
region_size -= child_size;
return child_region;

2
Source/Core/Common/FileUtil.cpp
View File

@ -715,7 +715,7 @@ std::string GetSysDirectory()
sysDir = GetExeDirectory() + DIR_SEP + SYSDATA_DIR;
#elif defined ANDROID
sysDir = s_android_sys_directory;
_assert_msg_(COMMON, !sysDir.empty(), "Sys directory has not been set");
ASSERT_MSG(COMMON, !sysDir.empty(), "Sys directory has not been set");
#else
sysDir = SYSDATA_DIR;
#endif

2
Source/Core/Common/SysConf.cpp
View File

@ -31,7 +31,7 @@ static size_t GetNonArrayEntrySize(SysConf::Entry::Type type)
case SysConf::Entry::Type::LongLong:
return 8;
default:
_assert_(false);
ASSERT(false);
return 0;
}
}

2
Source/Core/Common/SysConf.h
View File

@ -55,7 +55,7 @@ public:
template <typename T>
void SetData(T value)
{
_assert_(sizeof(value) == bytes.size());
ASSERT(sizeof(value) == bytes.size());
std::memcpy(bytes.data(), &value, bytes.size());
}

140
Source/Core/Common/x64Emitter.cpp
View File

@ -122,8 +122,8 @@ void XEmitter::ReserveCodeSpace(int bytes)
const u8* XEmitter::AlignCodeTo(size_t alignment)
{
_assert_msg_(DYNA_REC, alignment != 0 && (alignment & (alignment - 1)) == 0,
"Alignment must be power of two");
ASSERT_MSG(DYNA_REC, alignment != 0 && (alignment & (alignment - 1)) == 0,
"Alignment must be power of two");
u64 c = reinterpret_cast<u64>(code) & (alignment - 1);
if (c)
ReserveCodeSpace(static_cast<int>(alignment - c));
@ -150,7 +150,7 @@ const u8* XEmitter::AlignCodePage()
// causing a subtle JIT bug.
void XEmitter::CheckFlags()
{
_assert_msg_(DYNA_REC, !flags_locked, "Attempt to modify flags while flags locked!");
ASSERT_MSG(DYNA_REC, !flags_locked, "Attempt to modify flags while flags locked!");
}
void XEmitter::WriteModRM(int mod, int reg, int rm)
@ -187,8 +187,8 @@ void OpArg::WriteREX(XEmitter* emit, int opBits, int bits, int customOp) const
{
emit->Write8(op);
// Check the operation doesn't access AH, BH, CH, or DH.
_dbg_assert_(DYNA_REC, (offsetOrBaseReg & 0x100) == 0);
_dbg_assert_(DYNA_REC, (customOp & 0x100) == 0);
DEBUG_ASSERT(DYNA_REC, (offsetOrBaseReg & 0x100) == 0);
DEBUG_ASSERT(DYNA_REC, (customOp & 0x100) == 0);
}
}
@ -236,9 +236,9 @@ void OpArg::WriteRest(XEmitter* emit, int extraBytes, X64Reg _operandReg,
// TODO : add some checks
u64 ripAddr = (u64)emit->GetCodePtr() + 4 + extraBytes;
s64 distance = (s64)offset - (s64)ripAddr;
_assert_msg_(DYNA_REC,
(distance < 0x80000000LL && distance >= -0x80000000LL) || !warn_64bit_offset,
"WriteRest: op out of range (0x%" PRIx64 " uses 0x%" PRIx64 ")", ripAddr, offset);
ASSERT_MSG(DYNA_REC,
(distance < 0x80000000LL && distance >= -0x80000000LL) || !warn_64bit_offset,
"WriteRest: op out of range (0x%" PRIx64 " uses 0x%" PRIx64 ")", ripAddr, offset);
s32 offs = (s32)distance;
emit->Write32((u32)offs);
return;
@ -351,7 +351,7 @@ void OpArg::WriteRest(XEmitter* emit, int extraBytes, X64Reg _operandReg,
ss = 0;
break;
default:
_assert_msg_(DYNA_REC, 0, "Invalid scale for SIB byte");
ASSERT_MSG(DYNA_REC, 0, "Invalid scale for SIB byte");
ss = 0;
break;
}
@ -389,8 +389,8 @@ void XEmitter::JMP(const u8* addr, bool force5Bytes)
if (!force5Bytes)
{
s64 distance = (s64)(fn - ((u64)code + 2));
_assert_msg_(DYNA_REC, distance >= -0x80 && distance < 0x80,
"Jump target too far away, needs force5Bytes = true");
ASSERT_MSG(DYNA_REC, distance >= -0x80 && distance < 0x80,
"Jump target too far away, needs force5Bytes = true");
// 8 bits will do
Write8(0xEB);
Write8((u8)(s8)distance);
@ -399,8 +399,8 @@ void XEmitter::JMP(const u8* addr, bool force5Bytes)
{
s64 distance = (s64)(fn - ((u64)code + 5));
_assert_msg_(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL,
"Jump target too far away, needs indirect register");
ASSERT_MSG(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL,
"Jump target too far away, needs indirect register");
Write8(0xE9);
Write32((u32)(s32)distance);
}
@ -410,7 +410,7 @@ void XEmitter::JMPptr(const OpArg& arg2)
{
OpArg arg = arg2;
if (arg.IsImm())
_assert_msg_(DYNA_REC, 0, "JMPptr - Imm argument");
ASSERT_MSG(DYNA_REC, 0, "JMPptr - Imm argument");
arg.operandReg = 4;
arg.WriteREX(this, 0, 0);
Write8(0xFF);
@ -428,7 +428,7 @@ void XEmitter::JMPself()
void XEmitter::CALLptr(OpArg arg)
{
if (arg.IsImm())
_assert_msg_(DYNA_REC, 0, "CALLptr - Imm argument");
ASSERT_MSG(DYNA_REC, 0, "CALLptr - Imm argument");
arg.operandReg = 2;
arg.WriteREX(this, 0, 0);
Write8(0xFF);
@ -438,8 +438,8 @@ void XEmitter::CALLptr(OpArg arg)
void XEmitter::CALL(const void* fnptr)
{
u64 distance = u64(fnptr) - (u64(code) + 5);
_assert_msg_(DYNA_REC, distance < 0x0000000080000000ULL || distance >= 0xFFFFFFFF80000000ULL,
"CALL out of range (%p calls %p)", code, fnptr);
ASSERT_MSG(DYNA_REC, distance < 0x0000000080000000ULL || distance >= 0xFFFFFFFF80000000ULL,
"CALL out of range (%p calls %p)", code, fnptr);
Write8(0xE8);
Write32(u32(distance));
}
@ -500,8 +500,8 @@ void XEmitter::J_CC(CCFlags conditionCode, const u8* addr)
if (distance < -0x80 || distance >= 0x80)
{
distance = (s64)(fn - ((u64)code + 6));
_assert_msg_(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL,
"Jump target too far away, needs indirect register");
ASSERT_MSG(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL,
"Jump target too far away, needs indirect register");
Write8(0x0F);
Write8(0x80 + conditionCode);
Write32((u32)(s32)distance);
@ -518,15 +518,15 @@ void XEmitter::SetJumpTarget(const FixupBranch& branch)
if (branch.type == 0)
{
s64 distance = (s64)(code - branch.ptr);
_assert_msg_(DYNA_REC, distance >= -0x80 && distance < 0x80,
"Jump target too far away, needs force5Bytes = true");
ASSERT_MSG(DYNA_REC, distance >= -0x80 && distance < 0x80,
"Jump target too far away, needs force5Bytes = true");
branch.ptr[-1] = (u8)(s8)distance;
}
else if (branch.type == 1)
{
s64 distance = (s64)(code - branch.ptr);
_assert_msg_(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL,
"Jump target too far away, needs indirect register");
ASSERT_MSG(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL,
"Jump target too far away, needs indirect register");
s32 valid_distance = static_cast<s32>(distance);
std::memcpy(&branch.ptr[-4], &valid_distance, sizeof(s32));
@ -553,7 +553,7 @@ void XEmitter::RET_FAST()
// The first sign of decadence: optimized NOPs.
void XEmitter::NOP(size_t size)
{
_dbg_assert_(DYNA_REC, (int)size > 0);
DEBUG_ASSERT(DYNA_REC, (int)size > 0);
while (true)
{
switch (size)
@ -792,7 +792,7 @@ void XEmitter::PUSH(int bits, const OpArg& reg)
Write32((u32)reg.offset);
break;
default:
_assert_msg_(DYNA_REC, 0, "PUSH - Bad imm bits");
ASSERT_MSG(DYNA_REC, 0, "PUSH - Bad imm bits");
break;
}
}
@ -811,7 +811,7 @@ void XEmitter::POP(int /*bits*/, const OpArg& reg)
if (reg.IsSimpleReg())
POP(reg.GetSimpleReg());
else
_assert_msg_(DYNA_REC, 0, "POP - Unsupported encoding");
ASSERT_MSG(DYNA_REC, 0, "POP - Unsupported encoding");
}
void XEmitter::BSWAP(int bits, X64Reg reg)
@ -830,7 +830,7 @@ void XEmitter::BSWAP(int bits, X64Reg reg)
}
else
{
_assert_msg_(DYNA_REC, 0, "BSWAP - Wrong number of bits");
ASSERT_MSG(DYNA_REC, 0, "BSWAP - Wrong number of bits");
}
}
@ -844,7 +844,7 @@ void XEmitter::UD2()
void XEmitter::PREFETCH(PrefetchLevel level, OpArg arg)
{
_assert_msg_(DYNA_REC, !arg.IsImm(), "PREFETCH - Imm argument");
ASSERT_MSG(DYNA_REC, !arg.IsImm(), "PREFETCH - Imm argument");
arg.operandReg = (u8)level;
arg.WriteREX(this, 0, 0);
Write8(0x0F);
@ -854,7 +854,7 @@ void XEmitter::PREFETCH(PrefetchLevel level, OpArg arg)
void XEmitter::SETcc(CCFlags flag, OpArg dest)
{
_assert_msg_(DYNA_REC, !dest.IsImm(), "SETcc - Imm argument");
ASSERT_MSG(DYNA_REC, !dest.IsImm(), "SETcc - Imm argument");
dest.operandReg = 0;
dest.WriteREX(this, 0, 8);
Write8(0x0F);
@ -864,8 +864,8 @@ void XEmitter::SETcc(CCFlags flag, OpArg dest)
void XEmitter::CMOVcc(int bits, X64Reg dest, OpArg src, CCFlags flag)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "CMOVcc - Imm argument");
_assert_msg_(DYNA_REC, bits != 8, "CMOVcc - 8 bits unsupported");
ASSERT_MSG(DYNA_REC, !src.IsImm(), "CMOVcc - Imm argument");
ASSERT_MSG(DYNA_REC, bits != 8, "CMOVcc - 8 bits unsupported");
if (bits == 16)
Write8(0x66);
src.operandReg = dest;
@ -877,7 +877,7 @@ void XEmitter::CMOVcc(int bits, X64Reg dest, OpArg src, CCFlags flag)
void XEmitter::WriteMulDivType(int bits, OpArg src, int ext)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "WriteMulDivType - Imm argument");
ASSERT_MSG(DYNA_REC, !src.IsImm(), "WriteMulDivType - Imm argument");
CheckFlags();
src.operandReg = ext;
if (bits == 16)
@ -921,7 +921,7 @@ void XEmitter::NOT(int bits, const OpArg& src)
void XEmitter::WriteBitSearchType(int bits, X64Reg dest, OpArg src, u8 byte2, bool rep)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "WriteBitSearchType - Imm argument");
ASSERT_MSG(DYNA_REC, !src.IsImm(), "WriteBitSearchType - Imm argument");
CheckFlags();
src.operandReg = (u8)dest;
if (bits == 16)
@ -937,7 +937,7 @@ void XEmitter::WriteBitSearchType(int bits, X64Reg dest, OpArg src, u8 byte2, bo
void XEmitter::MOVNTI(int bits, const OpArg& dest, X64Reg src)
{
if (bits <= 16)
_assert_msg_(DYNA_REC, 0, "MOVNTI - bits<=16");
ASSERT_MSG(DYNA_REC, 0, "MOVNTI - bits<=16");
WriteBitSearchType(bits, src, dest, 0xC3);
}
@ -967,7 +967,7 @@ void XEmitter::LZCNT(int bits, X64Reg dest, const OpArg& src)
void XEmitter::MOVSX(int dbits, int sbits, X64Reg dest, OpArg src)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "MOVSX - Imm argument");
ASSERT_MSG(DYNA_REC, !src.IsImm(), "MOVSX - Imm argument");
if (dbits == sbits)
{
MOV(dbits, R(dest), src);
@ -1000,7 +1000,7 @@ void XEmitter::MOVSX(int dbits, int sbits, X64Reg dest, OpArg src)
void XEmitter::MOVZX(int dbits, int sbits, X64Reg dest, OpArg src)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "MOVZX - Imm argument");
ASSERT_MSG(DYNA_REC, !src.IsImm(), "MOVZX - Imm argument");
if (dbits == sbits)
{
MOV(dbits, R(dest), src);
@ -1027,14 +1027,14 @@ void XEmitter::MOVZX(int dbits, int sbits, X64Reg dest, OpArg src)
}
else
{
_assert_msg_(DYNA_REC, 0, "MOVZX - Invalid size");
ASSERT_MSG(DYNA_REC, 0, "MOVZX - Invalid size");
}
src.WriteRest(this);
}
void XEmitter::WriteMOVBE(int bits, u8 op, X64Reg reg, const OpArg& arg)
{
_assert_msg_(DYNA_REC, cpu_info.bMOVBE, "Generating MOVBE on a system that does not support it.");
ASSERT_MSG(DYNA_REC, cpu_info.bMOVBE, "Generating MOVBE on a system that does not support it.");
if (bits == 8)
{
MOV(8, op & 1 ? arg : R(reg), op & 1 ? R(reg) : arg);
@ -1042,7 +1042,7 @@ void XEmitter::WriteMOVBE(int bits, u8 op, X64Reg reg, const OpArg& arg)
}
if (bits == 16)
Write8(0x66);
_assert_msg_(DYNA_REC, !arg.IsSimpleReg() && !arg.IsImm(), "MOVBE: need r<-m or m<-r!");
ASSERT_MSG(DYNA_REC, !arg.IsSimpleReg() && !arg.IsImm(), "MOVBE: need r<-m or m<-r!");
arg.WriteREX(this, bits, bits, reg);
Write8(0x0F);
Write8(0x38);
@ -1127,7 +1127,7 @@ void XEmitter::SwapAndStore(int size, const OpArg& dst, X64Reg src, MovInfo* inf
void XEmitter::LEA(int bits, X64Reg dest, OpArg src)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "LEA - Imm argument");
ASSERT_MSG(DYNA_REC, !src.IsImm(), "LEA - Imm argument");
src.operandReg = (u8)dest;
if (bits == 16)
Write8(0x66); // TODO: performance warning
@ -1143,12 +1143,12 @@ void XEmitter::WriteShift(int bits, OpArg dest, const OpArg& shift, int ext)
bool writeImm = false;
if (dest.IsImm())
{
_assert_msg_(DYNA_REC, 0, "WriteShift - can't shift imms");
ASSERT_MSG(DYNA_REC, 0, "WriteShift - can't shift imms");
}
if ((shift.IsSimpleReg() && shift.GetSimpleReg() != ECX) ||
(shift.IsImm() && shift.GetImmBits() != 8))
{
_assert_msg_(DYNA_REC, 0, "WriteShift - illegal argument");
ASSERT_MSG(DYNA_REC, 0, "WriteShift - illegal argument");
}
dest.operandReg = ext;
if (bits == 16)
@ -1214,11 +1214,11 @@ void XEmitter::WriteBitTest(int bits, const OpArg& dest, const OpArg& index, int
CheckFlags();
if (dest.IsImm())
{
_assert_msg_(DYNA_REC, 0, "WriteBitTest - can't test imms");
ASSERT_MSG(DYNA_REC, 0, "WriteBitTest - can't test imms");
}
if ((index.IsImm() && index.GetImmBits() != 8))
{
_assert_msg_(DYNA_REC, 0, "WriteBitTest - illegal argument");
ASSERT_MSG(DYNA_REC, 0, "WriteBitTest - illegal argument");
}
if (bits == 16)
Write8(0x66);
@ -1263,16 +1263,16 @@ void XEmitter::SHRD(int bits, const OpArg& dest, const OpArg& src, const OpArg&
CheckFlags();
if (dest.IsImm())
{
_assert_msg_(DYNA_REC, 0, "SHRD - can't use imms as destination");
ASSERT_MSG(DYNA_REC, 0, "SHRD - can't use imms as destination");
}
if (!src.IsSimpleReg())
{
_assert_msg_(DYNA_REC, 0, "SHRD - must use simple register as source");
ASSERT_MSG(DYNA_REC, 0, "SHRD - must use simple register as source");
}
if ((shift.IsSimpleReg() && shift.GetSimpleReg() != ECX) ||
(shift.IsImm() && shift.GetImmBits() != 8))
{
_assert_msg_(DYNA_REC, 0, "SHRD - illegal shift");
ASSERT_MSG(DYNA_REC, 0, "SHRD - illegal shift");
}
if (bits == 16)
Write8(0x66);
@ -1298,16 +1298,16 @@ void XEmitter::SHLD(int bits, const OpArg& dest, const OpArg& src, const OpArg&
CheckFlags();
if (dest.IsImm())
{
_assert_msg_(DYNA_REC, 0, "SHLD - can't use imms as destination");
ASSERT_MSG(DYNA_REC, 0, "SHLD - can't use imms as destination");
}
if (!src.IsSimpleReg())
{
_assert_msg_(DYNA_REC, 0, "SHLD - must use simple register as source");
ASSERT_MSG(DYNA_REC, 0, "SHLD - must use simple register as source");
}
if ((shift.IsSimpleReg() && shift.GetSimpleReg() != ECX) ||
(shift.IsImm() && shift.GetImmBits() != 8))
{
_assert_msg_(DYNA_REC, 0, "SHLD - illegal shift");
ASSERT_MSG(DYNA_REC, 0, "SHLD - illegal shift");
}
if (bits == 16)
Write8(0x66);
@ -1346,7 +1346,7 @@ void OpArg::WriteNormalOp(XEmitter* emit, bool toRM, NormalOp op, const OpArg& o
X64Reg _operandReg;
if (IsImm())
{
_assert_msg_(DYNA_REC, 0, "WriteNormalOp - Imm argument, wrong order");
ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - Imm argument, wrong order");
}
if (bits == 16)
@ -1360,7 +1360,7 @@ void OpArg::WriteNormalOp(XEmitter* emit, bool toRM, NormalOp op, const OpArg& o
if (!toRM)
{
_assert_msg_(DYNA_REC, 0, "WriteNormalOp - Writing to Imm (!toRM)");
ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - Writing to Imm (!toRM)");
}
if (operand.scale == SCALE_IMM8 && bits == 8)
@ -1436,8 +1436,8 @@ void OpArg::WriteNormalOp(XEmitter* emit, bool toRM, NormalOp op, const OpArg& o
{
if (scale)
{
_assert_msg_(DYNA_REC, 0,
"WriteNormalOp - MOV with 64-bit imm requres register destination");
ASSERT_MSG(DYNA_REC, 0,
"WriteNormalOp - MOV with 64-bit imm requires register destination");
}
// mov reg64, imm64
else if (op == nrmMOV)
@ -1446,11 +1446,11 @@ void OpArg::WriteNormalOp(XEmitter* emit, bool toRM, NormalOp op, const OpArg& o
emit->Write64((u64)operand.offset);
return;
}
_assert_msg_(DYNA_REC, 0, "WriteNormalOp - Only MOV can take 64-bit imm");
ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - Only MOV can take 64-bit imm");
}
else
{
_assert_msg_(DYNA_REC, 0, "WriteNormalOp - Unhandled case %d %d", operand.scale, bits);
ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - Unhandled case %d %d", operand.scale, bits);
}
_operandReg = (X64Reg)normalops[op].ext; // pass extension in REG of ModRM
}
@ -1484,7 +1484,7 @@ void OpArg::WriteNormalOp(XEmitter* emit, bool toRM, NormalOp op, const OpArg& o
emit->Write32((u32)operand.offset);
break;
default:
_assert_msg_(DYNA_REC, 0, "WriteNormalOp - Unhandled case");
ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - Unhandled case");
}
}
@ -1493,7 +1493,7 @@ void XEmitter::WriteNormalOp(int bits, NormalOp op, const OpArg& a1, const OpArg
if (a1.IsImm())
{
// Booh! Can't write to an imm
_assert_msg_(DYNA_REC, 0, "WriteNormalOp - a1 cannot be imm");
ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - a1 cannot be imm");
return;
}
if (a2.IsImm())
@ -1508,8 +1508,8 @@ void XEmitter::WriteNormalOp(int bits, NormalOp op, const OpArg& a1, const OpArg
}
else
{
_assert_msg_(DYNA_REC, a2.IsSimpleReg() || a2.IsImm(),
"WriteNormalOp - a1 and a2 cannot both be memory");
ASSERT_MSG(DYNA_REC, a2.IsSimpleReg() || a2.IsImm(),
"WriteNormalOp - a1 and a2 cannot both be memory");
a1.WriteNormalOp(this, true, op, a2, bits);
}
}
@ -1587,7 +1587,7 @@ void XEmitter::CMP_or_TEST(int bits, const OpArg& a1, const OpArg& a2)
void XEmitter::MOV_sum(int bits, X64Reg dest, const OpArg& a1, const OpArg& a2)
{
// This stomps on flags, so ensure they aren't locked
_dbg_assert_(DYNA_REC, !flags_locked);
DEBUG_ASSERT(DYNA_REC, !flags_locked);
// Zero shortcuts (note that this can generate no code in the case where a1 == dest && a2 == zero
// or a2 == dest && a1 == zero)
@ -1659,19 +1659,19 @@ void XEmitter::IMUL(int bits, X64Reg regOp, const OpArg& a1, const OpArg& a2)
CheckFlags();
if (bits == 8)
{
_assert_msg_(DYNA_REC, 0, "IMUL - illegal bit size!");
ASSERT_MSG(DYNA_REC, 0, "IMUL - illegal bit size!");
return;
}
if (a1.IsImm())
{
_assert_msg_(DYNA_REC, 0, "IMUL - second arg cannot be imm!");
ASSERT_MSG(DYNA_REC, 0, "IMUL - second arg cannot be imm!");
return;
}
if (!a2.IsImm())
{
_assert_msg_(DYNA_REC, 0, "IMUL - third arg must be imm!");
ASSERT_MSG(DYNA_REC, 0, "IMUL - third arg must be imm!");
return;
}
@ -1701,7 +1701,7 @@ void XEmitter::IMUL(int bits, X64Reg regOp, const OpArg& a1, const OpArg& a2)
}
else
{
_assert_msg_(DYNA_REC, 0, "IMUL - unhandled case!");
ASSERT_MSG(DYNA_REC, 0, "IMUL - unhandled case!");
}
}
}
@ -1711,7 +1711,7 @@ void XEmitter::IMUL(int bits, X64Reg regOp, const OpArg& a)
CheckFlags();
if (bits == 8)
{
_assert_msg_(DYNA_REC, 0, "IMUL - illegal bit size!");
ASSERT_MSG(DYNA_REC, 0, "IMUL - illegal bit size!");
return;
}
@ -1890,7 +1890,7 @@ void XEmitter::MOVQ_xmm(OpArg arg, X64Reg src)
void XEmitter::WriteMXCSR(OpArg arg, int ext)
{
if (arg.IsImm() || arg.IsSimpleReg())
_assert_msg_(DYNA_REC, 0, "MXCSR - invalid operand");
ASSERT_MSG(DYNA_REC, 0, "MXCSR - invalid operand");
arg.operandReg = ext;
arg.WriteREX(this, 0, 0);
@ -3248,8 +3248,8 @@ void XEmitter::FWAIT()
void XEmitter::WriteFloatLoadStore(int bits, FloatOp op, FloatOp op_80b, const OpArg& arg)
{
int mf = 0;
_assert_msg_(DYNA_REC, !(bits == 80 && op_80b == floatINVALID),
"WriteFloatLoadStore: 80 bits not supported for this instruction");
ASSERT_MSG(DYNA_REC, !(bits == 80 && op_80b == floatINVALID),
"WriteFloatLoadStore: 80 bits not supported for this instruction");
switch (bits)
{
case 32:
@ -3262,7 +3262,7 @@ void XEmitter::WriteFloatLoadStore(int bits, FloatOp op, FloatOp op_80b, const O
mf = 2;
break;
default:
_assert_msg_(DYNA_REC, 0, "WriteFloatLoadStore: invalid bits (should be 32/64/80)");
ASSERT_MSG(DYNA_REC, 0, "WriteFloatLoadStore: invalid bits (should be 32/64/80)");
}
Write8(0xd9 | mf);
// x87 instructions use the reg field of the ModR/M byte as opcode:

28
Source/Core/Common/x64Emitter.h
View File

@ -156,64 +156,64 @@ struct OpArg
u64 Imm64() const
{
_dbg_assert_(DYNA_REC, scale == SCALE_IMM64);
DEBUG_ASSERT(DYNA_REC, scale == SCALE_IMM64);
return (u64)offset;
}
u32 Imm32() const
{
_dbg_assert_(DYNA_REC, scale == SCALE_IMM32);
DEBUG_ASSERT(DYNA_REC, scale == SCALE_IMM32);
return (u32)offset;
}
u16 Imm16() const
{
_dbg_assert_(DYNA_REC, scale == SCALE_IMM16);
DEBUG_ASSERT(DYNA_REC, scale == SCALE_IMM16);
return (u16)offset;
}
u8 Imm8() const
{
_dbg_assert_(DYNA_REC, scale == SCALE_IMM8);
DEBUG_ASSERT(DYNA_REC, scale == SCALE_IMM8);
return (u8)offset;
}
s64 SImm64() const
{
_dbg_assert_(DYNA_REC, scale == SCALE_IMM64);
DEBUG_ASSERT(DYNA_REC, scale == SCALE_IMM64);
return (s64)offset;
}
s32 SImm32() const
{
_dbg_assert_(DYNA_REC, scale == SCALE_IMM32);
DEBUG_ASSERT(DYNA_REC, scale == SCALE_IMM32);
return (s32)offset;
}
s16 SImm16() const
{
_dbg_assert_(DYNA_REC, scale == SCALE_IMM16);
DEBUG_ASSERT(DYNA_REC, scale == SCALE_IMM16);
return (s16)offset;
}
s8 SImm8() const
{
_dbg_assert_(DYNA_REC, scale == SCALE_IMM8);
DEBUG_ASSERT(DYNA_REC, scale == SCALE_IMM8);
return (s8)offset;
}
OpArg AsImm64() const
{
_dbg_assert_(DYNA_REC, IsImm());
DEBUG_ASSERT(DYNA_REC, IsImm());
return OpArg((u64)offset, SCALE_IMM64);
}
OpArg AsImm32() const
{
_dbg_assert_(DYNA_REC, IsImm());
DEBUG_ASSERT(DYNA_REC, IsImm());
return OpArg((u32)offset, SCALE_IMM32);
}
OpArg AsImm16() const
{
_dbg_assert_(DYNA_REC, IsImm());
DEBUG_ASSERT(DYNA_REC, IsImm());
return OpArg((u16)offset, SCALE_IMM16);
}
OpArg AsImm8() const
{
_dbg_assert_(DYNA_REC, IsImm());
DEBUG_ASSERT(DYNA_REC, IsImm());
return OpArg((u8)offset, SCALE_IMM8);
}
@ -253,7 +253,7 @@ struct OpArg
void AddMemOffset(int val)
{
_dbg_assert_msg_(DYNA_REC, scale == SCALE_RIP || (scale <= SCALE_ATREG && scale > SCALE_NONE),
DEBUG_ASSERT_MSG(DYNA_REC, scale == SCALE_RIP || (scale <= SCALE_ATREG && scale > SCALE_NONE),
"Tried to increment an OpArg which doesn't have an offset");
offset += val;
}
@ -329,7 +329,7 @@ inline u32 PtrOffset(const void* ptr, const void* base = nullptr)
s64 distance = (s64)ptr - (s64)base;
if (distance >= 0x80000000LL || distance < -0x80000000LL)
{
_assert_msg_(DYNA_REC, 0, "pointer offset out of range");
ASSERT_MSG(DYNA_REC, 0, "pointer offset out of range");
return 0;
}