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Assert: Uppercase assertion macros

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Macros should be all upper-cased. This is also kind of a wart that's
been sticking out for quite a while now (we avoid prefixing
underscores).
This commit is contained in:
Lioncash
2018-03-14 20:34:35 -04:00
parent 19d97f3fd9
commit 50a476c371
135 changed files with 719 additions and 741 deletions
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140
Source/Core/Common/x64Emitter.cpp
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@ -122,8 +122,8 @@ void XEmitter::ReserveCodeSpace(int bytes)
const u8* XEmitter::AlignCodeTo(size_t alignment)
{
_assert_msg_(DYNA_REC, alignment != 0 && (alignment & (alignment - 1)) == 0,
"Alignment must be power of two");
ASSERT_MSG(DYNA_REC, alignment != 0 && (alignment & (alignment - 1)) == 0,
"Alignment must be power of two");
u64 c = reinterpret_cast<u64>(code) & (alignment - 1);
if (c)
ReserveCodeSpace(static_cast<int>(alignment - c));
@ -150,7 +150,7 @@ const u8* XEmitter::AlignCodePage()
// causing a subtle JIT bug.
void XEmitter::CheckFlags()
{
_assert_msg_(DYNA_REC, !flags_locked, "Attempt to modify flags while flags locked!");
ASSERT_MSG(DYNA_REC, !flags_locked, "Attempt to modify flags while flags locked!");
}
void XEmitter::WriteModRM(int mod, int reg, int rm)
@ -187,8 +187,8 @@ void OpArg::WriteREX(XEmitter* emit, int opBits, int bits, int customOp) const
{
emit->Write8(op);
// Check the operation doesn't access AH, BH, CH, or DH.
_dbg_assert_(DYNA_REC, (offsetOrBaseReg & 0x100) == 0);
_dbg_assert_(DYNA_REC, (customOp & 0x100) == 0);
DEBUG_ASSERT(DYNA_REC, (offsetOrBaseReg & 0x100) == 0);
DEBUG_ASSERT(DYNA_REC, (customOp & 0x100) == 0);
}
}
@ -236,9 +236,9 @@ void OpArg::WriteRest(XEmitter* emit, int extraBytes, X64Reg _operandReg,
// TODO : add some checks
u64 ripAddr = (u64)emit->GetCodePtr() + 4 + extraBytes;
s64 distance = (s64)offset - (s64)ripAddr;
_assert_msg_(DYNA_REC,
(distance < 0x80000000LL && distance >= -0x80000000LL) || !warn_64bit_offset,
"WriteRest: op out of range (0x%" PRIx64 " uses 0x%" PRIx64 ")", ripAddr, offset);
ASSERT_MSG(DYNA_REC,
(distance < 0x80000000LL && distance >= -0x80000000LL) || !warn_64bit_offset,
"WriteRest: op out of range (0x%" PRIx64 " uses 0x%" PRIx64 ")", ripAddr, offset);
s32 offs = (s32)distance;
emit->Write32((u32)offs);
return;
@ -351,7 +351,7 @@ void OpArg::WriteRest(XEmitter* emit, int extraBytes, X64Reg _operandReg,
ss = 0;
break;
default:
_assert_msg_(DYNA_REC, 0, "Invalid scale for SIB byte");
ASSERT_MSG(DYNA_REC, 0, "Invalid scale for SIB byte");
ss = 0;
break;
}
@ -389,8 +389,8 @@ void XEmitter::JMP(const u8* addr, bool force5Bytes)
if (!force5Bytes)
{
s64 distance = (s64)(fn - ((u64)code + 2));
_assert_msg_(DYNA_REC, distance >= -0x80 && distance < 0x80,
"Jump target too far away, needs force5Bytes = true");
ASSERT_MSG(DYNA_REC, distance >= -0x80 && distance < 0x80,
"Jump target too far away, needs force5Bytes = true");
// 8 bits will do
Write8(0xEB);
Write8((u8)(s8)distance);
@ -399,8 +399,8 @@ void XEmitter::JMP(const u8* addr, bool force5Bytes)
{
s64 distance = (s64)(fn - ((u64)code + 5));
_assert_msg_(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL,
"Jump target too far away, needs indirect register");
ASSERT_MSG(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL,
"Jump target too far away, needs indirect register");
Write8(0xE9);
Write32((u32)(s32)distance);
}
@ -410,7 +410,7 @@ void XEmitter::JMPptr(const OpArg& arg2)
{
OpArg arg = arg2;
if (arg.IsImm())
_assert_msg_(DYNA_REC, 0, "JMPptr - Imm argument");
ASSERT_MSG(DYNA_REC, 0, "JMPptr - Imm argument");
arg.operandReg = 4;
arg.WriteREX(this, 0, 0);
Write8(0xFF);
@ -428,7 +428,7 @@ void XEmitter::JMPself()
void XEmitter::CALLptr(OpArg arg)
{
if (arg.IsImm())
_assert_msg_(DYNA_REC, 0, "CALLptr - Imm argument");
ASSERT_MSG(DYNA_REC, 0, "CALLptr - Imm argument");
arg.operandReg = 2;
arg.WriteREX(this, 0, 0);
Write8(0xFF);
@ -438,8 +438,8 @@ void XEmitter::CALLptr(OpArg arg)
void XEmitter::CALL(const void* fnptr)
{
u64 distance = u64(fnptr) - (u64(code) + 5);
_assert_msg_(DYNA_REC, distance < 0x0000000080000000ULL || distance >= 0xFFFFFFFF80000000ULL,
"CALL out of range (%p calls %p)", code, fnptr);
ASSERT_MSG(DYNA_REC, distance < 0x0000000080000000ULL || distance >= 0xFFFFFFFF80000000ULL,
"CALL out of range (%p calls %p)", code, fnptr);
Write8(0xE8);
Write32(u32(distance));
}
@ -500,8 +500,8 @@ void XEmitter::J_CC(CCFlags conditionCode, const u8* addr)
if (distance < -0x80 || distance >= 0x80)
{
distance = (s64)(fn - ((u64)code + 6));
_assert_msg_(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL,
"Jump target too far away, needs indirect register");
ASSERT_MSG(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL,
"Jump target too far away, needs indirect register");
Write8(0x0F);
Write8(0x80 + conditionCode);
Write32((u32)(s32)distance);
@ -518,15 +518,15 @@ void XEmitter::SetJumpTarget(const FixupBranch& branch)
if (branch.type == 0)
{
s64 distance = (s64)(code - branch.ptr);
_assert_msg_(DYNA_REC, distance >= -0x80 && distance < 0x80,
"Jump target too far away, needs force5Bytes = true");
ASSERT_MSG(DYNA_REC, distance >= -0x80 && distance < 0x80,
"Jump target too far away, needs force5Bytes = true");
branch.ptr[-1] = (u8)(s8)distance;
}
else if (branch.type == 1)
{
s64 distance = (s64)(code - branch.ptr);
_assert_msg_(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL,
"Jump target too far away, needs indirect register");
ASSERT_MSG(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL,
"Jump target too far away, needs indirect register");
s32 valid_distance = static_cast<s32>(distance);
std::memcpy(&branch.ptr[-4], &valid_distance, sizeof(s32));
@ -553,7 +553,7 @@ void XEmitter::RET_FAST()
// The first sign of decadence: optimized NOPs.
void XEmitter::NOP(size_t size)
{
_dbg_assert_(DYNA_REC, (int)size > 0);
DEBUG_ASSERT(DYNA_REC, (int)size > 0);
while (true)
{
switch (size)
@ -792,7 +792,7 @@ void XEmitter::PUSH(int bits, const OpArg& reg)
Write32((u32)reg.offset);
break;
default:
_assert_msg_(DYNA_REC, 0, "PUSH - Bad imm bits");
ASSERT_MSG(DYNA_REC, 0, "PUSH - Bad imm bits");
break;
}
}
@ -811,7 +811,7 @@ void XEmitter::POP(int /*bits*/, const OpArg& reg)
if (reg.IsSimpleReg())
POP(reg.GetSimpleReg());
else
_assert_msg_(DYNA_REC, 0, "POP - Unsupported encoding");
ASSERT_MSG(DYNA_REC, 0, "POP - Unsupported encoding");
}
void XEmitter::BSWAP(int bits, X64Reg reg)
@ -830,7 +830,7 @@ void XEmitter::BSWAP(int bits, X64Reg reg)
}
else
{
_assert_msg_(DYNA_REC, 0, "BSWAP - Wrong number of bits");
ASSERT_MSG(DYNA_REC, 0, "BSWAP - Wrong number of bits");
}
}
@ -844,7 +844,7 @@ void XEmitter::UD2()
void XEmitter::PREFETCH(PrefetchLevel level, OpArg arg)
{
_assert_msg_(DYNA_REC, !arg.IsImm(), "PREFETCH - Imm argument");
ASSERT_MSG(DYNA_REC, !arg.IsImm(), "PREFETCH - Imm argument");
arg.operandReg = (u8)level;
arg.WriteREX(this, 0, 0);
Write8(0x0F);
@ -854,7 +854,7 @@ void XEmitter::PREFETCH(PrefetchLevel level, OpArg arg)
void XEmitter::SETcc(CCFlags flag, OpArg dest)
{
_assert_msg_(DYNA_REC, !dest.IsImm(), "SETcc - Imm argument");
ASSERT_MSG(DYNA_REC, !dest.IsImm(), "SETcc - Imm argument");
dest.operandReg = 0;
dest.WriteREX(this, 0, 8);
Write8(0x0F);
@ -864,8 +864,8 @@ void XEmitter::SETcc(CCFlags flag, OpArg dest)
void XEmitter::CMOVcc(int bits, X64Reg dest, OpArg src, CCFlags flag)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "CMOVcc - Imm argument");
_assert_msg_(DYNA_REC, bits != 8, "CMOVcc - 8 bits unsupported");
ASSERT_MSG(DYNA_REC, !src.IsImm(), "CMOVcc - Imm argument");
ASSERT_MSG(DYNA_REC, bits != 8, "CMOVcc - 8 bits unsupported");
if (bits == 16)
Write8(0x66);
src.operandReg = dest;
@ -877,7 +877,7 @@ void XEmitter::CMOVcc(int bits, X64Reg dest, OpArg src, CCFlags flag)
void XEmitter::WriteMulDivType(int bits, OpArg src, int ext)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "WriteMulDivType - Imm argument");
ASSERT_MSG(DYNA_REC, !src.IsImm(), "WriteMulDivType - Imm argument");
CheckFlags();
src.operandReg = ext;
if (bits == 16)
@ -921,7 +921,7 @@ void XEmitter::NOT(int bits, const OpArg& src)
void XEmitter::WriteBitSearchType(int bits, X64Reg dest, OpArg src, u8 byte2, bool rep)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "WriteBitSearchType - Imm argument");
ASSERT_MSG(DYNA_REC, !src.IsImm(), "WriteBitSearchType - Imm argument");
CheckFlags();
src.operandReg = (u8)dest;
if (bits == 16)
@ -937,7 +937,7 @@ void XEmitter::WriteBitSearchType(int bits, X64Reg dest, OpArg src, u8 byte2, bo
void XEmitter::MOVNTI(int bits, const OpArg& dest, X64Reg src)
{
if (bits <= 16)
_assert_msg_(DYNA_REC, 0, "MOVNTI - bits<=16");
ASSERT_MSG(DYNA_REC, 0, "MOVNTI - bits<=16");
WriteBitSearchType(bits, src, dest, 0xC3);
}
@ -967,7 +967,7 @@ void XEmitter::LZCNT(int bits, X64Reg dest, const OpArg& src)
void XEmitter::MOVSX(int dbits, int sbits, X64Reg dest, OpArg src)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "MOVSX - Imm argument");
ASSERT_MSG(DYNA_REC, !src.IsImm(), "MOVSX - Imm argument");
if (dbits == sbits)
{
MOV(dbits, R(dest), src);
@ -1000,7 +1000,7 @@ void XEmitter::MOVSX(int dbits, int sbits, X64Reg dest, OpArg src)
void XEmitter::MOVZX(int dbits, int sbits, X64Reg dest, OpArg src)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "MOVZX - Imm argument");
ASSERT_MSG(DYNA_REC, !src.IsImm(), "MOVZX - Imm argument");
if (dbits == sbits)
{
MOV(dbits, R(dest), src);
@ -1027,14 +1027,14 @@ void XEmitter::MOVZX(int dbits, int sbits, X64Reg dest, OpArg src)
}
else
{
_assert_msg_(DYNA_REC, 0, "MOVZX - Invalid size");
ASSERT_MSG(DYNA_REC, 0, "MOVZX - Invalid size");
}
src.WriteRest(this);
}
void XEmitter::WriteMOVBE(int bits, u8 op, X64Reg reg, const OpArg& arg)
{
_assert_msg_(DYNA_REC, cpu_info.bMOVBE, "Generating MOVBE on a system that does not support it.");
ASSERT_MSG(DYNA_REC, cpu_info.bMOVBE, "Generating MOVBE on a system that does not support it.");
if (bits == 8)
{
MOV(8, op & 1 ? arg : R(reg), op & 1 ? R(reg) : arg);
@ -1042,7 +1042,7 @@ void XEmitter::WriteMOVBE(int bits, u8 op, X64Reg reg, const OpArg& arg)
}
if (bits == 16)
Write8(0x66);
_assert_msg_(DYNA_REC, !arg.IsSimpleReg() && !arg.IsImm(), "MOVBE: need r<-m or m<-r!");
ASSERT_MSG(DYNA_REC, !arg.IsSimpleReg() && !arg.IsImm(), "MOVBE: need r<-m or m<-r!");
arg.WriteREX(this, bits, bits, reg);
Write8(0x0F);
Write8(0x38);
@ -1127,7 +1127,7 @@ void XEmitter::SwapAndStore(int size, const OpArg& dst, X64Reg src, MovInfo* inf
void XEmitter::LEA(int bits, X64Reg dest, OpArg src)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "LEA - Imm argument");
ASSERT_MSG(DYNA_REC, !src.IsImm(), "LEA - Imm argument");
src.operandReg = (u8)dest;
if (bits == 16)
Write8(0x66); // TODO: performance warning
@ -1143,12 +1143,12 @@ void XEmitter::WriteShift(int bits, OpArg dest, const OpArg& shift, int ext)
bool writeImm = false;
if (dest.IsImm())
{
_assert_msg_(DYNA_REC, 0, "WriteShift - can't shift imms");
ASSERT_MSG(DYNA_REC, 0, "WriteShift - can't shift imms");
}
if ((shift.IsSimpleReg() && shift.GetSimpleReg() != ECX) ||
(shift.IsImm() && shift.GetImmBits() != 8))
{
_assert_msg_(DYNA_REC, 0, "WriteShift - illegal argument");
ASSERT_MSG(DYNA_REC, 0, "WriteShift - illegal argument");
}
dest.operandReg = ext;
if (bits == 16)
@ -1214,11 +1214,11 @@ void XEmitter::WriteBitTest(int bits, const OpArg& dest, const OpArg& index, int
CheckFlags();
if (dest.IsImm())
{
_assert_msg_(DYNA_REC, 0, "WriteBitTest - can't test imms");
ASSERT_MSG(DYNA_REC, 0, "WriteBitTest - can't test imms");
}
if ((index.IsImm() && index.GetImmBits() != 8))
{
_assert_msg_(DYNA_REC, 0, "WriteBitTest - illegal argument");
ASSERT_MSG(DYNA_REC, 0, "WriteBitTest - illegal argument");
}
if (bits == 16)
Write8(0x66);
@ -1263,16 +1263,16 @@ void XEmitter::SHRD(int bits, const OpArg& dest, const OpArg& src, const OpArg&
CheckFlags();
if (dest.IsImm())
{
_assert_msg_(DYNA_REC, 0, "SHRD - can't use imms as destination");
ASSERT_MSG(DYNA_REC, 0, "SHRD - can't use imms as destination");
}
if (!src.IsSimpleReg())
{
_assert_msg_(DYNA_REC, 0, "SHRD - must use simple register as source");
ASSERT_MSG(DYNA_REC, 0, "SHRD - must use simple register as source");
}
if ((shift.IsSimpleReg() && shift.GetSimpleReg() != ECX) ||
(shift.IsImm() && shift.GetImmBits() != 8))
{
_assert_msg_(DYNA_REC, 0, "SHRD - illegal shift");
ASSERT_MSG(DYNA_REC, 0, "SHRD - illegal shift");
}
if (bits == 16)
Write8(0x66);
@ -1298,16 +1298,16 @@ void XEmitter::SHLD(int bits, const OpArg& dest, const OpArg& src, const OpArg&
CheckFlags();
if (dest.IsImm())
{
_assert_msg_(DYNA_REC, 0, "SHLD - can't use imms as destination");
ASSERT_MSG(DYNA_REC, 0, "SHLD - can't use imms as destination");
}
if (!src.IsSimpleReg())
{
_assert_msg_(DYNA_REC, 0, "SHLD - must use simple register as source");
ASSERT_MSG(DYNA_REC, 0, "SHLD - must use simple register as source");
}
if ((shift.IsSimpleReg() && shift.GetSimpleReg() != ECX) ||
(shift.IsImm() && shift.GetImmBits() != 8))
{
_assert_msg_(DYNA_REC, 0, "SHLD - illegal shift");
ASSERT_MSG(DYNA_REC, 0, "SHLD - illegal shift");
}
if (bits == 16)
Write8(0x66);
@ -1346,7 +1346,7 @@ void OpArg::WriteNormalOp(XEmitter* emit, bool toRM, NormalOp op, const OpArg& o
X64Reg _operandReg;
if (IsImm())
{
_assert_msg_(DYNA_REC, 0, "WriteNormalOp - Imm argument, wrong order");
ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - Imm argument, wrong order");
}
if (bits == 16)
@ -1360,7 +1360,7 @@ void OpArg::WriteNormalOp(XEmitter* emit, bool toRM, NormalOp op, const OpArg& o
if (!toRM)
{
_assert_msg_(DYNA_REC, 0, "WriteNormalOp - Writing to Imm (!toRM)");
ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - Writing to Imm (!toRM)");
}
if (operand.scale == SCALE_IMM8 && bits == 8)
@ -1436,8 +1436,8 @@ void OpArg::WriteNormalOp(XEmitter* emit, bool toRM, NormalOp op, const OpArg& o
{
if (scale)
{
_assert_msg_(DYNA_REC, 0,
"WriteNormalOp - MOV with 64-bit imm requres register destination");
ASSERT_MSG(DYNA_REC, 0,
"WriteNormalOp - MOV with 64-bit imm requires register destination");
}
// mov reg64, imm64
else if (op == nrmMOV)
@ -1446,11 +1446,11 @@ void OpArg::WriteNormalOp(XEmitter* emit, bool toRM, NormalOp op, const OpArg& o
emit->Write64((u64)operand.offset);
return;
}
_assert_msg_(DYNA_REC, 0, "WriteNormalOp - Only MOV can take 64-bit imm");
ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - Only MOV can take 64-bit imm");
}
else
{
_assert_msg_(DYNA_REC, 0, "WriteNormalOp - Unhandled case %d %d", operand.scale, bits);
ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - Unhandled case %d %d", operand.scale, bits);
}
_operandReg = (X64Reg)normalops[op].ext; // pass extension in REG of ModRM
}
@ -1484,7 +1484,7 @@ void OpArg::WriteNormalOp(XEmitter* emit, bool toRM, NormalOp op, const OpArg& o
emit->Write32((u32)operand.offset);
break;
default:
_assert_msg_(DYNA_REC, 0, "WriteNormalOp - Unhandled case");
ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - Unhandled case");
}
}
@ -1493,7 +1493,7 @@ void XEmitter::WriteNormalOp(int bits, NormalOp op, const OpArg& a1, const OpArg
if (a1.IsImm())
{
// Booh! Can't write to an imm
_assert_msg_(DYNA_REC, 0, "WriteNormalOp - a1 cannot be imm");
ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - a1 cannot be imm");
return;
}
if (a2.IsImm())
@ -1508,8 +1508,8 @@ void XEmitter::WriteNormalOp(int bits, NormalOp op, const OpArg& a1, const OpArg
}
else
{
_assert_msg_(DYNA_REC, a2.IsSimpleReg() || a2.IsImm(),
"WriteNormalOp - a1 and a2 cannot both be memory");
ASSERT_MSG(DYNA_REC, a2.IsSimpleReg() || a2.IsImm(),
"WriteNormalOp - a1 and a2 cannot both be memory");
a1.WriteNormalOp(this, true, op, a2, bits);
}
}
@ -1587,7 +1587,7 @@ void XEmitter::CMP_or_TEST(int bits, const OpArg& a1, const OpArg& a2)
void XEmitter::MOV_sum(int bits, X64Reg dest, const OpArg& a1, const OpArg& a2)
{
// This stomps on flags, so ensure they aren't locked
_dbg_assert_(DYNA_REC, !flags_locked);
DEBUG_ASSERT(DYNA_REC, !flags_locked);
// Zero shortcuts (note that this can generate no code in the case where a1 == dest && a2 == zero
// or a2 == dest && a1 == zero)
@ -1659,19 +1659,19 @@ void XEmitter::IMUL(int bits, X64Reg regOp, const OpArg& a1, const OpArg& a2)
CheckFlags();
if (bits == 8)
{
_assert_msg_(DYNA_REC, 0, "IMUL - illegal bit size!");
ASSERT_MSG(DYNA_REC, 0, "IMUL - illegal bit size!");
return;
}
if (a1.IsImm())
{
_assert_msg_(DYNA_REC, 0, "IMUL - second arg cannot be imm!");
ASSERT_MSG(DYNA_REC, 0, "IMUL - second arg cannot be imm!");
return;
}
if (!a2.IsImm())
{
_assert_msg_(DYNA_REC, 0, "IMUL - third arg must be imm!");
ASSERT_MSG(DYNA_REC, 0, "IMUL - third arg must be imm!");
return;
}
@ -1701,7 +1701,7 @@ void XEmitter::IMUL(int bits, X64Reg regOp, const OpArg& a1, const OpArg& a2)
}
else
{
_assert_msg_(DYNA_REC, 0, "IMUL - unhandled case!");
ASSERT_MSG(DYNA_REC, 0, "IMUL - unhandled case!");
}
}
}
@ -1711,7 +1711,7 @@ void XEmitter::IMUL(int bits, X64Reg regOp, const OpArg& a)
CheckFlags();
if (bits == 8)
{
_assert_msg_(DYNA_REC, 0, "IMUL - illegal bit size!");
ASSERT_MSG(DYNA_REC, 0, "IMUL - illegal bit size!");
return;
}
@ -1890,7 +1890,7 @@ void XEmitter::MOVQ_xmm(OpArg arg, X64Reg src)
void XEmitter::WriteMXCSR(OpArg arg, int ext)
{
if (arg.IsImm() || arg.IsSimpleReg())
_assert_msg_(DYNA_REC, 0, "MXCSR - invalid operand");
ASSERT_MSG(DYNA_REC, 0, "MXCSR - invalid operand");
arg.operandReg = ext;
arg.WriteREX(this, 0, 0);
@ -3248,8 +3248,8 @@ void XEmitter::FWAIT()
void XEmitter::WriteFloatLoadStore(int bits, FloatOp op, FloatOp op_80b, const OpArg& arg)
{
int mf = 0;
_assert_msg_(DYNA_REC, !(bits == 80 && op_80b == floatINVALID),
"WriteFloatLoadStore: 80 bits not supported for this instruction");
ASSERT_MSG(DYNA_REC, !(bits == 80 && op_80b == floatINVALID),
"WriteFloatLoadStore: 80 bits not supported for this instruction");
switch (bits)
{
case 32:
@ -3262,7 +3262,7 @@ void XEmitter::WriteFloatLoadStore(int bits, FloatOp op, FloatOp op_80b, const O
mf = 2;
break;
default:
_assert_msg_(DYNA_REC, 0, "WriteFloatLoadStore: invalid bits (should be 32/64/80)");
ASSERT_MSG(DYNA_REC, 0, "WriteFloatLoadStore: invalid bits (should be 32/64/80)");
}
Write8(0xd9 | mf);
// x87 instructions use the reg field of the ModR/M byte as opcode: