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JitArm64: Store memory pointer once, not per block.
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@ -205,6 +205,7 @@ void JitArm64::WriteExit(u32 destination)
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b->linkData.push_back(linkData);
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}
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void JitArm64::WriteExceptionExit(ARM64Reg dest)
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{
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Cleanup();
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@ -464,10 +465,6 @@ const u8* JitArm64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitB
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gpr.Start(js.gpa);
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fpr.Start(js.fpa);
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// Setup memory base register
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u8* base = UReg_MSR(MSR).DR ? Memory::logical_base : Memory::physical_base;
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MOVI2R(X28, (u64)base);
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if (!SConfig::GetInstance().bEnableDebugging)
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js.downcountAmount += PatchEngine::GetSpeedhackCycles(em_address);
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@ -13,6 +13,7 @@
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// Dedicated host registers
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// X29 = ppcState pointer
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// X28 = memory base register
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using namespace Arm64Gen;
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enum RegType
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@ -26,6 +26,8 @@ void JitArm64AsmRoutineManager::Generate()
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ABI_PushRegisters(regs_to_save);
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MOVI2R(X29, (u64)&PowerPC::ppcState);
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MOVI2R(X28, (u64)Memory::logical_base);
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FixupBranch to_dispatcher = B();
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// If we align the dispatcher to a page then we can load its location with one ADRP instruction
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@ -44,11 +46,11 @@ void JitArm64AsmRoutineManager::Generate()
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// This block of code gets the address of the compiled block of code
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// It runs though to the compiling portion if it isn't found
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LDR(INDEX_UNSIGNED, W28, X29, PPCSTATE_OFF(pc)); // Load the current PC into W28
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BFM(W28, WSP, 3, 2); // Wipe the top 3 bits. Same as PC & JIT_ICACHE_MASK
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LDR(INDEX_UNSIGNED, W26, X29, PPCSTATE_OFF(pc)); // Load the current PC into W26
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BFM(W26, WSP, 3, 2); // Wipe the top 3 bits. Same as PC & JIT_ICACHE_MASK
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MOVI2R(X27, (u64)jit->GetBlockCache()->iCache.data());
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LDR(W27, X27, X28);
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LDR(W27, X27, X26);
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FixupBranch JitBlock = TBNZ(W27, 7); // Test the 7th bit
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// Success, it is our Jitblock.
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