mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2025-07-23 06:09:50 -06:00
Moving pixel engine and command processor from core to video common. This will break previous save states. Adds decoding single pixels to texture decoder.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@4391 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
donkopunchstania
380
Source/Core/VideoCommon/Src/PixelEngine.cpp
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380
Source/Core/VideoCommon/Src/PixelEngine.cpp
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// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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// http://developer.nvidia.com/object/General_FAQ.html#t6 !!!!!
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#include "Common.h"
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#include "VideoCommon.h"
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#include "ChunkFile.h"
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#include "Atomic.h"
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#include "PixelEngine.h"
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#include "CommandProcessor.h"
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namespace PixelEngine
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{
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union UPEZConfReg
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{
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u16 Hex;
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struct
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{
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unsigned ZCompEnable : 1; // Z Comparator Enable
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unsigned Function : 3;
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unsigned ZUpdEnable : 1;
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unsigned : 11;
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};
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};
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union UPEAlphaConfReg
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{
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u16 Hex;
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struct
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{
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unsigned BMMath : 1; // GX_BM_BLEND || GX_BM_SUBSTRACT
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unsigned BMLogic : 1; // GX_BM_LOGIC
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unsigned Dither : 1;
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unsigned ColorUpdEnable : 1;
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unsigned AlphaUpdEnable : 1;
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unsigned DstFactor : 3;
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unsigned SrcFactor : 3;
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unsigned Substract : 1; // Additive mode by default
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unsigned BlendOperator : 4;
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};
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};
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union UPEDstAlphaConfReg
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{
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u16 Hex;
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struct
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{
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unsigned DstAlpha : 8;
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unsigned Enable : 1;
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unsigned : 7;
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};
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};
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union UPEAlphaModeConfReg
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{
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u16 Hex;
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struct
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{
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unsigned Threshold : 8;
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unsigned CompareMode : 8;
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};
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};
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// Not sure about this reg...
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union UPEAlphaReadReg
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{
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u16 Hex;
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struct
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{
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unsigned ReadMode : 3;
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unsigned : 13;
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};
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};
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// fifo Control Register
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union UPECtrlReg
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{
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struct
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{
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unsigned PETokenEnable : 1;
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unsigned PEFinishEnable : 1;
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unsigned PEToken : 1; // write only
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unsigned PEFinish : 1; // write only
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unsigned : 12;
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};
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u16 Hex;
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UPECtrlReg() {Hex = 0; }
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UPECtrlReg(u16 _hex) {Hex = _hex; }
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};
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// STATE_TO_SAVE
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static UPEZConfReg m_ZConf;
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static UPEAlphaConfReg m_AlphaConf;
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static UPEDstAlphaConfReg m_DstAlphaConf;
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static UPEAlphaModeConfReg m_AlphaModeConf;
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static UPEAlphaReadReg m_AlphaRead;
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static UPECtrlReg m_Control;
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//static u16 m_Token; // token value most recently encountered
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static bool g_bSignalTokenInterrupt;
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static bool g_bSignalFinishInterrupt;
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static int et_SetTokenOnMainThread;
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static int et_SetFinishOnMainThread;
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u16 bbox[4];
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bool bbox_active;
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enum
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{
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INT_CAUSE_PE_TOKEN = 0x200, // GP Token
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INT_CAUSE_PE_FINISH = 0x400, // GP Finished
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};
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void DoState(PointerWrap &p)
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{
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p.Do(m_ZConf);
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p.Do(m_AlphaConf);
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p.Do(m_DstAlphaConf);
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p.Do(m_AlphaModeConf);
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p.Do(m_AlphaRead);
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p.Do(m_Control);
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p.Do(CommandProcessor::fifo.PEToken);
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p.Do(g_bSignalTokenInterrupt);
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p.Do(g_bSignalFinishInterrupt);
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p.Do(bbox);
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p.Do(bbox_active);
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}
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void UpdateInterrupts();
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void SetToken_OnMainThread(u64 userdata, int cyclesLate);
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void SetFinish_OnMainThread(u64 userdata, int cyclesLate);
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void Init()
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{
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m_Control.Hex = 0;
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et_SetTokenOnMainThread = g_VideoInitialize.pRegisterEvent("SetToken", SetToken_OnMainThread);
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et_SetFinishOnMainThread = g_VideoInitialize.pRegisterEvent("SetFinish", SetFinish_OnMainThread);
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bbox[0] = 0x80;
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bbox[1] = 0xA0;
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bbox[2] = 0x80;
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bbox[3] = 0xA0;
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bbox_active = false;
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}
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void Read16(u16& _uReturnValue, const u32 _iAddress)
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{
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DEBUG_LOG(PIXELENGINE, "(r16) 0x%08x", _iAddress);
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switch (_iAddress & 0xFFF)
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{
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// CPU Direct Access EFB Raster State Config
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case PE_ZCONF:
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_uReturnValue = m_ZConf.Hex;
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INFO_LOG(PIXELENGINE, "(r16) ZCONF");
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break;
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case PE_ALPHACONF:
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// Most games read this early. no idea why.
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_uReturnValue = m_AlphaConf.Hex;
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INFO_LOG(PIXELENGINE, "(r16) ALPHACONF");
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break;
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case PE_DSTALPHACONF:
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_uReturnValue = m_DstAlphaConf.Hex;
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INFO_LOG(PIXELENGINE, "(r16) DSTALPHACONF");
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break;
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case PE_ALPHAMODE:
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_uReturnValue = m_AlphaModeConf.Hex;
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INFO_LOG(PIXELENGINE, "(r16) ALPHAMODE");
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break;
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case PE_ALPHAREAD:
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_uReturnValue = m_AlphaRead.Hex;
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WARN_LOG(PIXELENGINE, "(r16) ALPHAREAD");
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break;
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case PE_CTRL_REGISTER:
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_uReturnValue = m_Control.Hex;
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INFO_LOG(PIXELENGINE, "(r16) CTRL_REGISTER : %04x", _uReturnValue);
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break;
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case PE_TOKEN_REG:
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_uReturnValue = CommandProcessor::fifo.PEToken;
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INFO_LOG(PIXELENGINE, "(r16) TOKEN_REG : %04x", _uReturnValue);
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break;
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// The return values for these BBOX registers need to be gotten from the bounding box of the object.
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// See http://code.google.com/p/dolphin-emu/issues/detail?id=360#c74 for more details.
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// 0x80, 0xa0, 0x80, 0xa0 makes Paper Mario happy.
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case PE_BBOX_LEFT: _uReturnValue = bbox[0]; INFO_LOG(PIXELENGINE, "R: BBOX_LEFT = %i", bbox[0]); bbox_active = false; break;
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case PE_BBOX_RIGHT: _uReturnValue = bbox[1]; INFO_LOG(PIXELENGINE, "R: BBOX_RIGHT = %i", bbox[1]); bbox_active = false; break;
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case PE_BBOX_TOP: _uReturnValue = bbox[2]; INFO_LOG(PIXELENGINE, "R: BBOX_TOP = %i", bbox[2]); bbox_active = false; break;
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case PE_BBOX_BOTTOM: _uReturnValue = bbox[3]; INFO_LOG(PIXELENGINE, "R: BBOX_BOTTOM = %i", bbox[3]); bbox_active = false; break;
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case PE_PERF_0L:
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case PE_PERF_0H:
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case PE_PERF_1L:
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case PE_PERF_1H:
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case PE_PERF_2L:
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case PE_PERF_2H:
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case PE_PERF_3L:
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case PE_PERF_3H:
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case PE_PERF_4L:
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case PE_PERF_4H:
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case PE_PERF_5L:
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case PE_PERF_5H:
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INFO_LOG(PIXELENGINE, "(r16) perf counter @ %08x", _iAddress);
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break;
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default:
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INFO_LOG(PIXELENGINE, "(r16) unknown @ %08x", _iAddress);
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_uReturnValue = 1;
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break;
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}
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}
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void Write16(const u16 _iValue, const u32 _iAddress)
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{
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switch (_iAddress & 0xFFF)
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{
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// CPU Direct Access EFB Raster State Config
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case PE_ZCONF:
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m_ZConf.Hex = _iValue;
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INFO_LOG(PIXELENGINE, "(w16) ZCONF: %02x", _iValue);
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break;
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case PE_ALPHACONF:
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m_AlphaConf.Hex = _iValue;
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INFO_LOG(PIXELENGINE, "(w16) ALPHACONF: %02x", _iValue);
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break;
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case PE_DSTALPHACONF:
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m_DstAlphaConf.Hex = _iValue;
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INFO_LOG(PIXELENGINE, "(w16) DSTALPHACONF: %02x", _iValue);
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break;
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case PE_ALPHAMODE:
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m_AlphaModeConf.Hex = _iValue;
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INFO_LOG(PIXELENGINE, "(w16) ALPHAMODE: %02x", _iValue);
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break;
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case PE_ALPHAREAD:
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m_AlphaRead.Hex = _iValue;
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INFO_LOG(PIXELENGINE, "(w16) ALPHAREAD: %02x", _iValue);
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break;
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case PE_CTRL_REGISTER:
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{
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UPECtrlReg tmpCtrl(_iValue);
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if (tmpCtrl.PEToken) g_bSignalTokenInterrupt = false;
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if (tmpCtrl.PEFinish) g_bSignalFinishInterrupt = false;
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m_Control.PETokenEnable = tmpCtrl.PETokenEnable;
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m_Control.PEFinishEnable = tmpCtrl.PEFinishEnable;
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m_Control.PEToken = 0; // this flag is write only
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m_Control.PEFinish = 0; // this flag is write only
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DEBUG_LOG(PIXELENGINE, "(w16) CTRL_REGISTER: 0x%04x", _iValue);
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UpdateInterrupts();
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}
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break;
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case PE_TOKEN_REG:
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//LOG(PIXELENGINE,"WEIRD: program wrote token: %i",_iValue);
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PanicAlert("(w16) WTF? PowerPC program wrote token: %i", _iValue);
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//only the gx pipeline is supposed to be able to write here
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//g_token = _iValue;
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break;
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default:
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WARN_LOG(PIXELENGINE, "(w16) unknown %04x @ %08x", _iValue, _iAddress);
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break;
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}
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}
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void Write32(const u32 _iValue, const u32 _iAddress)
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{
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WARN_LOG(PIXELENGINE, "(w32) 0x%08x @ 0x%08x IGNORING...",_iValue,_iAddress);
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}
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bool AllowIdleSkipping()
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{
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return !g_VideoInitialize.bUseDualCore|| (!m_Control.PETokenEnable && !m_Control.PEFinishEnable);
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}
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void UpdateInterrupts()
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{
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// check if there is a token-interrupt
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if (g_bSignalTokenInterrupt & m_Control.PETokenEnable)
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g_VideoInitialize.pSetInterrupt(INT_CAUSE_PE_TOKEN, true);
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else
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g_VideoInitialize.pSetInterrupt(INT_CAUSE_PE_TOKEN, false);
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// check if there is a finish-interrupt
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if (g_bSignalFinishInterrupt & m_Control.PEFinishEnable)
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g_VideoInitialize.pSetInterrupt(INT_CAUSE_PE_FINISH, true);
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else
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g_VideoInitialize.pSetInterrupt(INT_CAUSE_PE_FINISH, false);
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}
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// TODO(mb2): Refactor SetTokenINT_OnMainThread(u64 userdata, int cyclesLate).
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// Think about the right order between tokenVal and tokenINT... one day maybe.
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// Cleanup++
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// Called only if BPMEM_PE_TOKEN_INT_ID is ack by GP
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void SetToken_OnMainThread(u64 userdata, int cyclesLate)
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{
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//if (userdata >> 16)
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//{
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g_bSignalTokenInterrupt = true;
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//_dbg_assert_msg_(PIXELENGINE, (CommandProcessor::fifo.PEToken == (userdata&0xFFFF)), "WTF? BPMEM_PE_TOKEN_INT_ID's token != BPMEM_PE_TOKEN_ID's token" );
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INFO_LOG(PIXELENGINE, "VIDEO Plugin raises INT_CAUSE_PE_TOKEN (btw, token: %04x)", CommandProcessor::fifo.PEToken);
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UpdateInterrupts();
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//}
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//else
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// LOGV(PIXELENGINE, 1, "VIDEO Plugin wrote token: %i", CommandProcessor::fifo.PEToken);
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}
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void SetFinish_OnMainThread(u64 userdata, int cyclesLate)
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{
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g_bSignalFinishInterrupt = 1;
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UpdateInterrupts();
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}
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// SetToken
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// THIS IS EXECUTED FROM VIDEO THREAD
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void SetToken(const u16 _token, const int _bSetTokenAcknowledge)
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{
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// TODO?: set-token-value and set-token-INT could be merged since set-token-INT own the token value.
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if (_bSetTokenAcknowledge) // set token INT
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{
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// This seems smelly...
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CommandProcessor::IncrementGPWDToken(); // for DC watchdog hack since PEToken seems to be a frame-finish too
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g_VideoInitialize.pScheduleEvent_Threadsafe(
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0, et_SetTokenOnMainThread, _token | (_bSetTokenAcknowledge << 16));
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}
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else // set token value
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{
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// we do it directly from videoThread because of
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// Super Monkey Ball
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// XXX: No 16-bit atomic store available, so cheat and use 32-bit.
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// That's what we've always done. We're counting on fifo.PEToken to be
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// 4-byte padded.
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Common::AtomicStore(*(volatile u32*)&CommandProcessor::fifo.PEToken, _token);
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}
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}
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// SetFinish
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// THIS IS EXECUTED FROM VIDEO THREAD (BPStructs.cpp) when a new frame has been drawn
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void SetFinish()
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{
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CommandProcessor::IncrementGPWDToken(); // for DC watchdog hack
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g_VideoInitialize.pScheduleEvent_Threadsafe(
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0, et_SetFinishOnMainThread, 0);
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INFO_LOG(PIXELENGINE, "VIDEO Set Finish");
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}
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} // end of namespace PixelEngine
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Block a user