From 575f1b309a4e6e9580bd62ab3c3e584811b4a9da Mon Sep 17 00:00:00 2001 From: Sintendo Date: Fri, 14 Sep 2018 21:56:29 +0200 Subject: [PATCH] x64Emitter: short MOV for 64bit immediates (1) Prior to this commit, the emitter would unconditionally emit a 10-byte instruction known as MOVABS when loading a 64-bit immediate to a register. 0: 48 b8 ef be ad de ff movabs rax,0xffffffffdeadbeef 7: ff ff ff With this change, it will instead emit a 7-byte instruction when it is possible to express the 64-bit immediate using a signed 32-bit value. 0: 48 c7 c0 ef be ad de mov rax,0xffffffffdeadbeef --- Source/Core/Common/x64Emitter.cpp | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/Source/Core/Common/x64Emitter.cpp b/Source/Core/Common/x64Emitter.cpp index d419f32af5..8e85e146b3 100644 --- a/Source/Core/Common/x64Emitter.cpp +++ b/Source/Core/Common/x64Emitter.cpp @@ -1469,11 +1469,21 @@ void OpArg::WriteNormalOp(XEmitter* emit, bool toRM, NormalOp op, const OpArg& o // mov reg64, imm64 else if (op == NormalOp::MOV) { - emit->Write8(0xB8 + (offsetOrBaseReg & 7)); - emit->Write64((u64)operand.offset); - return; + // movabs reg64, imm64 (10 bytes) + if (static_cast(operand.offset) != static_cast(operand.offset)) + { + emit->Write8(0xB8 + (offsetOrBaseReg & 7)); + emit->Write64(operand.offset); + return; + } + // mov reg64, simm32 (7 bytes) + emit->Write8(op_def.imm32); + immToWrite = 32; + } + else + { + ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - Only MOV can take 64-bit imm"); } - ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - Only MOV can take 64-bit imm"); } else {