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@ -75,10 +75,10 @@ union USIChannelOut
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u32 Hex;
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struct
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{
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unsigned OUTPUT1 : 8;
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unsigned OUTPUT0 : 8;
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unsigned CMD : 8;
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unsigned : 8;
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u32 OUTPUT1 : 8;
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u32 OUTPUT0 : 8;
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u32 CMD : 8;
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u32 : 8;
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};
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};
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@ -88,12 +88,12 @@ union USIChannelIn_Hi
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u32 Hex;
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struct
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{
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unsigned INPUT3 : 8;
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unsigned INPUT2 : 8;
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unsigned INPUT1 : 8;
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unsigned INPUT0 : 6;
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unsigned ERRLATCH : 1; // 0: no error 1: Error latched. Check SISR.
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unsigned ERRSTAT : 1; // 0: no error 1: error on last transfer
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u32 INPUT3 : 8;
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u32 INPUT2 : 8;
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u32 INPUT1 : 8;
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u32 INPUT0 : 6;
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u32 ERRLATCH : 1; // 0: no error 1: Error latched. Check SISR.
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u32 ERRSTAT : 1; // 0: no error 1: error on last transfer
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};
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};
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@ -103,10 +103,10 @@ union USIChannelIn_Lo
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u32 Hex;
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struct
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{
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unsigned INPUT7 : 8;
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unsigned INPUT6 : 8;
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unsigned INPUT5 : 8;
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unsigned INPUT4 : 8;
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u32 INPUT7 : 8;
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u32 INPUT6 : 8;
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u32 INPUT5 : 8;
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u32 INPUT4 : 8;
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};
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};
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@ -125,17 +125,17 @@ union USIPoll
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u32 Hex;
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struct
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{
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unsigned VBCPY3 : 1; // 1: write to output buffer only on vblank
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unsigned VBCPY2 : 1;
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unsigned VBCPY1 : 1;
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unsigned VBCPY0 : 1;
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unsigned EN3 : 1; // Enable polling of channel
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unsigned EN2 : 1; // does not affect communication RAM transfers
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unsigned EN1 : 1;
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unsigned EN0 : 1;
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unsigned Y : 8; // Polls per frame
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unsigned X : 10; // Polls per X lines. begins at vsync, min 7, max depends on video mode
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unsigned : 6;
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u32 VBCPY3 : 1; // 1: write to output buffer only on vblank
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u32 VBCPY2 : 1;
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u32 VBCPY1 : 1;
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u32 VBCPY0 : 1;
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u32 EN3 : 1; // Enable polling of channel
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u32 EN2 : 1; // does not affect communication RAM transfers
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u32 EN1 : 1;
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u32 EN0 : 1;
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u32 Y : 8; // Polls per frame
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u32 X : 10; // Polls per X lines. begins at vsync, min 7, max depends on video mode
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u32 : 6;
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};
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};
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@ -145,22 +145,22 @@ union USIComCSR
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u32 Hex;
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struct
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{
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unsigned TSTART : 1; // write: start transfer read: transfer status
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unsigned CHANNEL : 2; // determines which SI channel will be used on the communication interface.
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unsigned : 3;
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unsigned CALLBEN : 1; // Callback enable
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unsigned CMDEN : 1; // Command enable?
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unsigned INLNGTH : 7;
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unsigned : 1;
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unsigned OUTLNGTH : 7; // Communication Channel Output Length in bytes
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unsigned : 1;
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unsigned CHANEN : 1; // Channel enable?
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unsigned CHANNUM : 2; // Channel number?
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unsigned RDSTINTMSK : 1; // Read Status Interrupt Status Mask
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unsigned RDSTINT : 1; // Read Status Interrupt Status
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unsigned COMERR : 1; // Communication Error (set 0)
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unsigned TCINTMSK : 1; // Transfer Complete Interrupt Mask
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unsigned TCINT : 1; // Transfer Complete Interrupt
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u32 TSTART : 1; // write: start transfer read: transfer status
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u32 CHANNEL : 2; // determines which SI channel will be used on the communication interface.
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u32 : 3;
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u32 CALLBEN : 1; // Callback enable
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u32 CMDEN : 1; // Command enable?
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u32 INLNGTH : 7;
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u32 : 1;
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u32 OUTLNGTH : 7; // Communication Channel Output Length in bytes
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u32 : 1;
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u32 CHANEN : 1; // Channel enable?
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u32 CHANNUM : 2; // Channel number?
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u32 RDSTINTMSK : 1; // Read Status Interrupt Status Mask
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u32 RDSTINT : 1; // Read Status Interrupt Status
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u32 COMERR : 1; // Communication Error (set 0)
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u32 TCINTMSK : 1; // Transfer Complete Interrupt Mask
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u32 TCINT : 1; // Transfer Complete Interrupt
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};
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USIComCSR() {Hex = 0;}
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USIComCSR(u32 _hex) {Hex = _hex;}
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@ -172,35 +172,35 @@ union USIStatusReg
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u32 Hex;
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struct
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{
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unsigned UNRUN3 : 1; // (RWC) write 1: bit cleared read 1: main proc underrun error
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unsigned OVRUN3 : 1; // (RWC) write 1: bit cleared read 1: overrun error
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unsigned COLL3 : 1; // (RWC) write 1: bit cleared read 1: collision error
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unsigned NOREP3 : 1; // (RWC) write 1: bit cleared read 1: response error
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unsigned WRST3 : 1; // (R) 1: buffer channel0 not copied
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unsigned RDST3 : 1; // (R) 1: new Data available
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unsigned : 2; // 7:6
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unsigned UNRUN2 : 1; // (RWC) write 1: bit cleared read 1: main proc underrun error
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unsigned OVRUN2 : 1; // (RWC) write 1: bit cleared read 1: overrun error
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unsigned COLL2 : 1; // (RWC) write 1: bit cleared read 1: collision error
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unsigned NOREP2 : 1; // (RWC) write 1: bit cleared read 1: response error
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unsigned WRST2 : 1; // (R) 1: buffer channel0 not copied
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unsigned RDST2 : 1; // (R) 1: new Data available
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unsigned : 2; // 15:14
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unsigned UNRUN1 : 1; // (RWC) write 1: bit cleared read 1: main proc underrun error
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unsigned OVRUN1 : 1; // (RWC) write 1: bit cleared read 1: overrun error
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unsigned COLL1 : 1; // (RWC) write 1: bit cleared read 1: collision error
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unsigned NOREP1 : 1; // (RWC) write 1: bit cleared read 1: response error
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unsigned WRST1 : 1; // (R) 1: buffer channel0 not copied
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unsigned RDST1 : 1; // (R) 1: new Data available
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unsigned : 2; // 23:22
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unsigned UNRUN0 : 1; // (RWC) write 1: bit cleared read 1: main proc underrun error
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unsigned OVRUN0 : 1; // (RWC) write 1: bit cleared read 1: overrun error
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unsigned COLL0 : 1; // (RWC) write 1: bit cleared read 1: collision error
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unsigned NOREP0 : 1; // (RWC) write 1: bit cleared read 1: response error
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unsigned WRST0 : 1; // (R) 1: buffer channel0 not copied
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unsigned RDST0 : 1; // (R) 1: new Data available
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unsigned : 1;
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unsigned WR : 1; // (RW) write 1 start copy, read 0 copy done
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u32 UNRUN3 : 1; // (RWC) write 1: bit cleared read 1: main proc underrun error
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u32 OVRUN3 : 1; // (RWC) write 1: bit cleared read 1: overrun error
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u32 COLL3 : 1; // (RWC) write 1: bit cleared read 1: collision error
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u32 NOREP3 : 1; // (RWC) write 1: bit cleared read 1: response error
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u32 WRST3 : 1; // (R) 1: buffer channel0 not copied
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u32 RDST3 : 1; // (R) 1: new Data available
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u32 : 2; // 7:6
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u32 UNRUN2 : 1; // (RWC) write 1: bit cleared read 1: main proc underrun error
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u32 OVRUN2 : 1; // (RWC) write 1: bit cleared read 1: overrun error
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u32 COLL2 : 1; // (RWC) write 1: bit cleared read 1: collision error
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u32 NOREP2 : 1; // (RWC) write 1: bit cleared read 1: response error
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u32 WRST2 : 1; // (R) 1: buffer channel0 not copied
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u32 RDST2 : 1; // (R) 1: new Data available
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u32 : 2; // 15:14
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u32 UNRUN1 : 1; // (RWC) write 1: bit cleared read 1: main proc underrun error
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u32 OVRUN1 : 1; // (RWC) write 1: bit cleared read 1: overrun error
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u32 COLL1 : 1; // (RWC) write 1: bit cleared read 1: collision error
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u32 NOREP1 : 1; // (RWC) write 1: bit cleared read 1: response error
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u32 WRST1 : 1; // (R) 1: buffer channel0 not copied
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u32 RDST1 : 1; // (R) 1: new Data available
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u32 : 2; // 23:22
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u32 UNRUN0 : 1; // (RWC) write 1: bit cleared read 1: main proc underrun error
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u32 OVRUN0 : 1; // (RWC) write 1: bit cleared read 1: overrun error
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u32 COLL0 : 1; // (RWC) write 1: bit cleared read 1: collision error
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u32 NOREP0 : 1; // (RWC) write 1: bit cleared read 1: response error
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u32 WRST0 : 1; // (R) 1: buffer channel0 not copied
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u32 RDST0 : 1; // (R) 1: new Data available
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u32 : 1;
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u32 WR : 1; // (RW) write 1 start copy, read 0 copy done
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};
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USIStatusReg() {Hex = 0;}
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USIStatusReg(u32 _hex) {Hex = _hex;}
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@ -212,8 +212,8 @@ union USIEXIClockCount
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u32 Hex;
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struct
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{
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unsigned LOCK : 1; // 1: prevents CPU from setting EXI clock to 32MHz
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unsigned : 30;
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u32 LOCK : 1; // 1: prevents CPU from setting EXI clock to 32MHz
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u32 : 0;
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};
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};
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@ -249,9 +249,13 @@ void Init()
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g_Poll.Hex = 0;
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g_Poll.X = 7;
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g_ComCSR.Hex = 0;
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g_StatusReg.Hex = 0;
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g_EXIClockCount.Hex = 0;
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g_EXIClockCount.LOCK = 1;
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memset(g_SIBuffer, 0, 128);
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changeDevice = CoreTiming::RegisterEvent("ChangeSIDevice", ChangeDeviceCallback);
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@ -286,13 +290,11 @@ void Read32(u32& _uReturnValue, const u32 _iAddress)
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return;
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case SI_CHANNEL_0_IN_HI:
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g_StatusReg.RDST0 = 0;
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UpdateInterrupts();
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_uReturnValue = g_Channel[0].m_InHi.Hex;
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return;
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case SI_CHANNEL_0_IN_LO:
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g_StatusReg.RDST0 = 0;
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UpdateInterrupts();
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_uReturnValue = g_Channel[0].m_InLo.Hex;
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return;
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@ -305,13 +307,11 @@ void Read32(u32& _uReturnValue, const u32 _iAddress)
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return;
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case SI_CHANNEL_1_IN_HI:
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g_StatusReg.RDST1 = 0;
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UpdateInterrupts();
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_uReturnValue = g_Channel[1].m_InHi.Hex;
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return;
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case SI_CHANNEL_1_IN_LO:
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g_StatusReg.RDST1 = 0;
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UpdateInterrupts();
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_uReturnValue = g_Channel[1].m_InLo.Hex;
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return;
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@ -324,13 +324,11 @@ void Read32(u32& _uReturnValue, const u32 _iAddress)
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return;
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case SI_CHANNEL_2_IN_HI:
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g_StatusReg.RDST2 = 0;
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UpdateInterrupts();
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_uReturnValue = g_Channel[2].m_InHi.Hex;
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return;
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case SI_CHANNEL_2_IN_LO:
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g_StatusReg.RDST2 = 0;
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UpdateInterrupts();
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_uReturnValue = g_Channel[2].m_InLo.Hex;
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return;
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@ -343,13 +341,11 @@ void Read32(u32& _uReturnValue, const u32 _iAddress)
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return;
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case SI_CHANNEL_3_IN_HI:
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g_StatusReg.RDST3 = 0;
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UpdateInterrupts();
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_uReturnValue = g_Channel[3].m_InHi.Hex;
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return;
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case SI_CHANNEL_3_IN_LO:
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g_StatusReg.RDST3 = 0;
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UpdateInterrupts();
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_uReturnValue = g_Channel[3].m_InLo.Hex;
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return;
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@ -402,7 +398,7 @@ void Write32(const u32 _iValue, const u32 _iAddress)
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case SI_CHANNEL_3_IN_LO: g_Channel[3].m_InLo.Hex = _iValue; break;
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case SI_POLL:
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INFO_LOG(SERIALINTERFACE, "Poll: X=%03d Y=%03d %s%s%s%s%s%s%s%s",
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INFO_LOG(SERIALINTERFACE, "Wrote Poll: X=%03d Y=%03d %s%s%s%s%s%s%s%s",
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g_Poll.X, g_Poll.Y,
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g_Poll.EN0 ? "EN0 ":" ", g_Poll.EN1 ? "EN1 ":" ",
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g_Poll.EN2 ? "EN2 ":" ", g_Poll.EN3 ? "EN3 ":" ",
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@ -478,12 +474,12 @@ void Write32(const u32 _iValue, const u32 _iAddress)
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g_EXIClockCount.Hex = _iValue;
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break;
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case 0x80:
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case 0x80: // Bogus? never seen it with ma own eyes
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INFO_LOG(SERIALINTERFACE, "WII something at 0xCD006480");
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break;
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default:
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_dbg_assert_(SERIALINTERFACE,0);
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_dbg_assert_(SERIALINTERFACE, 0);
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break;
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}
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}
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@ -522,11 +518,8 @@ void GenerateSIInterrupt(SIInterruptType _SIInterrupt)
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void RemoveDevice(int _iDeviceNumber)
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{
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if (g_Channel[_iDeviceNumber].m_pDevice != NULL)
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{
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delete g_Channel[_iDeviceNumber].m_pDevice;
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g_Channel[_iDeviceNumber].m_pDevice = NULL;
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}
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delete g_Channel[_iDeviceNumber].m_pDevice;
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g_Channel[_iDeviceNumber].m_pDevice = NULL;
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}
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void AddDevice(const TSIDevices _device, int _iDeviceNumber)
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@ -538,54 +531,50 @@ void AddDevice(const TSIDevices _device, int _iDeviceNumber)
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// create the new one
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g_Channel[_iDeviceNumber].m_pDevice = SIDevice_Create(_device, _iDeviceNumber);
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_dbg_assert_(SERIALINTERFACE, g_Channel[_iDeviceNumber].m_pDevice != NULL);
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}
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void SetNoResponse(u32 channel)
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{
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// raise the NO RESPONSE error
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switch (channel)
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{
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case 0: g_StatusReg.NOREP0 = 1; break;
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case 1: g_StatusReg.NOREP1 = 1; break;
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case 2: g_StatusReg.NOREP2 = 1; break;
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case 3: g_StatusReg.NOREP3 = 1; break;
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}
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g_ComCSR.COMERR = 1;
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}
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void ChangeDeviceCallback(u64 userdata, int cyclesLate)
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{
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u8 channel = (u8)(userdata >> 32);
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// doubt this matters...
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g_Channel[channel].m_Out.Hex = 0;
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g_Channel[channel].m_InHi.Hex = 0;
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g_Channel[channel].m_InLo.Hex = 0;
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// raise the NO RESPONSE error
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switch (channel)
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{
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case 0:
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g_StatusReg.NOREP0 = 1;
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break;
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case 1:
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g_StatusReg.NOREP1 = 1;
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break;
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case 2:
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g_StatusReg.NOREP2 = 1;
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break;
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case 3:
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g_StatusReg.NOREP3 = 1;
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break;
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}
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SetNoResponse(channel);
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AddDevice((TSIDevices)(u32)userdata, channel);
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}
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void ChangeDevice(TSIDevices device, int deviceNumber)
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void ChangeDevice(TSIDevices device, int channel)
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{
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// Called from GUI, so we need to make it thread safe.
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// Let the hardware see no device for .5b cycles
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CoreTiming::ScheduleEvent_Threadsafe(0, changeDevice, (SI_DUMMY | (u64)deviceNumber << 32));
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CoreTiming::ScheduleEvent_Threadsafe(500000000, changeDevice, (device | (u64)deviceNumber << 32));
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CoreTiming::ScheduleEvent_Threadsafe(0, changeDevice, ((u64)channel << 32) | SI_NONE);
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CoreTiming::ScheduleEvent_Threadsafe(500000000, changeDevice, ((u64)channel << 32) | device);
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}
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void UpdateDevices()
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{
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// Update channels
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g_StatusReg.RDST0 = g_Channel[0].m_pDevice->GetData(g_Channel[0].m_InHi.Hex, g_Channel[0].m_InLo.Hex) ? 1 : 0;
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g_StatusReg.RDST1 = g_Channel[1].m_pDevice->GetData(g_Channel[1].m_InHi.Hex, g_Channel[1].m_InLo.Hex) ? 1 : 0;
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g_StatusReg.RDST2 = g_Channel[2].m_pDevice->GetData(g_Channel[2].m_InHi.Hex, g_Channel[2].m_InLo.Hex) ? 1 : 0;
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g_StatusReg.RDST3 = g_Channel[3].m_pDevice->GetData(g_Channel[3].m_InHi.Hex, g_Channel[3].m_InLo.Hex) ? 1 : 0;
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// Update channels and set the status bit if there's new data
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g_StatusReg.RDST0 = !!g_Channel[0].m_pDevice->GetData(g_Channel[0].m_InHi.Hex, g_Channel[0].m_InLo.Hex);
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g_StatusReg.RDST1 = !!g_Channel[1].m_pDevice->GetData(g_Channel[1].m_InHi.Hex, g_Channel[1].m_InLo.Hex);
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g_StatusReg.RDST2 = !!g_Channel[2].m_pDevice->GetData(g_Channel[2].m_InHi.Hex, g_Channel[2].m_InLo.Hex);
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g_StatusReg.RDST3 = !!g_Channel[3].m_pDevice->GetData(g_Channel[3].m_InHi.Hex, g_Channel[3].m_InLo.Hex);
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// Update interrupts
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UpdateInterrupts();
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}
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