diff --git a/Source/Core/Core/PowerPC/Interpreter/Interpreter.cpp b/Source/Core/Core/PowerPC/Interpreter/Interpreter.cpp index b13c858858..23e722f713 100644 --- a/Source/Core/Core/PowerPC/Interpreter/Interpreter.cpp +++ b/Source/Core/Core/PowerPC/Interpreter/Interpreter.cpp @@ -131,7 +131,7 @@ static void Trace(const UGeckoInstruction& inst) DEBUG_LOG_FMT(POWERPC, "INTER PC: {:08x} SRR0: {:08x} SRR1: {:08x} CRval: {:016x} " "FPSCR: {:08x} MSR: {:08x} LR: {:08x} {} {:08x} {}", - PowerPC::ppcState.pc, SRR0, SRR1, PowerPC::ppcState.cr.fields[0], + PowerPC::ppcState.pc, SRR0(PowerPC::ppcState), SRR1, PowerPC::ppcState.cr.fields[0], PowerPC::ppcState.fpscr.Hex, PowerPC::ppcState.msr.Hex, PowerPC::ppcState.spr[8], regs, inst.hex, ppc_inst); } diff --git a/Source/Core/Core/PowerPC/Interpreter/Interpreter_Branch.cpp b/Source/Core/Core/PowerPC/Interpreter/Interpreter_Branch.cpp index 89a819b34c..ef1cde4463 100644 --- a/Source/Core/Core/PowerPC/Interpreter/Interpreter_Branch.cpp +++ b/Source/Core/Core/PowerPC/Interpreter/Interpreter_Branch.cpp @@ -118,7 +118,7 @@ void Interpreter::rfi(UGeckoInstruction inst) // PowerPC::CheckExceptions(); // else // set NPC to saved offset and resume - PowerPC::ppcState.npc = SRR0; + PowerPC::ppcState.npc = SRR0(PowerPC::ppcState); m_end_block = true; } diff --git a/Source/Core/Core/PowerPC/Jit64/Jit.cpp b/Source/Core/Core/PowerPC/Jit64/Jit.cpp index 2a2d62b6b5..e6544d1c66 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit.cpp @@ -759,7 +759,7 @@ void Jit64::Trace() DEBUG_LOG_FMT(DYNA_REC, "JIT64 PC: {:08x} SRR0: {:08x} SRR1: {:08x} FPSCR: {:08x} " "MSR: {:08x} LR: {:08x} {} {}", - PowerPC::ppcState.pc, SRR0, SRR1, PowerPC::ppcState.fpscr.Hex, + PowerPC::ppcState.pc, SRR0(PowerPC::ppcState), SRR1, PowerPC::ppcState.fpscr.Hex, PowerPC::ppcState.msr.Hex, PowerPC::ppcState.spr[8], regs, fregs); } diff --git a/Source/Core/Core/PowerPC/JitArm64/Jit.cpp b/Source/Core/Core/PowerPC/JitArm64/Jit.cpp index 496b76ae01..bb9c3fd7ed 100644 --- a/Source/Core/Core/PowerPC/JitArm64/Jit.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/Jit.cpp @@ -705,7 +705,7 @@ void JitArm64::Trace() DEBUG_LOG_FMT(DYNA_REC, "JitArm64 PC: {:08x} SRR0: {:08x} SRR1: {:08x} FPSCR: {:08x} " "MSR: {:08x} LR: {:08x} {} {}", - PowerPC::ppcState.pc, SRR0, SRR1, PowerPC::ppcState.fpscr.Hex, + PowerPC::ppcState.pc, SRR0(PowerPC::ppcState), SRR1, PowerPC::ppcState.fpscr.Hex, PowerPC::ppcState.msr.Hex, PowerPC::ppcState.spr[8], regs, fregs); } diff --git a/Source/Core/Core/PowerPC/PowerPC.cpp b/Source/Core/Core/PowerPC/PowerPC.cpp index 646605d715..aa6306f91c 100644 --- a/Source/Core/Core/PowerPC/PowerPC.cpp +++ b/Source/Core/Core/PowerPC/PowerPC.cpp @@ -489,7 +489,7 @@ void CheckExceptions() if (exceptions & EXCEPTION_ISI) { - SRR0 = PowerPC::ppcState.npc; + SRR0(PowerPC::ppcState) = PowerPC::ppcState.npc; // Page fault occurred SRR1 = (PowerPC::ppcState.msr.Hex & 0x87C0FFFF) | (1 << 30); PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE; @@ -501,7 +501,7 @@ void CheckExceptions() } else if (exceptions & EXCEPTION_PROGRAM) { - SRR0 = PowerPC::ppcState.pc; + SRR0(PowerPC::ppcState) = PowerPC::ppcState.pc; // SRR1 was partially set by GenerateProgramException, so bitwise or is used here SRR1 |= PowerPC::ppcState.msr.Hex & 0x87C0FFFF; PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE; @@ -513,7 +513,7 @@ void CheckExceptions() } else if (exceptions & EXCEPTION_SYSCALL) { - SRR0 = PowerPC::ppcState.npc; + SRR0(PowerPC::ppcState) = PowerPC::ppcState.npc; SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF; PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE; PowerPC::ppcState.msr.Hex &= ~0x04EF36; @@ -525,7 +525,7 @@ void CheckExceptions() else if (exceptions & EXCEPTION_FPU_UNAVAILABLE) { // This happens a lot - GameCube OS uses deferred FPU context switching - SRR0 = PowerPC::ppcState.pc; // re-execute the instruction + SRR0(PowerPC::ppcState) = PowerPC::ppcState.pc; // re-execute the instruction SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF; PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE; PowerPC::ppcState.msr.Hex &= ~0x04EF36; @@ -540,7 +540,7 @@ void CheckExceptions() } else if (exceptions & EXCEPTION_DSI) { - SRR0 = PowerPC::ppcState.pc; + SRR0(PowerPC::ppcState) = PowerPC::ppcState.pc; SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF; PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE; PowerPC::ppcState.msr.Hex &= ~0x04EF36; @@ -552,7 +552,7 @@ void CheckExceptions() } else if (exceptions & EXCEPTION_ALIGNMENT) { - SRR0 = PowerPC::ppcState.pc; + SRR0(PowerPC::ppcState) = PowerPC::ppcState.pc; SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF; PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE; PowerPC::ppcState.msr.Hex &= ~0x04EF36; @@ -582,7 +582,7 @@ void CheckExternalExceptions() if (exceptions & EXCEPTION_EXTERNAL_INT) { // Pokemon gets this "too early", it hasn't a handler yet - SRR0 = PowerPC::ppcState.npc; + SRR0(PowerPC::ppcState) = PowerPC::ppcState.npc; SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF; PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE; PowerPC::ppcState.msr.Hex &= ~0x04EF36; @@ -595,7 +595,7 @@ void CheckExternalExceptions() } else if (exceptions & EXCEPTION_PERFORMANCE_MONITOR) { - SRR0 = PowerPC::ppcState.npc; + SRR0(PowerPC::ppcState) = PowerPC::ppcState.npc; SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF; PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE; PowerPC::ppcState.msr.Hex &= ~0x04EF36; @@ -606,7 +606,7 @@ void CheckExternalExceptions() } else if (exceptions & EXCEPTION_DECREMENTER) { - SRR0 = PowerPC::ppcState.npc; + SRR0(PowerPC::ppcState) = PowerPC::ppcState.npc; SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF; PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE; PowerPC::ppcState.msr.Hex &= ~0x04EF36; diff --git a/Source/Core/Core/PowerPC/PowerPC.h b/Source/Core/Core/PowerPC/PowerPC.h index 0bdb64b9fc..6a278d3bbd 100644 --- a/Source/Core/Core/PowerPC/PowerPC.h +++ b/Source/Core/Core/PowerPC/PowerPC.h @@ -248,7 +248,7 @@ void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst); #define LR(ppc_state) (ppc_state).spr[SPR_LR] #define CTR(ppc_state) (ppc_state).spr[SPR_CTR] -#define SRR0 PowerPC::ppcState.spr[SPR_SRR0] +#define SRR0(ppc_state) (ppc_state).spr[SPR_SRR0] #define SRR1 PowerPC::ppcState.spr[SPR_SRR1] #define SPRG0 PowerPC::ppcState.spr[SPR_SPRG0] #define SPRG1 PowerPC::ppcState.spr[SPR_SPRG1]