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Core/PowerPC: Split 'IsRAMAddress' method into 'IsEffectiveRAMAddress' and 'IsPhysicalRAMAddress' methods

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This commit is contained in:
Dr. Dystopia
2024-07-16 12:10:48 +02:00
parent 95f6c76713
commit 6591fa3751
2 changed files with 23 additions and 23 deletions
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43
Source/Core/Core/PowerPC/MMU.cpp
View File

@ -937,39 +937,35 @@ bool MMU::IsOptimizableRAMAddress(const u32 address, const u32 access_size) cons
return (bat_result_1 & bat_result_2 & BAT_PHYSICAL_BIT) != 0; return (bat_result_1 & bat_result_2 & BAT_PHYSICAL_BIT) != 0;
} }
template <XCheckTLBFlag flag> bool MMU::IsPhysicalRAMAddress(const u32 address) const
bool MMU::IsRAMAddress(u32 address, bool translate)
{ {
if (translate) const u32 segment = address >> 28;
{
auto translate_address = TranslateAddress<flag>(address);
if (!translate_address.Success())
return false;
address = translate_address.address;
}
u32 segment = address >> 28;
if (m_memory.GetRAM() && segment == 0x0 && (address & 0x0FFFFFFF) < m_memory.GetRamSizeReal()) if (m_memory.GetRAM() && segment == 0x0 && (address & 0x0FFFFFFF) < m_memory.GetRamSizeReal())
{ {
return true; return true;
} }
else if (m_memory.GetEXRAM() && segment == 0x1 && if (m_memory.GetEXRAM() && segment == 0x1 && (address & 0x0FFFFFFF) < m_memory.GetExRamSizeReal())
(address & 0x0FFFFFFF) < m_memory.GetExRamSizeReal())
{ {
return true; return true;
} }
else if (m_memory.GetFakeVMEM() && ((address & 0xFE000000) == 0x7E000000)) if (m_memory.GetFakeVMEM() && (address & 0xFE000000) == 0x7E000000)
{ {
return true; return true;
} }
else if (m_memory.GetL1Cache() && segment == 0xE && if (m_memory.GetL1Cache() && segment == 0xE && address < 0xE0000000 + m_memory.GetL1CacheSize())
(address < (0xE0000000 + m_memory.GetL1CacheSize())))
{ {
return true; return true;
} }
return false; return false;
} }
template <XCheckTLBFlag flag>
bool MMU::IsEffectiveRAMAddress(const u32 address)
{
const auto translate_address = TranslateAddress<flag>(address);
return translate_address.Success() && IsPhysicalRAMAddress(translate_address.address);
}
bool MMU::HostIsRAMAddress(const Core::CPUThreadGuard& guard, u32 address, bool MMU::HostIsRAMAddress(const Core::CPUThreadGuard& guard, u32 address,
RequestedAddressSpace space) RequestedAddressSpace space)
{ {
@ -977,13 +973,14 @@ bool MMU::HostIsRAMAddress(const Core::CPUThreadGuard& guard, u32 address,
switch (space) switch (space)
{ {
case RequestedAddressSpace::Effective: case RequestedAddressSpace::Effective:
return mmu.IsRAMAddress<XCheckTLBFlag::NoException>(address, mmu.m_ppc_state.msr.DR); return mmu.m_ppc_state.msr.DR ? mmu.IsEffectiveRAMAddress<XCheckTLBFlag::NoException>(address) :
mmu.IsPhysicalRAMAddress(address);
case RequestedAddressSpace::Physical: case RequestedAddressSpace::Physical:
return mmu.IsRAMAddress<XCheckTLBFlag::NoException>(address, false); return mmu.IsPhysicalRAMAddress(address);
case RequestedAddressSpace::Virtual: case RequestedAddressSpace::Virtual:
if (!mmu.m_ppc_state.msr.DR) if (!mmu.m_ppc_state.msr.DR)
return false; return false;
return mmu.IsRAMAddress<XCheckTLBFlag::NoException>(address, true); return mmu.IsEffectiveRAMAddress<XCheckTLBFlag::NoException>(address);
} }
ASSERT(false); ASSERT(false);
@ -1001,13 +998,15 @@ bool MMU::HostIsInstructionRAMAddress(const Core::CPUThreadGuard& guard, u32 add
switch (space) switch (space)
{ {
case RequestedAddressSpace::Effective: case RequestedAddressSpace::Effective:
return mmu.IsRAMAddress<XCheckTLBFlag::OpcodeNoException>(address, mmu.m_ppc_state.msr.IR); return mmu.m_ppc_state.msr.IR ?
mmu.IsEffectiveRAMAddress<XCheckTLBFlag::OpcodeNoException>(address) :
mmu.IsPhysicalRAMAddress(address);
case RequestedAddressSpace::Physical: case RequestedAddressSpace::Physical:
return mmu.IsRAMAddress<XCheckTLBFlag::OpcodeNoException>(address, false); return mmu.IsPhysicalRAMAddress(address);
case RequestedAddressSpace::Virtual: case RequestedAddressSpace::Virtual:
if (!mmu.m_ppc_state.msr.IR) if (!mmu.m_ppc_state.msr.IR)
return false; return false;
return mmu.IsRAMAddress<XCheckTLBFlag::OpcodeNoException>(address, true); return mmu.IsEffectiveRAMAddress<XCheckTLBFlag::OpcodeNoException>(address);
} }
ASSERT(false); ASSERT(false);

3
Source/Core/Core/PowerPC/MMU.h
View File

@ -310,7 +310,8 @@ private:
template <XCheckTLBFlag flag, bool never_translate = false> template <XCheckTLBFlag flag, bool never_translate = false>
void WriteToHardware(u32 em_address, const u32 data, const u32 size); void WriteToHardware(u32 em_address, const u32 data, const u32 size);
template <XCheckTLBFlag flag> template <XCheckTLBFlag flag>
bool IsRAMAddress(u32 address, bool translate); bool IsEffectiveRAMAddress(u32 address);
bool IsPhysicalRAMAddress(u32 address) const;
template <typename T> template <typename T>
static std::optional<ReadResult<T>> HostTryReadUX(const Core::CPUThreadGuard& guard, static std::optional<ReadResult<T>> HostTryReadUX(const Core::CPUThreadGuard& guard,