mirror of
https://github.com/dolphin-emu/dolphin.git
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Meta:
Using Unix tools to operate on a tree containing filename with spaces in them is really annoying, so rename the handful of instances where there were spaces. Host.cpp has never been used. Games tend to lookup the following directories that we don't yet have anything to put in, so prepopulate them in Data/User/Wii: title/00010001 title/00010002 title/00010003 title/00010004 title/00010005 title/00010006 title/00010007 meta shared2/title Set eol-style native on a number of text files which didn't already have it. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@5572 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
Soren Jorvang
@ -1,314 +1,314 @@
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; This test checks the effect of the index looping registers (R8-R11)
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incdir "tests"
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include "dsp_base.inc"
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; Tests done using AR1 = 0x0010, IX1 = 0. WR1 (wrap 1) means WR1.
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; WR1 = 0
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; 10, 10, 10, 10,
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; WR1 = 1
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; 10, 11, 10, 11,
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; WR1 = 2
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; 10, 12, 11, 13, 12, 11, 13, 12, 11, 13, 12, 11
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; WR1 = 3
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; 10, 13, 12, 11, 10, 13, 12...
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; WR1 = 4
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; 10, 14, 13, 17, 16, 15, 14, 13, 17, 16, 15, 14, 13, ...
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; WR1 = 5
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; 10, 15, 14, 13, 12, 17, 16, 15, 14, 13, 12, 17,
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; WR1 = 6
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; 10, 16, 15, 14, 13, 12, 11, 17, 16, 15, 14, 13
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; WR1 = 7
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; 10, 17, 16, 15, .. normal
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; WR1 = 8
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; 10, 18, 17, 1f, 1e, 1d, 1c, 1b, 1a, 19, 18, 17, 1f, 1e, .....
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; I really don't know how the above could possibly be efficiently implemented in hardware.
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; And thus it's tricky to implement in software too :p
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; test using indexing register 1 - 0 is used in send_back
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lri $AR1, #16
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lri $IX1, #32
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lri $WR1, #0
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call send_back ; 1
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nx'dr : $AR1
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call send_back ; 1
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nx'dr : $AR1
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call send_back ; 1
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nx'dr : $AR1
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call send_back ; 1
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lri $AR1, #16
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lri $WR1, #1
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call send_back ; 1
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nx'dr : $AR1
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call send_back ; 1
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nx'dr : $AR1
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call send_back ; 1
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nx'dr : $AR1
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call send_back ; 1
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nx'dr : $AR1
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call send_back ; 1
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lri $AR1, #16
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lri $WR1, #2
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call send_back ; 1
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nx'dr : $AR1
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call send_back ; 1
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nx'dr : $AR1
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call send_back ; 1
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nx'dr : $AR1
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||||
call send_back ; 1
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nx'dr : $AR1
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||||
call send_back ; 1
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||||
nx'dr : $AR1
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||||
call send_back ; 1
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nx'dr : $AR1
|
||||
call send_back ; 1
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nx'dr : $AR1
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call send_back ; 1
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nx'dr : $AR1
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call send_back ; 1
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lri $AR1, #16
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lri $WR1, #3
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call send_back ; 1
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nx'dr : $AR1
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call send_back ; 1
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nx'dr : $AR1
|
||||
call send_back ; 1
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nx'dr : $AR1
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||||
call send_back ; 1
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nx'dr : $AR1
|
||||
call send_back ; 1
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nx'dr : $AR1
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||||
call send_back ; 1
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nx'dr : $AR1
|
||||
call send_back ; 1
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nx'dr : $AR1
|
||||
call send_back ; 1
|
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nx'dr : $AR1
|
||||
call send_back ; 1
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nx'dr : $AR1
|
||||
call send_back ; 1
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nx'dr : $AR1
|
||||
call send_back ; 1
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nx'dr : $AR1
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call send_back ; 1
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lri $AR1, #16
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lri $WR1, #4
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call send_back ; 1
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nx'dr : $AR1
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call send_back ; 1
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nx'dr : $AR1
|
||||
call send_back ; 1
|
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nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
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|
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lri $AR1, #16
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lri $WR1, #5
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||||
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
|
||||
lri $AR1, #16
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lri $WR1, #6
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|
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call send_back ; 1
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nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
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||||
call send_back ; 1
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||||
|
||||
lri $AR1, #16
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lri $WR1, #7
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||||
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
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||||
call send_back ; 1
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||||
|
||||
lri $AR1, #16
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||||
lri $WR1, #8
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||||
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
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||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
|
||||
lri $WR1, #0xFFFF
|
||||
|
||||
; We're done, DO NOT DELETE THIS LINE
|
||||
jmp end_of_test
|
||||
; This test checks the effect of the index looping registers (R8-R11)
|
||||
incdir "tests"
|
||||
include "dsp_base.inc"
|
||||
|
||||
; Tests done using AR1 = 0x0010, IX1 = 0. WR1 (wrap 1) means WR1.
|
||||
; WR1 = 0
|
||||
; 10, 10, 10, 10,
|
||||
; WR1 = 1
|
||||
; 10, 11, 10, 11,
|
||||
; WR1 = 2
|
||||
; 10, 12, 11, 13, 12, 11, 13, 12, 11, 13, 12, 11
|
||||
; WR1 = 3
|
||||
; 10, 13, 12, 11, 10, 13, 12...
|
||||
; WR1 = 4
|
||||
; 10, 14, 13, 17, 16, 15, 14, 13, 17, 16, 15, 14, 13, ...
|
||||
; WR1 = 5
|
||||
; 10, 15, 14, 13, 12, 17, 16, 15, 14, 13, 12, 17,
|
||||
; WR1 = 6
|
||||
; 10, 16, 15, 14, 13, 12, 11, 17, 16, 15, 14, 13
|
||||
; WR1 = 7
|
||||
; 10, 17, 16, 15, .. normal
|
||||
; WR1 = 8
|
||||
; 10, 18, 17, 1f, 1e, 1d, 1c, 1b, 1a, 19, 18, 17, 1f, 1e, .....
|
||||
|
||||
|
||||
; I really don't know how the above could possibly be efficiently implemented in hardware.
|
||||
; And thus it's tricky to implement in software too :p
|
||||
|
||||
; test using indexing register 1 - 0 is used in send_back
|
||||
lri $AR1, #16
|
||||
lri $IX1, #32
|
||||
lri $WR1, #0
|
||||
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #2
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #3
|
||||
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #4
|
||||
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #5
|
||||
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #6
|
||||
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #7
|
||||
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #8
|
||||
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
nx'dr : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
|
||||
lri $WR1, #0xFFFF
|
||||
|
||||
; We're done, DO NOT DELETE THIS LINE
|
||||
jmp end_of_test
|
||||
|
||||
@ -1,275 +1,275 @@
|
||||
; This is the trojan program we send to the DSP from DSPSpy to figure it out.
|
||||
REGS_BASE: equ 0x0f80
|
||||
MEM_HI: equ 0x0f7E
|
||||
MEM_LO: equ 0x0f7F
|
||||
|
||||
|
||||
; Interrupt vectors 8 vectors, 2 opcodes each
|
||||
jmp irq0
|
||||
jmp irq1
|
||||
jmp irq2
|
||||
jmp irq3
|
||||
jmp irq4
|
||||
jmp irq5
|
||||
jmp irq6
|
||||
jmp irq7
|
||||
|
||||
; Main code (and normal entrypoint) at 0x10
|
||||
sbset #0x02
|
||||
sbset #0x03
|
||||
sbclr #0x04
|
||||
sbset #0x05
|
||||
sbset #0x06
|
||||
|
||||
s16
|
||||
lri $CR, #0x00ff
|
||||
|
||||
clr $acc1
|
||||
clr $acc0
|
||||
|
||||
; get address of memory dump and copy it to DRAM
|
||||
call 0x807e
|
||||
si @DMBH, #0x8888
|
||||
si @DMBL, #0xdead
|
||||
si @DIRQ, #0x0001
|
||||
|
||||
call 0x8078
|
||||
andi $ac0.m, #0x7fff
|
||||
lrs $ac1.m, @CMBL
|
||||
|
||||
sr @MEM_HI, $ac0.m
|
||||
sr @MEM_LO, $ac1.m
|
||||
|
||||
lri $ax0.l, #0
|
||||
lri $ax1.l, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
|
||||
lri $ax0.h, #0x2000
|
||||
lr $ac0.l, @MEM_HI
|
||||
lr $ac0.m, @MEM_LO
|
||||
call do_dma
|
||||
|
||||
|
||||
; get address of registers and DMA them to ram
|
||||
call 0x807e
|
||||
si @DMBH, #0x8888
|
||||
si @DMBL, #0xbeef
|
||||
si @DIRQ, #0x0001
|
||||
|
||||
call 0x8078
|
||||
andi $ac0.m, #0x7fff
|
||||
lrs $ac1.m, @CMBL
|
||||
|
||||
sr @MEM_HI, $ac0.m
|
||||
sr @MEM_LO, $ac1.m
|
||||
|
||||
lri $ax0.l, #REGS_BASE
|
||||
lri $ax1.l, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
|
||||
lri $ax0.h, #0x80
|
||||
lr $ac0.l, @MEM_HI
|
||||
lr $ac0.m, @MEM_LO
|
||||
call do_dma
|
||||
|
||||
; Read in all the registers from RAM
|
||||
lri $ar0, #REGS_BASE+1
|
||||
lrri $ar1, @$ar0
|
||||
lrri $ar2, @$ar0
|
||||
lrri $ar3, @$ar0
|
||||
lrri $ix0, @$ar0
|
||||
lrri $ix1, @$ar0
|
||||
lrri $ix2, @$ar0
|
||||
lrri $ix3, @$ar0
|
||||
lrri $wr0, @$ar0
|
||||
lrri $wr1, @$ar0
|
||||
lrri $wr2, @$ar0
|
||||
lrri $wr3, @$ar0
|
||||
lrri $st0, @$ar0
|
||||
lrri $st1, @$ar0
|
||||
lrri $st2, @$ar0
|
||||
lrri $st3, @$ar0
|
||||
lrri $ac0.h, @$ar0
|
||||
lrri $ac1.h, @$ar0
|
||||
lrri $cr, @$ar0
|
||||
lrri $sr, @$ar0
|
||||
lrri $prod.l, @$ar0
|
||||
lrri $prod.m1, @$ar0
|
||||
lrri $prod.h, @$ar0
|
||||
lrri $prod.m2, @$ar0
|
||||
lrri $ax0.l, @$ar0
|
||||
lrri $ax1.l, @$ar0
|
||||
lrri $ax0.h, @$ar0
|
||||
lrri $ax1.h, @$ar0
|
||||
lrri $ac0.l, @$ar0
|
||||
lrri $ac1.l, @$ar0
|
||||
lrri $ac0.m, @$ar0
|
||||
lrri $ac1.m, @$ar0
|
||||
lr $ar0, @REGS_BASE
|
||||
|
||||
jmp start_of_test
|
||||
|
||||
; This is where we jump when we're done testing, see above.
|
||||
; We just fall into a loop, playing dead until someone resets the DSP.
|
||||
end_of_test:
|
||||
jmp end_of_test
|
||||
|
||||
; Utility function to do DMA.
|
||||
do_dma:
|
||||
sr @DSMAH, $ac0.l
|
||||
sr @DSMAL, $ac0.m
|
||||
sr @DSPA, $ax0.l
|
||||
sr @DSCR, $ax1.l
|
||||
sr @DSBL, $ax0.h ; This kicks off the DMA.
|
||||
call 0x863d ; Wait for DMA to complete by watching a bit in DSCR.
|
||||
ret
|
||||
|
||||
; IRQ handlers. Just send back exception# and die
|
||||
irq0:
|
||||
lri $ac0.m, #0x0000
|
||||
jmp irq
|
||||
irq1:
|
||||
lri $ac0.m, #0x0001
|
||||
jmp irq
|
||||
irq2:
|
||||
lri $ac0.m, #0x0002
|
||||
jmp irq
|
||||
irq3:
|
||||
lri $ac0.m, #0x0003
|
||||
jmp irq
|
||||
irq4:
|
||||
lri $ac0.m, #0x0004
|
||||
jmp irq
|
||||
irq5:
|
||||
lri $ac0.m, #0x0005
|
||||
jmp irq
|
||||
irq6:
|
||||
lri $ac0.m, #0x0006
|
||||
jmp irq
|
||||
irq7:
|
||||
lri $ac0.m, #0x0007
|
||||
|
||||
irq:
|
||||
lrs $ac1.m, @DMBH
|
||||
andcf $ac1.m, #0x8000
|
||||
jlz irq
|
||||
si @DMBH, #0x8bad
|
||||
;sr @DMBL, $wr3 ; ???
|
||||
sr @DMBL, $ac0.m ; Exception number
|
||||
si @DIRQ, #0x0001
|
||||
halt ; Through some magic this allows us to properly ack the exception in dspspy
|
||||
;rti ; allow dumping of ucodes which cause exceptions...probably not safe at all
|
||||
|
||||
; DMA:s the current state of the registers back to the PowerPC. To do this,
|
||||
; it must write the contents of all regs to DRAM.
|
||||
; Unfortunately, this loop uses ar0 so it's best to use AR1 and friends for testing
|
||||
; when messing with indexing.
|
||||
send_back:
|
||||
; make state safe.
|
||||
set16
|
||||
; store registers to reg table
|
||||
sr @REGS_BASE, $ar0
|
||||
lri $ar0, #(REGS_BASE + 1)
|
||||
srri @$ar0, $ar1
|
||||
srri @$ar0, $ar2
|
||||
srri @$ar0, $ar3
|
||||
srri @$ar0, $ix0
|
||||
srri @$ar0, $ix1
|
||||
srri @$ar0, $ix2
|
||||
srri @$ar0, $ix3
|
||||
srri @$ar0, $wr0
|
||||
srri @$ar0, $wr1
|
||||
srri @$ar0, $wr2
|
||||
srri @$ar0, $wr3
|
||||
srri @$ar0, $st0
|
||||
srri @$ar0, $st1
|
||||
srri @$ar0, $st2
|
||||
srri @$ar0, $st3
|
||||
srri @$ar0, $ac0.h
|
||||
srri @$ar0, $ac1.h
|
||||
srri @$ar0, $cr
|
||||
srri @$ar0, $sr
|
||||
srri @$ar0, $prod.l
|
||||
srri @$ar0, $prod.m1
|
||||
srri @$ar0, $prod.h
|
||||
srri @$ar0, $prod.m2
|
||||
srri @$ar0, $ax0.l
|
||||
srri @$ar0, $ax1.l
|
||||
srri @$ar0, $ax0.h
|
||||
srri @$ar0, $ax1.h
|
||||
srri @$ar0, $ac0.l
|
||||
srri @$ar0, $ac1.l
|
||||
srri @$ar0, $ac0.m
|
||||
srri @$ar0, $ac1.m
|
||||
|
||||
; Regs are stored. Prepare DMA.
|
||||
lri $ax0.l, #0x0000
|
||||
lri $ax1.l, #1 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
|
||||
lri $ax0.h, #0x200
|
||||
lr $ac0.l, @MEM_HI
|
||||
lr $ac0.m, @MEM_LO
|
||||
|
||||
; Now, why are we looping here?
|
||||
lri $ar1, #8+8
|
||||
bloop $ar1, dma_copy
|
||||
call do_dma
|
||||
addi $ac0.m, #0x200
|
||||
mrr $ac1.m, $ax0.l
|
||||
addi $ac1.m, #0x100
|
||||
dma_copy:
|
||||
mrr $ax0.l, $ac1.m
|
||||
|
||||
; Wait for the CPU to send us a mail.
|
||||
call 0x807e
|
||||
si @DMBH, #0x8888
|
||||
si @DMBL, #0xfeeb
|
||||
si @DIRQ, #0x0001
|
||||
|
||||
; wait for the CPU to recieve our response before we execute the next op
|
||||
call 0x8078
|
||||
andi $ac0.m, #0x7fff
|
||||
lrs $ac1.m, @CMBL
|
||||
|
||||
; Restore all regs again so we're ready to execute another op.
|
||||
lri $ar0, #REGS_BASE+1
|
||||
lrri $ar1, @$ar0
|
||||
lrri $ar2, @$ar0
|
||||
lrri $ar3, @$ar0
|
||||
lrri $ix0, @$ar0
|
||||
lrri $ix1, @$ar0
|
||||
lrri $ix2, @$ar0
|
||||
lrri $ix3, @$ar0
|
||||
lrri $wr0, @$ar0
|
||||
lrri $wr1, @$ar0
|
||||
lrri $wr2, @$ar0
|
||||
lrri $wr3, @$ar0
|
||||
lrri $st0, @$ar0
|
||||
lrri $st1, @$ar0
|
||||
lrri $st2, @$ar0
|
||||
lrri $st3, @$ar0
|
||||
lrri $ac0.h, @$ar0
|
||||
lrri $ac1.h, @$ar0
|
||||
lrri $cr, @$ar0
|
||||
lrri $sr, @$ar0
|
||||
lrri $prod.l, @$ar0
|
||||
lrri $prod.m1, @$ar0
|
||||
lrri $prod.h, @$ar0
|
||||
lrri $prod.m2, @$ar0
|
||||
lrri $ax0.l, @$ar0
|
||||
lrri $ax1.l, @$ar0
|
||||
lrri $ax0.h, @$ar0
|
||||
lrri $ax1.h, @$ar0
|
||||
lrri $ac0.l, @$ar0
|
||||
lrri $ac1.l, @$ar0
|
||||
lrri $ac0.m, @$ar0
|
||||
lrri $ac1.m, @$ar0
|
||||
lr $ar0, @REGS_BASE
|
||||
|
||||
ret ; from send_back
|
||||
|
||||
; If you are in set40 mode, use this instead of send_back if you want to stay
|
||||
; in set40 mode.
|
||||
send_back_40:
|
||||
set16
|
||||
call send_back
|
||||
set40
|
||||
ret
|
||||
|
||||
; Obviously this must be included directly before your test code
|
||||
start_of_test:
|
||||
; This is the trojan program we send to the DSP from DSPSpy to figure it out.
|
||||
REGS_BASE: equ 0x0f80
|
||||
MEM_HI: equ 0x0f7E
|
||||
MEM_LO: equ 0x0f7F
|
||||
|
||||
|
||||
; Interrupt vectors 8 vectors, 2 opcodes each
|
||||
jmp irq0
|
||||
jmp irq1
|
||||
jmp irq2
|
||||
jmp irq3
|
||||
jmp irq4
|
||||
jmp irq5
|
||||
jmp irq6
|
||||
jmp irq7
|
||||
|
||||
; Main code (and normal entrypoint) at 0x10
|
||||
sbset #0x02
|
||||
sbset #0x03
|
||||
sbclr #0x04
|
||||
sbset #0x05
|
||||
sbset #0x06
|
||||
|
||||
s16
|
||||
lri $CR, #0x00ff
|
||||
|
||||
clr $acc1
|
||||
clr $acc0
|
||||
|
||||
; get address of memory dump and copy it to DRAM
|
||||
call 0x807e
|
||||
si @DMBH, #0x8888
|
||||
si @DMBL, #0xdead
|
||||
si @DIRQ, #0x0001
|
||||
|
||||
call 0x8078
|
||||
andi $ac0.m, #0x7fff
|
||||
lrs $ac1.m, @CMBL
|
||||
|
||||
sr @MEM_HI, $ac0.m
|
||||
sr @MEM_LO, $ac1.m
|
||||
|
||||
lri $ax0.l, #0
|
||||
lri $ax1.l, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
|
||||
lri $ax0.h, #0x2000
|
||||
lr $ac0.l, @MEM_HI
|
||||
lr $ac0.m, @MEM_LO
|
||||
call do_dma
|
||||
|
||||
|
||||
; get address of registers and DMA them to ram
|
||||
call 0x807e
|
||||
si @DMBH, #0x8888
|
||||
si @DMBL, #0xbeef
|
||||
si @DIRQ, #0x0001
|
||||
|
||||
call 0x8078
|
||||
andi $ac0.m, #0x7fff
|
||||
lrs $ac1.m, @CMBL
|
||||
|
||||
sr @MEM_HI, $ac0.m
|
||||
sr @MEM_LO, $ac1.m
|
||||
|
||||
lri $ax0.l, #REGS_BASE
|
||||
lri $ax1.l, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
|
||||
lri $ax0.h, #0x80
|
||||
lr $ac0.l, @MEM_HI
|
||||
lr $ac0.m, @MEM_LO
|
||||
call do_dma
|
||||
|
||||
; Read in all the registers from RAM
|
||||
lri $ar0, #REGS_BASE+1
|
||||
lrri $ar1, @$ar0
|
||||
lrri $ar2, @$ar0
|
||||
lrri $ar3, @$ar0
|
||||
lrri $ix0, @$ar0
|
||||
lrri $ix1, @$ar0
|
||||
lrri $ix2, @$ar0
|
||||
lrri $ix3, @$ar0
|
||||
lrri $wr0, @$ar0
|
||||
lrri $wr1, @$ar0
|
||||
lrri $wr2, @$ar0
|
||||
lrri $wr3, @$ar0
|
||||
lrri $st0, @$ar0
|
||||
lrri $st1, @$ar0
|
||||
lrri $st2, @$ar0
|
||||
lrri $st3, @$ar0
|
||||
lrri $ac0.h, @$ar0
|
||||
lrri $ac1.h, @$ar0
|
||||
lrri $cr, @$ar0
|
||||
lrri $sr, @$ar0
|
||||
lrri $prod.l, @$ar0
|
||||
lrri $prod.m1, @$ar0
|
||||
lrri $prod.h, @$ar0
|
||||
lrri $prod.m2, @$ar0
|
||||
lrri $ax0.l, @$ar0
|
||||
lrri $ax1.l, @$ar0
|
||||
lrri $ax0.h, @$ar0
|
||||
lrri $ax1.h, @$ar0
|
||||
lrri $ac0.l, @$ar0
|
||||
lrri $ac1.l, @$ar0
|
||||
lrri $ac0.m, @$ar0
|
||||
lrri $ac1.m, @$ar0
|
||||
lr $ar0, @REGS_BASE
|
||||
|
||||
jmp start_of_test
|
||||
|
||||
; This is where we jump when we're done testing, see above.
|
||||
; We just fall into a loop, playing dead until someone resets the DSP.
|
||||
end_of_test:
|
||||
jmp end_of_test
|
||||
|
||||
; Utility function to do DMA.
|
||||
do_dma:
|
||||
sr @DSMAH, $ac0.l
|
||||
sr @DSMAL, $ac0.m
|
||||
sr @DSPA, $ax0.l
|
||||
sr @DSCR, $ax1.l
|
||||
sr @DSBL, $ax0.h ; This kicks off the DMA.
|
||||
call 0x863d ; Wait for DMA to complete by watching a bit in DSCR.
|
||||
ret
|
||||
|
||||
; IRQ handlers. Just send back exception# and die
|
||||
irq0:
|
||||
lri $ac0.m, #0x0000
|
||||
jmp irq
|
||||
irq1:
|
||||
lri $ac0.m, #0x0001
|
||||
jmp irq
|
||||
irq2:
|
||||
lri $ac0.m, #0x0002
|
||||
jmp irq
|
||||
irq3:
|
||||
lri $ac0.m, #0x0003
|
||||
jmp irq
|
||||
irq4:
|
||||
lri $ac0.m, #0x0004
|
||||
jmp irq
|
||||
irq5:
|
||||
lri $ac0.m, #0x0005
|
||||
jmp irq
|
||||
irq6:
|
||||
lri $ac0.m, #0x0006
|
||||
jmp irq
|
||||
irq7:
|
||||
lri $ac0.m, #0x0007
|
||||
|
||||
irq:
|
||||
lrs $ac1.m, @DMBH
|
||||
andcf $ac1.m, #0x8000
|
||||
jlz irq
|
||||
si @DMBH, #0x8bad
|
||||
;sr @DMBL, $wr3 ; ???
|
||||
sr @DMBL, $ac0.m ; Exception number
|
||||
si @DIRQ, #0x0001
|
||||
halt ; Through some magic this allows us to properly ack the exception in dspspy
|
||||
;rti ; allow dumping of ucodes which cause exceptions...probably not safe at all
|
||||
|
||||
; DMA:s the current state of the registers back to the PowerPC. To do this,
|
||||
; it must write the contents of all regs to DRAM.
|
||||
; Unfortunately, this loop uses ar0 so it's best to use AR1 and friends for testing
|
||||
; when messing with indexing.
|
||||
send_back:
|
||||
; make state safe.
|
||||
set16
|
||||
; store registers to reg table
|
||||
sr @REGS_BASE, $ar0
|
||||
lri $ar0, #(REGS_BASE + 1)
|
||||
srri @$ar0, $ar1
|
||||
srri @$ar0, $ar2
|
||||
srri @$ar0, $ar3
|
||||
srri @$ar0, $ix0
|
||||
srri @$ar0, $ix1
|
||||
srri @$ar0, $ix2
|
||||
srri @$ar0, $ix3
|
||||
srri @$ar0, $wr0
|
||||
srri @$ar0, $wr1
|
||||
srri @$ar0, $wr2
|
||||
srri @$ar0, $wr3
|
||||
srri @$ar0, $st0
|
||||
srri @$ar0, $st1
|
||||
srri @$ar0, $st2
|
||||
srri @$ar0, $st3
|
||||
srri @$ar0, $ac0.h
|
||||
srri @$ar0, $ac1.h
|
||||
srri @$ar0, $cr
|
||||
srri @$ar0, $sr
|
||||
srri @$ar0, $prod.l
|
||||
srri @$ar0, $prod.m1
|
||||
srri @$ar0, $prod.h
|
||||
srri @$ar0, $prod.m2
|
||||
srri @$ar0, $ax0.l
|
||||
srri @$ar0, $ax1.l
|
||||
srri @$ar0, $ax0.h
|
||||
srri @$ar0, $ax1.h
|
||||
srri @$ar0, $ac0.l
|
||||
srri @$ar0, $ac1.l
|
||||
srri @$ar0, $ac0.m
|
||||
srri @$ar0, $ac1.m
|
||||
|
||||
; Regs are stored. Prepare DMA.
|
||||
lri $ax0.l, #0x0000
|
||||
lri $ax1.l, #1 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
|
||||
lri $ax0.h, #0x200
|
||||
lr $ac0.l, @MEM_HI
|
||||
lr $ac0.m, @MEM_LO
|
||||
|
||||
; Now, why are we looping here?
|
||||
lri $ar1, #8+8
|
||||
bloop $ar1, dma_copy
|
||||
call do_dma
|
||||
addi $ac0.m, #0x200
|
||||
mrr $ac1.m, $ax0.l
|
||||
addi $ac1.m, #0x100
|
||||
dma_copy:
|
||||
mrr $ax0.l, $ac1.m
|
||||
|
||||
; Wait for the CPU to send us a mail.
|
||||
call 0x807e
|
||||
si @DMBH, #0x8888
|
||||
si @DMBL, #0xfeeb
|
||||
si @DIRQ, #0x0001
|
||||
|
||||
; wait for the CPU to recieve our response before we execute the next op
|
||||
call 0x8078
|
||||
andi $ac0.m, #0x7fff
|
||||
lrs $ac1.m, @CMBL
|
||||
|
||||
; Restore all regs again so we're ready to execute another op.
|
||||
lri $ar0, #REGS_BASE+1
|
||||
lrri $ar1, @$ar0
|
||||
lrri $ar2, @$ar0
|
||||
lrri $ar3, @$ar0
|
||||
lrri $ix0, @$ar0
|
||||
lrri $ix1, @$ar0
|
||||
lrri $ix2, @$ar0
|
||||
lrri $ix3, @$ar0
|
||||
lrri $wr0, @$ar0
|
||||
lrri $wr1, @$ar0
|
||||
lrri $wr2, @$ar0
|
||||
lrri $wr3, @$ar0
|
||||
lrri $st0, @$ar0
|
||||
lrri $st1, @$ar0
|
||||
lrri $st2, @$ar0
|
||||
lrri $st3, @$ar0
|
||||
lrri $ac0.h, @$ar0
|
||||
lrri $ac1.h, @$ar0
|
||||
lrri $cr, @$ar0
|
||||
lrri $sr, @$ar0
|
||||
lrri $prod.l, @$ar0
|
||||
lrri $prod.m1, @$ar0
|
||||
lrri $prod.h, @$ar0
|
||||
lrri $prod.m2, @$ar0
|
||||
lrri $ax0.l, @$ar0
|
||||
lrri $ax1.l, @$ar0
|
||||
lrri $ax0.h, @$ar0
|
||||
lrri $ax1.h, @$ar0
|
||||
lrri $ac0.l, @$ar0
|
||||
lrri $ac1.l, @$ar0
|
||||
lrri $ac0.m, @$ar0
|
||||
lrri $ac1.m, @$ar0
|
||||
lr $ar0, @REGS_BASE
|
||||
|
||||
ret ; from send_back
|
||||
|
||||
; If you are in set40 mode, use this instead of send_back if you want to stay
|
||||
; in set40 mode.
|
||||
send_back_40:
|
||||
set16
|
||||
call send_back
|
||||
set40
|
||||
ret
|
||||
|
||||
; Obviously this must be included directly before your test code
|
||||
start_of_test:
|
||||
|
||||
@ -1,21 +1,21 @@
|
||||
incdir "tests"
|
||||
include "dsp_base.inc"
|
||||
|
||||
; Right here we are at a specific predetermined state.
|
||||
; Ideal environment to try instructions.
|
||||
|
||||
; We can call send_back at any time to send data back to the PowerPC.
|
||||
|
||||
; Calling set40 here seemed to crash the dsp tester in strange ways
|
||||
; until I added set16 in send_back. Seems clear that it affects something important.
|
||||
|
||||
lri $AC0.M, #0x1000
|
||||
call send_back
|
||||
|
||||
set40
|
||||
lri $AC0.M, #0x1000
|
||||
set16
|
||||
call send_back
|
||||
|
||||
; We're done, DO NOT DELETE THIS LINE
|
||||
jmp end_of_test
|
||||
incdir "tests"
|
||||
include "dsp_base.inc"
|
||||
|
||||
; Right here we are at a specific predetermined state.
|
||||
; Ideal environment to try instructions.
|
||||
|
||||
; We can call send_back at any time to send data back to the PowerPC.
|
||||
|
||||
; Calling set40 here seemed to crash the dsp tester in strange ways
|
||||
; until I added set16 in send_back. Seems clear that it affects something important.
|
||||
|
||||
lri $AC0.M, #0x1000
|
||||
call send_back
|
||||
|
||||
set40
|
||||
lri $AC0.M, #0x1000
|
||||
set16
|
||||
call send_back
|
||||
|
||||
; We're done, DO NOT DELETE THIS LINE
|
||||
jmp end_of_test
|
||||
|
||||
@ -1,319 +1,319 @@
|
||||
; This test checks the effect of the index looping registers (R8-R11)
|
||||
incdir "tests"
|
||||
include "dsp_base.inc"
|
||||
|
||||
; First theories, fitting tests with nice masks in the loop registers
|
||||
; IR THEORY: if ((ar & lp) == lp) ar &= ~lp;
|
||||
; DR THEORY: if ((ar & lp) == 0) ar |= lp;
|
||||
; These were proven FALSE though by the following:
|
||||
|
||||
; Tests done using AR1 = 0x0010, IX1 = 0
|
||||
; WR1 = 0
|
||||
; 10, 11, 11, 11, 11......
|
||||
; WR1 = 1
|
||||
; 10, 11, 10, 11, 10......
|
||||
; WR1 = 2
|
||||
; 10, 11, 12, 13, 11, 12, 13, 11, 12, 13 ......
|
||||
; WR1 = 3
|
||||
; 10, 11, 12, 13, 10, 11, 12, 13, 10, 11, 12, 13.......
|
||||
; WR1 = 4
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 13, 14, 15, 16, 17, 13, 14, 15 ......
|
||||
; WR1 = 5
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 12, 13, 14, 15 ...
|
||||
; WR1 = 6
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 11, 12, 13, 14...
|
||||
; WR1 = 7
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 10, 11, ....
|
||||
; WR1 = 8
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f, 17, 18, 19, 1a, 1b.....
|
||||
|
||||
|
||||
; I really don't know how the above could possibly be efficiently implemented in hardware.
|
||||
; And thus it's tricky to implement in software too :p
|
||||
|
||||
; test using indexing register 1 - 0 is used in send_back
|
||||
lri $AR1, #16
|
||||
lri $IX1, #32
|
||||
lri $WR1, #0
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #2
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #3
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #4
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #5
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #6
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #7
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #8
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
|
||||
lri $WR1, #0xFFFF
|
||||
|
||||
; We're done, DO NOT DELETE THIS LINE
|
||||
jmp end_of_test
|
||||
; This test checks the effect of the index looping registers (R8-R11)
|
||||
incdir "tests"
|
||||
include "dsp_base.inc"
|
||||
|
||||
; First theories, fitting tests with nice masks in the loop registers
|
||||
; IR THEORY: if ((ar & lp) == lp) ar &= ~lp;
|
||||
; DR THEORY: if ((ar & lp) == 0) ar |= lp;
|
||||
; These were proven FALSE though by the following:
|
||||
|
||||
; Tests done using AR1 = 0x0010, IX1 = 0
|
||||
; WR1 = 0
|
||||
; 10, 11, 11, 11, 11......
|
||||
; WR1 = 1
|
||||
; 10, 11, 10, 11, 10......
|
||||
; WR1 = 2
|
||||
; 10, 11, 12, 13, 11, 12, 13, 11, 12, 13 ......
|
||||
; WR1 = 3
|
||||
; 10, 11, 12, 13, 10, 11, 12, 13, 10, 11, 12, 13.......
|
||||
; WR1 = 4
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 13, 14, 15, 16, 17, 13, 14, 15 ......
|
||||
; WR1 = 5
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 12, 13, 14, 15 ...
|
||||
; WR1 = 6
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 11, 12, 13, 14...
|
||||
; WR1 = 7
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 10, 11, ....
|
||||
; WR1 = 8
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f, 17, 18, 19, 1a, 1b.....
|
||||
|
||||
|
||||
; I really don't know how the above could possibly be efficiently implemented in hardware.
|
||||
; And thus it's tricky to implement in software too :p
|
||||
|
||||
; test using indexing register 1 - 0 is used in send_back
|
||||
lri $AR1, #16
|
||||
lri $IX1, #32
|
||||
lri $WR1, #0
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #2
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #3
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #4
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #5
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #6
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #7
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR1, #16
|
||||
lri $WR1, #8
|
||||
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
nx'ir : $AR1
|
||||
call send_back ; 1
|
||||
|
||||
|
||||
lri $WR1, #0xFFFF
|
||||
|
||||
; We're done, DO NOT DELETE THIS LINE
|
||||
jmp end_of_test
|
||||
|
||||
@ -1,247 +1,247 @@
|
||||
; This test verifies LD
|
||||
incdir "tests"
|
||||
include "dsp_base.inc"
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x77
|
||||
lri $AX1.L, #0x22
|
||||
|
||||
nx'ld : $AX0.L, $AX1.L, @$AR3
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x23
|
||||
lri $AX1.L, #0x64
|
||||
|
||||
nx'ld : $AX0.L, $AX1.L, @$AR2
|
||||
call send_back ; 2
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x43
|
||||
lri $AX1.L, #0x53
|
||||
|
||||
nx'ld : $AX0.L, $AX1.L, @$AR1
|
||||
call send_back ; 3
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0xd3
|
||||
lri $AX1.L, #0x13
|
||||
|
||||
nx'ld : $AX0.L, $AX1.L, @$AR0
|
||||
call send_back ; 4
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x77
|
||||
lri $AX1.L, #0x22
|
||||
|
||||
|
||||
nx'ld : $AX1.L, $AX1.H, @$AR3
|
||||
call send_back ; 5
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x23
|
||||
lri $AX1.L, #0x64
|
||||
|
||||
nx'ld : $AX1.L, $AX1.H, @$AR2
|
||||
call send_back ; 6
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x43
|
||||
lri $AX1.L, #0x53
|
||||
|
||||
nx'ld : $AX1.L, $AX1.H, @$AR1
|
||||
call send_back ; 7
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0xd3
|
||||
lri $AX1.L, #0x13
|
||||
|
||||
nx'ld : $AX1.L, $AX1.H, @$AR0
|
||||
call send_back ; 8
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x77
|
||||
lri $AX1.L, #0x22
|
||||
|
||||
nx'ldn : $AX0.L, $AX1.L, @$AR3
|
||||
call send_back ; 9
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x23
|
||||
lri $AX1.L, #0x64
|
||||
|
||||
nx'ldn : $AX0.L, $AX1.L, @$AR2
|
||||
call send_back ; 10
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x43
|
||||
lri $AX1.L, #0x53
|
||||
|
||||
nx'ldn : $AX0.L, $AX1.L, @$AR1
|
||||
call send_back ; 11
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0xd3
|
||||
lri $AX1.L, #0x13
|
||||
|
||||
nx'ldn : $AX0.L, $AX1.L, @$AR0
|
||||
call send_back ; 12
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x77
|
||||
lri $AX1.L, #0x22
|
||||
|
||||
nx'ldm : $AX0.L, $AX1.L, @$AR3
|
||||
call send_back ; 13
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x23
|
||||
lri $AX1.L, #0x64
|
||||
|
||||
nx'ldm : $AX0.L, $AX1.L, @$AR2
|
||||
call send_back ; 14
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x43
|
||||
lri $AX1.L, #0x53
|
||||
|
||||
nx'ldm : $AX0.L, $AX1.L, @$AR1
|
||||
call send_back ; 15
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0xd3
|
||||
lri $AX1.L, #0x13
|
||||
|
||||
nx'ldm : $AX0.L, $AX1.L, @$AR0
|
||||
call send_back ; 16
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x77
|
||||
lri $AX1.L, #0x22
|
||||
|
||||
nx'ldnm : $AX0.L, $AX1.L, @$AR3
|
||||
call send_back ; 17
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x23
|
||||
lri $AX1.L, #0x64
|
||||
|
||||
nx'ldnm : $AX0.L, $AX1.L, @$AR2
|
||||
call send_back ; 18
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x43
|
||||
lri $AX1.L, #0x53
|
||||
|
||||
nx'ldnm : $AX0.L, $AX1.L, @$AR1
|
||||
call send_back ; 19
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0xd3
|
||||
lri $AX1.L, #0x13
|
||||
|
||||
nx'ldnm : $AX0.L, $AX1.L, @$AR0
|
||||
call send_back ; 20
|
||||
|
||||
|
||||
|
||||
; This test verifies LD
|
||||
incdir "tests"
|
||||
include "dsp_base.inc"
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x77
|
||||
lri $AX1.L, #0x22
|
||||
|
||||
nx'ld : $AX0.L, $AX1.L, @$AR3
|
||||
call send_back ; 1
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x23
|
||||
lri $AX1.L, #0x64
|
||||
|
||||
nx'ld : $AX0.L, $AX1.L, @$AR2
|
||||
call send_back ; 2
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x43
|
||||
lri $AX1.L, #0x53
|
||||
|
||||
nx'ld : $AX0.L, $AX1.L, @$AR1
|
||||
call send_back ; 3
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0xd3
|
||||
lri $AX1.L, #0x13
|
||||
|
||||
nx'ld : $AX0.L, $AX1.L, @$AR0
|
||||
call send_back ; 4
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x77
|
||||
lri $AX1.L, #0x22
|
||||
|
||||
|
||||
nx'ld : $AX1.L, $AX1.H, @$AR3
|
||||
call send_back ; 5
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x23
|
||||
lri $AX1.L, #0x64
|
||||
|
||||
nx'ld : $AX1.L, $AX1.H, @$AR2
|
||||
call send_back ; 6
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x43
|
||||
lri $AX1.L, #0x53
|
||||
|
||||
nx'ld : $AX1.L, $AX1.H, @$AR1
|
||||
call send_back ; 7
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0xd3
|
||||
lri $AX1.L, #0x13
|
||||
|
||||
nx'ld : $AX1.L, $AX1.H, @$AR0
|
||||
call send_back ; 8
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x77
|
||||
lri $AX1.L, #0x22
|
||||
|
||||
nx'ldn : $AX0.L, $AX1.L, @$AR3
|
||||
call send_back ; 9
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x23
|
||||
lri $AX1.L, #0x64
|
||||
|
||||
nx'ldn : $AX0.L, $AX1.L, @$AR2
|
||||
call send_back ; 10
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x43
|
||||
lri $AX1.L, #0x53
|
||||
|
||||
nx'ldn : $AX0.L, $AX1.L, @$AR1
|
||||
call send_back ; 11
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0xd3
|
||||
lri $AX1.L, #0x13
|
||||
|
||||
nx'ldn : $AX0.L, $AX1.L, @$AR0
|
||||
call send_back ; 12
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x77
|
||||
lri $AX1.L, #0x22
|
||||
|
||||
nx'ldm : $AX0.L, $AX1.L, @$AR3
|
||||
call send_back ; 13
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x23
|
||||
lri $AX1.L, #0x64
|
||||
|
||||
nx'ldm : $AX0.L, $AX1.L, @$AR2
|
||||
call send_back ; 14
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x43
|
||||
lri $AX1.L, #0x53
|
||||
|
||||
nx'ldm : $AX0.L, $AX1.L, @$AR1
|
||||
call send_back ; 15
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0xd3
|
||||
lri $AX1.L, #0x13
|
||||
|
||||
nx'ldm : $AX0.L, $AX1.L, @$AR0
|
||||
call send_back ; 16
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x77
|
||||
lri $AX1.L, #0x22
|
||||
|
||||
nx'ldnm : $AX0.L, $AX1.L, @$AR3
|
||||
call send_back ; 17
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x23
|
||||
lri $AX1.L, #0x64
|
||||
|
||||
nx'ldnm : $AX0.L, $AX1.L, @$AR2
|
||||
call send_back ; 18
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0x43
|
||||
lri $AX1.L, #0x53
|
||||
|
||||
nx'ldnm : $AX0.L, $AX1.L, @$AR1
|
||||
call send_back ; 19
|
||||
|
||||
lri $AR0, #0x001c
|
||||
lri $AR1, #0x001d
|
||||
lri $AR2, #0x001e
|
||||
lri $AR3, #0x001f
|
||||
lri $AX0.H, #0x111
|
||||
lri $AX1.H, #0x111
|
||||
lri $AX0.L, #0xd3
|
||||
lri $AX1.L, #0x13
|
||||
|
||||
nx'ldnm : $AX0.L, $AX1.L, @$AR0
|
||||
call send_back ; 20
|
||||
|
||||
|
||||
|
||||
|
||||
@ -1,250 +1,250 @@
|
||||
; This test checks the effect of SET15 on multiplications.
|
||||
incdir "tests"
|
||||
include "dsp_base.inc"
|
||||
|
||||
; Results is in capitails like this: UNSIGNED
|
||||
|
||||
CLR15
|
||||
|
||||
; Test MULXMVZ - SET15
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.H, #0x100
|
||||
MULXMVZ $AX0.L, $AX1.H, $ACC0 ; SIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
SET15
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.H, #0x100
|
||||
MULXMVZ $AX0.L, $AX1.H, $ACC0 ; UNSIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
CLR15
|
||||
|
||||
; Test MULXMV - SET15
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.H, #0x100
|
||||
MULXMV $AX0.L, $AX1.H, $ACC0 ; SIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
SET15
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.H, #0x100
|
||||
MULXMV $AX0.L, $AX1.H, $ACC0 ; UNSIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
CLR15
|
||||
|
||||
; Test MULXAC - SET15
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.H, #0x100
|
||||
MULXAC $AX0.L, $AX1.H, $ACC0 ; SIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
SET15
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.H, #0x100
|
||||
MULXAC $AX0.L, $AX1.H, $ACC0 ; UNSIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
CLR15
|
||||
|
||||
; Test MULX - SET15
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.H, #0x100
|
||||
MULX $AX0.L, $AX1.H ; SIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
SET15
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.H, #0x100
|
||||
MULX $AX0.L, $AX1.H ; UNSIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
CLR15
|
||||
|
||||
|
||||
; Test MADDX - SET15
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.L, #0x100
|
||||
MADDX $AX0.L, $AX1.L ; SIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
SET15
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.L, #0x100
|
||||
MADDX $AX0.L, $AX1.L ; SIGNED (!)
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
CLR15
|
||||
|
||||
|
||||
; Test MULC - SET15
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
LRI $AC0.M, #0xFFFF
|
||||
LRI $AX0.H, #0x100
|
||||
MULC $AC0.M, $AX0.H ; SIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
SET15
|
||||
LRI $AC0.M, #0xFFFF
|
||||
LRI $AX0.H, #0x100
|
||||
MULC $AC0.M, $AX0.H ; SIGNED (!)
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
CLR15
|
||||
|
||||
|
||||
; Test MULCAC - SET15
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
LRI $AC0.M, #0xFFFF
|
||||
LRI $AX0.H, #0x100
|
||||
MULCAC $AC0.M, $AX0.H, $ACC0 ; SIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
SET15
|
||||
LRI $AC0.M, #0xFFFF
|
||||
LRI $AX0.H, #0x100
|
||||
MULCAC $AC0.M, $AX0.H, $ACC0 ; SIGNED (!)
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
CLR15
|
||||
|
||||
|
||||
; Test MUL - SET15
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX0.H, #0x100
|
||||
MUL $AX0.L, $AX0.H ; SIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
|
||||
CLR $ACC0
|
||||
SET15
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX0.H, #0x100
|
||||
MUL $AX0.L, $AX0.H ; SIGNED (!)
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
CLR15
|
||||
|
||||
|
||||
; Test MULAC - SET15
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX0.H, #0x100
|
||||
MULAC $AX0.L, $AX0.H, $ACC0 ; SIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
|
||||
CLR $ACC0
|
||||
SET15
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX0.H, #0x100
|
||||
MULAC $AX0.L, $AX0.H, $ACC0 ; SIGNED (!)
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
CLR15
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
; We're done, DO NOT DELETE THIS LINE
|
||||
jmp end_of_test
|
||||
|
||||
; test accelerator
|
||||
|
||||
; TODO: DSPSpy puts a 16-bit ramp at 0x10000000
|
||||
LRIS $AC1.M, #0x0a ; 16-bit PCM audio
|
||||
;SRS @SampleFormat, $AC1.M
|
||||
; Start accelerator position
|
||||
LRI $AC1.M, #0x0100
|
||||
SRS @ACCAH, $AC1.M
|
||||
LRI $AC1.M, #0x1000
|
||||
SRS @ACCAH, $AC1.M
|
||||
; Current accelerator position
|
||||
LRI $AC1.M, #0x0100
|
||||
SRS @ACCAH, $AC1.M
|
||||
LRI $AC1.M, #0x1000
|
||||
SRS @ACCAH, $AC1.M
|
||||
; End accelerator position
|
||||
LRI $AC1.M, #0x0100
|
||||
SRS @ACCAH, $AC1.M
|
||||
LRI $AC1.M, #0x2000
|
||||
SRS @ACCAH, $AC1.M
|
||||
|
||||
; Now to the interesting parameter - gain.
|
||||
LRI $AC1.M, #0xFFFF
|
||||
SRS @GAIN, $AC1.M
|
||||
|
||||
; Let's now load a sample through the accelerator.
|
||||
LRS $AC1.M, @ARAM
|
||||
call send_back
|
||||
|
||||
jmp end_of_test
|
||||
|
||||
; test addpaxz
|
||||
call send_back
|
||||
|
||||
clrp
|
||||
lri $AX0.L, #0x1111
|
||||
lri $AX0.H, #0x2222
|
||||
call send_back
|
||||
|
||||
clrp
|
||||
addpaxz $ACC0, $AX0.H
|
||||
|
||||
call send_back
|
||||
|
||||
clrp
|
||||
set40
|
||||
addpaxz $ACC0, $AX0.H
|
||||
set16
|
||||
|
||||
call send_back
|
||||
|
||||
clrp
|
||||
set15
|
||||
addpaxz $ACC0, $AX0.H
|
||||
clr15
|
||||
|
||||
call send_back
|
||||
|
||||
|
||||
jmp end_of_test
|
||||
|
||||
; This test checks the effect of SET15 on multiplications.
|
||||
incdir "tests"
|
||||
include "dsp_base.inc"
|
||||
|
||||
; Results is in capitails like this: UNSIGNED
|
||||
|
||||
CLR15
|
||||
|
||||
; Test MULXMVZ - SET15
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.H, #0x100
|
||||
MULXMVZ $AX0.L, $AX1.H, $ACC0 ; SIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
SET15
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.H, #0x100
|
||||
MULXMVZ $AX0.L, $AX1.H, $ACC0 ; UNSIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
CLR15
|
||||
|
||||
; Test MULXMV - SET15
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.H, #0x100
|
||||
MULXMV $AX0.L, $AX1.H, $ACC0 ; SIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
SET15
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.H, #0x100
|
||||
MULXMV $AX0.L, $AX1.H, $ACC0 ; UNSIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
CLR15
|
||||
|
||||
; Test MULXAC - SET15
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.H, #0x100
|
||||
MULXAC $AX0.L, $AX1.H, $ACC0 ; SIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
SET15
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.H, #0x100
|
||||
MULXAC $AX0.L, $AX1.H, $ACC0 ; UNSIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
CLR15
|
||||
|
||||
; Test MULX - SET15
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.H, #0x100
|
||||
MULX $AX0.L, $AX1.H ; SIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
SET15
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.H, #0x100
|
||||
MULX $AX0.L, $AX1.H ; UNSIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
CLR15
|
||||
|
||||
|
||||
; Test MADDX - SET15
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.L, #0x100
|
||||
MADDX $AX0.L, $AX1.L ; SIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
SET15
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX1.L, #0x100
|
||||
MADDX $AX0.L, $AX1.L ; SIGNED (!)
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
CLR15
|
||||
|
||||
|
||||
; Test MULC - SET15
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
LRI $AC0.M, #0xFFFF
|
||||
LRI $AX0.H, #0x100
|
||||
MULC $AC0.M, $AX0.H ; SIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
SET15
|
||||
LRI $AC0.M, #0xFFFF
|
||||
LRI $AX0.H, #0x100
|
||||
MULC $AC0.M, $AX0.H ; SIGNED (!)
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
CLR15
|
||||
|
||||
|
||||
; Test MULCAC - SET15
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
LRI $AC0.M, #0xFFFF
|
||||
LRI $AX0.H, #0x100
|
||||
MULCAC $AC0.M, $AX0.H, $ACC0 ; SIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
SET15
|
||||
LRI $AC0.M, #0xFFFF
|
||||
LRI $AX0.H, #0x100
|
||||
MULCAC $AC0.M, $AX0.H, $ACC0 ; SIGNED (!)
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
CLR15
|
||||
|
||||
|
||||
; Test MUL - SET15
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX0.H, #0x100
|
||||
MUL $AX0.L, $AX0.H ; SIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
|
||||
CLR $ACC0
|
||||
SET15
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX0.H, #0x100
|
||||
MUL $AX0.L, $AX0.H ; SIGNED (!)
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
CLR15
|
||||
|
||||
|
||||
; Test MULAC - SET15
|
||||
CLR $ACC0
|
||||
CLRP
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX0.H, #0x100
|
||||
MULAC $AX0.L, $AX0.H, $ACC0 ; SIGNED
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
|
||||
CLR $ACC0
|
||||
SET15
|
||||
LRI $AX0.L, #0xFFFF
|
||||
LRI $AX0.H, #0x100
|
||||
MULAC $AX0.L, $AX0.H, $ACC0 ; SIGNED (!)
|
||||
MOVP $ACC0
|
||||
call send_back
|
||||
CLR15
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
; We're done, DO NOT DELETE THIS LINE
|
||||
jmp end_of_test
|
||||
|
||||
; test accelerator
|
||||
|
||||
; TODO: DSPSpy puts a 16-bit ramp at 0x10000000
|
||||
LRIS $AC1.M, #0x0a ; 16-bit PCM audio
|
||||
;SRS @SampleFormat, $AC1.M
|
||||
; Start accelerator position
|
||||
LRI $AC1.M, #0x0100
|
||||
SRS @ACCAH, $AC1.M
|
||||
LRI $AC1.M, #0x1000
|
||||
SRS @ACCAH, $AC1.M
|
||||
; Current accelerator position
|
||||
LRI $AC1.M, #0x0100
|
||||
SRS @ACCAH, $AC1.M
|
||||
LRI $AC1.M, #0x1000
|
||||
SRS @ACCAH, $AC1.M
|
||||
; End accelerator position
|
||||
LRI $AC1.M, #0x0100
|
||||
SRS @ACCAH, $AC1.M
|
||||
LRI $AC1.M, #0x2000
|
||||
SRS @ACCAH, $AC1.M
|
||||
|
||||
; Now to the interesting parameter - gain.
|
||||
LRI $AC1.M, #0xFFFF
|
||||
SRS @GAIN, $AC1.M
|
||||
|
||||
; Let's now load a sample through the accelerator.
|
||||
LRS $AC1.M, @ARAM
|
||||
call send_back
|
||||
|
||||
jmp end_of_test
|
||||
|
||||
; test addpaxz
|
||||
call send_back
|
||||
|
||||
clrp
|
||||
lri $AX0.L, #0x1111
|
||||
lri $AX0.H, #0x2222
|
||||
call send_back
|
||||
|
||||
clrp
|
||||
addpaxz $ACC0, $AX0.H
|
||||
|
||||
call send_back
|
||||
|
||||
clrp
|
||||
set40
|
||||
addpaxz $ACC0, $AX0.H
|
||||
set16
|
||||
|
||||
call send_back
|
||||
|
||||
clrp
|
||||
set15
|
||||
addpaxz $ACC0, $AX0.H
|
||||
clr15
|
||||
|
||||
call send_back
|
||||
|
||||
|
||||
jmp end_of_test
|
||||
|
||||
|
||||
@ -1,49 +1,49 @@
|
||||
incdir "tests"
|
||||
include "dsp_base.inc"
|
||||
|
||||
; Reads regs from 0xFF80 to 0xFF8D and sends them back
|
||||
|
||||
lr $AC0.M, @0xff80
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff81
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff82
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff83
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff84
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff85
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff86
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff87
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff88
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff89
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff8A
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff8B
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff8C
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff8D
|
||||
call send_back
|
||||
|
||||
; We're done, DO NOT DELETE THIS LINE
|
||||
jmp end_of_test
|
||||
incdir "tests"
|
||||
include "dsp_base.inc"
|
||||
|
||||
; Reads regs from 0xFF80 to 0xFF8D and sends them back
|
||||
|
||||
lr $AC0.M, @0xff80
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff81
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff82
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff83
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff84
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff85
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff86
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff87
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff88
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff89
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff8A
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff8B
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff8C
|
||||
call send_back
|
||||
|
||||
lr $AC0.M, @0xff8D
|
||||
call send_back
|
||||
|
||||
; We're done, DO NOT DELETE THIS LINE
|
||||
jmp end_of_test
|
||||
|
||||
Reference in New Issue
Block a user