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Updated C bit on TLB cache hits.
Added TLB state to the save state file.
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@ -28,7 +28,7 @@ std::string PPCDebugInterface::Disassemble(unsigned int address)
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if (!Memory::IsRAMAddress(address, true, true))
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{
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if (!SConfig::GetInstance().m_LocalCoreStartupParameter.bMMU || !((address & JIT_ICACHE_VMEM_BIT) &&
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Memory::TranslateAddress(address, Memory::FLAG_OPCODE)))
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Memory::TranslateAddress(address, Memory::FLAG_NO_EXCEPTION)))
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{
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return "(No RAM here)";
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}
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