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LLE JIT:

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* Added 21 Arithmetic instructions to the JIT
* Used the DSPAnalyser to identify arithmetic/multiplier instructions that precede a conditional branch.  This allows the JIT to skip updating the SR when nothing would read from it.  Marked all arithmetic/multiplier instructions in the DSPTable for this purpose.
* Converted CheckExternalInterrupt into ASM
* Fixed a couple instructions in DSP Load/Store


git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6633 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
skidau
2010-12-21 14:48:05 +00:00
parent 0030d55725
commit 6cb78515c6
11 changed files with 977 additions and 514 deletions
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674
Source/Core/DSPCore/Src/Jit/DSPJitArithmetic.cpp
View File

@ -20,6 +20,7 @@
#include "../DSPIntCCUtil.h"
#include "../DSPIntUtil.h"
#include "../DSPEmitter.h"
#include "../DSPAnalyzer.h"
#include "x64Emitter.h"
#include "ABI.h"
using namespace Gen;
@ -96,14 +97,21 @@ using namespace Gen;
// Test accumulator %acR.
//
// flags out: --xx xx00
//void DSPEmitter::tst(const UDSPInstruction opc)
//{
// u8 reg = (opc >> 11) & 0x1;
// s64 acc = dsp_get_long_acc(reg);
// Update_SR_Register64(acc);
// zeroWriteBackLog();
//}
void DSPEmitter::tst(const UDSPInstruction opc)
{
#ifdef _M_X64
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
u8 reg = (opc >> 11) & 0x1;
// s64 acc = dsp_get_long_acc(reg);
get_long_acc(reg);
// Update_SR_Register64(acc);
Update_SR_Register64();
}
#else
Default(opc);
#endif
}
// TSTAXH $axR.h
// 1000 011r xxxx xxxx
@ -383,8 +391,8 @@ void DSPEmitter::addr(const UDSPInstruction opc)
MOV(64, R(R11), ImmPtr(&g_dsp.r));
// s64 acc = dsp_get_long_acc(dreg);
get_long_acc(dreg);
PUSH(64, R(RAX));
get_long_acc(dreg, RCX);
MOV(64, R(RAX), R(RCX));
// s64 ax = (s16)g_dsp.r[sreg];
MOVSX(64, 16, RDX, MDisp(R11, sreg * 2));
// ax <<= 16;
@ -392,27 +400,18 @@ void DSPEmitter::addr(const UDSPInstruction opc)
// s64 res = acc + ax;
ADD(64, R(RAX), R(RDX));
// dsp_set_long_acc(dreg, res);
set_long_acc(dreg);
// Update_SR_Register64(res, isCarry(acc, res), isOverflow(acc, ax, res));
XOR(8, R(RSI), R(RSI));
POP(64, R(RCX));
CMP(64, R(RCX), R(RAX));
// Carry = (acc>res)
FixupBranch noCarry = J_CC(CC_G);
OR(8, R(RSI), Imm8(1));
SetJumpTarget(noCarry);
// Overflow = ((acc ^ res) & (ax ^ res)) < 0
XOR(64, R(RCX), R(RAX));
XOR(64, R(RDX), R(RAX));
AND(64, R(RCX), R(RDX));
CMP(64, R(RCX), Imm8(0));
FixupBranch noOverflow = J_CC(CC_L);
OR(8, R(RSI), Imm8(2));
SetJumpTarget(noOverflow);
Update_SR_Register64();
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
MOV(64, R(RSI), R(RAX));
set_long_acc(dreg, RSI);
Update_SR_Register64_Carry();
}
else
{
set_long_acc(dreg, RAX);
}
#else
Default(opc);
#endif
@ -423,61 +422,106 @@ void DSPEmitter::addr(const UDSPInstruction opc)
// Adds secondary accumulator $axS to accumulator register $acD.
//
// flags out: x-xx xxxx
//void DSPEmitter::addax(const UDSPInstruction opc)
//{
// u8 dreg = (opc >> 8) & 0x1;
// u8 sreg = (opc >> 9) & 0x1;
void DSPEmitter::addax(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 dreg = (opc >> 8) & 0x1;
u8 sreg = (opc >> 9) & 0x1;
// s64 acc = dsp_get_long_acc(dreg);
get_long_acc(dreg, RCX);
MOV(64, R(RAX), R(RCX));
// s64 ax = dsp_get_long_acx(sreg);
get_long_acx(sreg, RDX);
// s64 res = acc + ax;
// zeroWriteBackLog();
ADD(64, R(RAX), R(RDX));
// dsp_set_long_acc(dreg, res);
// res = dsp_get_long_acc(dreg);
// Update_SR_Register64(res, isCarry(acc, res), isOverflow(acc, ax, res));
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
MOV(64, R(RSI), R(RAX));
set_long_acc(dreg, RSI);
Update_SR_Register64_Carry();
}
else
{
set_long_acc(dreg, RAX);
}
#else
Default(opc);
#endif
}
// ADD $acD, $ac(1-D)
// 0100 110d xxxx xxxx
// Adds accumulator $ac(1-D) to accumulator register $acD.
//
// flags out: x-xx xxxx
//void DSPEmitter::add(const UDSPInstruction opc)
//{
// u8 dreg = (opc >> 8) & 0x1;
void DSPEmitter::add(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 dreg = (opc >> 8) & 0x1;
// s64 acc0 = dsp_get_long_acc(dreg);
get_long_acc(dreg, RCX);
MOV(64, R(RAX), R(RCX));
// s64 acc1 = dsp_get_long_acc(1 - dreg);
get_long_acc(1 - dreg, RDX);
// s64 res = acc0 + acc1;
// zeroWriteBackLog();
ADD(64, R(RAX), R(RDX));
// dsp_set_long_acc(dreg, res);
// res = dsp_get_long_acc(dreg);
// Update_SR_Register64(res, isCarry(acc0, res), isOverflow(acc0, acc1, res));
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
MOV(64, R(RSI), R(RAX));
set_long_acc(dreg, RSI);
Update_SR_Register64_Carry();
}
else
{
set_long_acc(dreg, RAX);
}
#else
Default(opc);
#endif
}
// ADDP $acD
// 0100 111d xxxx xxxx
// Adds product register to accumulator register.
//
// flags out: x-xx xxxx
//void DSPEmitter::addp(const UDSPInstruction opc)
//{
// u8 dreg = (opc >> 8) & 0x1;
void DSPEmitter::addp(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 dreg = (opc >> 8) & 0x1;
// s64 acc = dsp_get_long_acc(dreg);
get_long_acc(dreg, RCX);
MOV(64, R(RAX), R(RCX));
// s64 prod = dsp_get_long_prod();
get_long_prod(RDX);
// s64 res = acc + prod;
// zeroWriteBackLog();
ADD(64, R(RAX), R(RDX));
// dsp_set_long_acc(dreg, res);
// res = dsp_get_long_acc(dreg);
// Update_SR_Register64(res, isCarry2(acc, res), isOverflow(acc, prod, res));
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
MOV(64, R(RSI), R(RAX));
set_long_acc(dreg, RSI);
Update_SR_Register64_Carry2();
}
else
{
set_long_acc(dreg, RAX);
}
#else
Default(opc);
#endif
}
// ADDAXL $acD, $axS.l
// 0111 00sd xxxx xxxx
@ -508,77 +552,145 @@ void DSPEmitter::addr(const UDSPInstruction opc)
// Adds immediate (16-bit sign extended) to mid accumulator $acD.hm.
//
// flags out: x-xx xxxx
//void DSPEmitter::addi(const UDSPInstruction opc)
//{
// u8 areg = (opc >> 8) & 0x1;
void DSPEmitter::addi(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 areg = (opc >> 8) & 0x1;
// s64 acc = dsp_get_long_acc(areg);
get_long_acc(areg, RCX);
MOV(64, R(RAX), R(RCX));
// s64 imm = (s16)dsp_fetch_code();
// imm <<= 16;
s16 imm = dsp_imem_read(compilePC+1);
//imm <<= 16;
MOV(16, R(RDX), Imm16(imm));
MOVSX(64, 16, RDX, R(RDX));
SHL(64, R(RDX), Imm8(16));
// s64 res = acc + imm;
ADD(64, R(RAX), R(RDX));
// dsp_set_long_acc(areg, res);
// res = dsp_get_long_acc(areg);
// Update_SR_Register64(res, isCarry(acc, res), isOverflow(acc, imm, res));
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
MOV(64, R(RSI), R(RAX));
set_long_acc(areg, RSI);
Update_SR_Register64_Carry();
}
else
{
set_long_acc(areg, RAX);
}
#else
Default(opc);
#endif
}
// ADDIS $acD, #I
// 0000 010d iiii iiii
// Adds short immediate (8-bit sign extended) to mid accumulator $acD.hm.
//
// flags out: x-xx xxxx
//void DSPEmitter::addis(const UDSPInstruction opc)
//{
// u8 dreg = (opc >> 8) & 0x1;
void DSPEmitter::addis(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 dreg = (opc >> 8) & 0x1;
// s64 acc = dsp_get_long_acc(dreg);
get_long_acc(dreg, RCX);
MOV(64, R(RAX), R(RCX));
// s64 imm = (s8)(u8)opc;
// imm <<= 16;
MOV(8, R(RDX), Imm8((u8)opc));
MOVSX(64, 8, RDX, R(RDX));
SHL(64, R(RDX), Imm8(16));
// s64 res = acc + imm;
ADD(64, R(RAX), R(RDX));
// dsp_set_long_acc(dreg, res);
// res = dsp_get_long_acc(dreg);
// Update_SR_Register64(res, isCarry(acc, res), isOverflow(acc, imm, res));
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
MOV(64, R(RSI), R(RAX));
set_long_acc(dreg, RSI);
Update_SR_Register64_Carry();
}
else
{
set_long_acc(dreg, RAX);
}
#else
Default(opc);
#endif
}
// INCM $acsD
// 0111 010d xxxx xxxx
// Increment 24-bit mid-accumulator $acsD.
//
// flags out: x-xx xxxx
//void DSPEmitter::incm(const UDSPInstruction opc)
//{
// u8 dreg = (opc >> 8) & 0x1;
// s64 sub = 0x10000;
void DSPEmitter::incm(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 dreg = (opc >> 8) & 0x1;
s64 sub = 0x10000;
// s64 acc = dsp_get_long_acc(dreg);
get_long_acc(dreg, RCX);
MOV(64, R(RAX), R(RCX));
// s64 res = acc + sub;
// zeroWriteBackLog();
//
ADD(64, R(RAX), Imm32((u32)sub));
// dsp_set_long_acc(dreg, res);
// res = dsp_get_long_acc(dreg);
// Update_SR_Register64(res, isCarry(acc, res), isOverflow(acc, sub, res));
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
MOV(64, R(RDX), Imm32((u32)sub));
MOV(64, R(RSI), R(RAX));
set_long_acc(dreg, RSI);
Update_SR_Register64_Carry();
}
else
{
set_long_acc(dreg);
Update_SR_Register64_Carry();
}
#else
Default(opc);
#endif
}
// INC $acD
// 0111 011d xxxx xxxx
// Increment accumulator $acD.
//
// flags out: x-xx xxxx
//void DSPEmitter::inc(const UDSPInstruction opc)
//{
// u8 dreg = (opc >> 8) & 0x1;
void DSPEmitter::inc(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 dreg = (opc >> 8) & 0x1;
// s64 acc = dsp_get_long_acc(dreg);
// s64 res = acc + 1;
// zeroWriteBackLog();
get_long_acc(dreg, RCX);
MOV(64, R(RAX), R(RCX));
// s64 res = acc + 1;
ADD(64, R(RAX), Imm8(1));
// dsp_set_long_acc(dreg, res);
// res = dsp_get_long_acc(dreg);
// Update_SR_Register64(res, isCarry(acc, res), isOverflow(acc, 1, res));
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
MOV(64, R(RDX), Imm64(1));
MOV(64, R(RSI), R(RAX));
set_long_acc(dreg, RSI);
Update_SR_Register64_Carry();
}
else
{
set_long_acc(dreg);
Update_SR_Register64_Carry();
}
#else
Default(opc);
#endif
}
//----
@ -587,122 +699,216 @@ void DSPEmitter::addr(const UDSPInstruction opc)
// Subtracts register $axS.L from accumulator $acD.M register.
//
// flags out: x-xx xxxx
//void DSPEmitter::subr(const UDSPInstruction opc)
//{
// u8 dreg = (opc >> 8) & 0x1;
// u8 sreg = ((opc >> 9) & 0x3) + DSP_REG_AXL0;
void DSPEmitter::subr(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 dreg = (opc >> 8) & 0x1;
u8 sreg = ((opc >> 9) & 0x3) + DSP_REG_AXL0;
// s64 acc = dsp_get_long_acc(dreg);
get_long_acc(dreg, RCX);
MOV(64, R(RAX), R(RCX));
// s64 ax = (s16)g_dsp.r[sreg];
MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVSX(64, 16, RDX, MDisp(R11, sreg * 2));
// ax <<= 16;
SHL(64, R(RDX), Imm8(16));
// s64 res = acc - ax;
// zeroWriteBackLog();
SUB(64, R(RAX), R(RDX));
// dsp_set_long_acc(dreg, res);
// res = dsp_get_long_acc(dreg);
// Update_SR_Register64(res, isCarry2(acc, res), isOverflow(acc, -ax, res));
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
NEG(64, R(RDX));
MOV(64, R(RSI), R(RAX));
set_long_acc(dreg, RSI);
Update_SR_Register64_Carry2();
}
else
{
set_long_acc(dreg, RAX);
}
#else
Default(opc);
#endif
}
// SUBAX $acD, $axS
// 0101 10sd xxxx xxxx
// Subtracts secondary accumulator $axS from accumulator register $acD.
//
// flags out: x-xx xxxx
//void DSPEmitter::subax(const UDSPInstruction opc)
//{
// u8 dreg = (opc >> 8) & 0x1;
// u8 sreg = (opc >> 9) & 0x1;
void DSPEmitter::subax(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 dreg = (opc >> 8) & 0x1;
u8 sreg = (opc >> 9) & 0x1;
// s64 acc = dsp_get_long_acc(dreg);
get_long_acc(dreg, RCX);
MOV(64, R(RAX), R(RCX));
// s64 acx = dsp_get_long_acx(sreg);
get_long_acx(sreg, RDX);
// s64 res = acc - acx;
// zeroWriteBackLog();
SUB(64, R(RAX), R(RDX));
// dsp_set_long_acc(dreg, res);
// res = dsp_get_long_acc(dreg);
// Update_SR_Register64(res, isCarry2(acc, res), isOverflow(acc, -acx, res));
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
NEG(64, R(RDX));
MOV(64, R(RSI), R(RAX));
set_long_acc(dreg, RSI);
Update_SR_Register64_Carry2();
}
else
{
set_long_acc(dreg, RAX);
}
#else
Default(opc);
#endif
}
// SUB $acD, $ac(1-D)
// 0101 110d xxxx xxxx
// Subtracts accumulator $ac(1-D) from accumulator register $acD.
//
// flags out: x-xx xxxx
//void DSPEmitter::sub(const UDSPInstruction opc)
//{
// u8 dreg = (opc >> 8) & 0x1;
void DSPEmitter::sub(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 dreg = (opc >> 8) & 0x1;
// s64 acc1 = dsp_get_long_acc(dreg);
get_long_acc(dreg, RCX);
MOV(64, R(RAX), R(RCX));
// s64 acc2 = dsp_get_long_acc(1 - dreg);
get_long_acc(1 - dreg, RDX);
// s64 res = acc1 - acc2;
// zeroWriteBackLog();
SUB(64, R(RAX), R(RDX));
// dsp_set_long_acc(dreg, res);
// res = dsp_get_long_acc(dreg);
// Update_SR_Register64(res, isCarry2(acc1, res), isOverflow(acc1, -acc2, res));
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
NEG(64, R(RDX));
MOV(64, R(RSI), R(RAX));
set_long_acc(dreg, RSI);
Update_SR_Register64_Carry2();
}
else
{
set_long_acc(dreg, RAX);
}
#else
Default(opc);
#endif
}
// SUBP $acD
// 0101 111d xxxx xxxx
// Subtracts product register from accumulator register.
//
// flags out: x-xx xxxx
//void DSPEmitter::subp(const UDSPInstruction opc)
//{
// u8 dreg = (opc >> 8) & 0x1;
void DSPEmitter::subp(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 dreg = (opc >> 8) & 0x1;
// s64 acc = dsp_get_long_acc(dreg);
get_long_acc(dreg, RCX);
MOV(64, R(RAX), R(RCX));
// s64 prod = dsp_get_long_prod();
get_long_prod(RDX);
// s64 res = acc - prod;
// zeroWriteBackLog();
SUB(64, R(RAX), R(RDX));
// dsp_set_long_acc(dreg, res);
// res = dsp_get_long_acc(dreg);
// Update_SR_Register64(res, isCarry2(acc, res), isOverflow(acc, -prod, res));
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
NEG(64, R(RDX));
MOV(64, R(RSI), R(RAX));
set_long_acc(dreg, RSI);
Update_SR_Register64_Carry2();
}
else
{
set_long_acc(dreg, RAX);
}
#else
Default(opc);
#endif
}
// DECM $acsD
// 0111 100d xxxx xxxx
// Decrement 24-bit mid-accumulator $acsD.
//
// flags out: x-xx xxxx
//void DSPEmitter::decm(const UDSPInstruction opc)
//{
// u8 dreg = (opc >> 8) & 0x01;
// s64 sub = 0x10000;
void DSPEmitter::decm(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 dreg = (opc >> 8) & 0x01;
s64 sub = 0x10000;
// s64 acc = dsp_get_long_acc(dreg);
get_long_acc(dreg, RCX);
MOV(64, R(RAX), R(RCX));
// s64 res = acc - sub;
// zeroWriteBackLog();
//
SUB(64, R(RAX), Imm32((u32)sub));
// dsp_set_long_acc(dreg, res);
// res = dsp_get_long_acc(dreg);
// Update_SR_Register64(res, isCarry2(acc, res), isOverflow(acc, -sub, res));
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
MOV(64, R(RDX), Imm64(-sub));
MOV(64, R(RSI), R(RAX));
set_long_acc(dreg, RSI);
Update_SR_Register64_Carry2();
}
else
{
set_long_acc(dreg, RAX);
}
#else
Default(opc);
#endif
}
// DEC $acD
// 0111 101d xxxx xxxx
// Decrement accumulator $acD.
//
// flags out: x-xx xxxx
//void DSPEmitter::dec(const UDSPInstruction opc)
//{
// u8 dreg = (opc >> 8) & 0x01;
void DSPEmitter::dec(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 dreg = (opc >> 8) & 0x01;
// s64 acc = dsp_get_long_acc(dreg);
get_long_acc(dreg, RCX);
MOV(64, R(RAX), R(RCX));
// s64 res = acc - 1;
// zeroWriteBackLog();
SUB(64, R(RAX), Imm8(1));
// dsp_set_long_acc(dreg, res);
set_long_acc(dreg);
// res = dsp_get_long_acc(dreg);
// Update_SR_Register64(res, isCarry2(acc, res), isOverflow(acc, -1, res));
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
MOV(8, R(RDX), Imm8(1));
NEG(8, R(RDX));
MOV(64, R(RSI), R(RAX));
set_long_acc(dreg, RSI);
Update_SR_Register64_Carry2();
}
else
{
set_long_acc(dreg, RAX);
}
#else
Default(opc);
#endif
}
//----
@ -711,38 +917,55 @@ void DSPEmitter::addr(const UDSPInstruction opc)
// Negate accumulator $acD.
//
// flags out: --xx xx00
//void DSPEmitter::neg(const UDSPInstruction opc)
//{
// u8 dreg = (opc >> 8) & 0x1;
//
void DSPEmitter::neg(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 dreg = (opc >> 8) & 0x1;
// s64 acc = dsp_get_long_acc(dreg);
get_long_acc(dreg);
// acc = 0 - acc;
// zeroWriteBackLog();
NEG(64, R(RAX));
// dsp_set_long_acc(dreg, acc);
set_long_acc(dreg);
// Update_SR_Register64(dsp_get_long_acc(dreg));
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif
}
// ABS $acD
// 1010 d001 xxxx xxxx
// absolute value of $acD
//
// flags out: --xx xx00
//void DSPEmitter::abs(const UDSPInstruction opc)
//{
// u8 dreg = (opc >> 11) & 0x1;
void DSPEmitter::abs(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 dreg = (opc >> 11) & 0x1;
// s64 acc = dsp_get_long_acc(dreg);
// if (acc < 0)
// acc = 0 - acc;
//
// zeroWriteBackLog();
get_long_acc(dreg);
// if (acc < 0) acc = 0 - acc;
CMP(64, R(RAX), Imm8(0));
FixupBranch lessThan = J_CC(CC_L);
NEG(64, R(RAX));
set_long_acc(dreg);
SetJumpTarget(lessThan);
// dsp_set_long_acc(dreg, acc);
set_long_acc(dreg);
// Update_SR_Register64(dsp_get_long_acc(dreg));
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif
}
//----
// MOVR $acD, $axS.R
@ -752,54 +975,76 @@ void DSPEmitter::addr(const UDSPInstruction opc)
// TODO: Check what happens to acD.h.
//
// flags out: --xx xx00
//void DSPEmitter::movr(const UDSPInstruction opc)
//{
// u8 areg = (opc >> 8) & 0x1;
// u8 sreg = ((opc >> 9) & 0x3) + DSP_REG_AXL0;
//
void DSPEmitter::movr(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 areg = (opc >> 8) & 0x1;
u8 sreg = ((opc >> 9) & 0x3) + DSP_REG_AXL0;
// s64 acc = (s16)g_dsp.r[sreg];
MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVSX(64, 16, RAX, MDisp(R11, sreg * 2));
// acc <<= 16;
SHL(64, R(RAX), Imm8(16));
// acc &= ~0xffff;
// zeroWriteBackLog();
// dsp_set_long_acc(areg, acc);
// Update_SR_Register64(acc);
//}
set_long_acc(areg);
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif
}
// MOVAX $acD, $axS
// 0110 10sd xxxx xxxx
// Moves secondary accumulator $axS to accumulator $axD.
//
// flags out: --xx xx00
//void DSPEmitter::movax(const UDSPInstruction opc)
//{
// u8 dreg = (opc >> 8) & 0x1;
// u8 sreg = (opc >> 9) & 0x1;
void DSPEmitter::movax(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 dreg = (opc >> 8) & 0x1;
u8 sreg = (opc >> 9) & 0x1;
// s64 acx = dsp_get_long_acx(sreg);
// zeroWriteBackLog();
get_long_acx(sreg);
// dsp_set_long_acc(dreg, acx);
set_long_acc(dreg);
// Update_SR_Register64(acx);
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif
}
// MOV $acD, $ac(1-D)
// 0110 110d xxxx xxxx
// Moves accumulator $ax(1-D) to accumulator $axD.
//
// flags out: --x0 xx00
//void DSPEmitter::mov(const UDSPInstruction opc)
//{
// u8 dreg = (opc >> 8) & 0x1;
void DSPEmitter::mov(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 dreg = (opc >> 8) & 0x1;
// u64 acc = dsp_get_long_acc(1 - dreg);
// zeroWriteBackLog();
get_long_acc(1 - dreg);
// dsp_set_long_acc(dreg, acc);
set_long_acc(dreg);
// Update_SR_Register64(acc);
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif
}
//----
@ -810,6 +1055,7 @@ void DSPEmitter::addr(const UDSPInstruction opc)
// flags out: --xx xx00
void DSPEmitter::lsl16(const UDSPInstruction opc)
{
Default(opc); return; // TODO: Breaks ZTP Wii
#ifdef _M_X64
u8 areg = (opc >> 8) & 0x1;
// s64 acc = dsp_get_long_acc(areg);
@ -819,7 +1065,10 @@ void DSPEmitter::lsl16(const UDSPInstruction opc)
// dsp_set_long_acc(areg, acc);
set_long_acc(areg);
// Update_SR_Register64(dsp_get_long_acc(areg));
Update_SR_Register64();
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif
@ -830,37 +1079,54 @@ void DSPEmitter::lsl16(const UDSPInstruction opc)
// Logically shifts right accumulator $acR by 16.
//
// flags out: --xx xx00
//void DSPEmitter::lsr16(const UDSPInstruction opc)
//{
// u8 areg = (opc >> 8) & 0x1;
void DSPEmitter::lsr16(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 areg = (opc >> 8) & 0x1;
// u64 acc = dsp_get_long_acc(areg);
get_long_acc(areg);
// acc &= 0x000000FFFFFFFFFFULL; // Lop off the extraneous sign extension our 64-bit fake accum causes
// acc >>= 16;
// zeroWriteBackLog();
SHR(64, R(RAX), Imm8(16));
AND(64, R(RAX), Imm32(0xffffff));
// dsp_set_long_acc(areg, (s64)acc);
set_long_acc(areg);
// Update_SR_Register64(dsp_get_long_acc(areg));
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif
}
// ASR16 $acR
// 1001 r001 xxxx xxxx
// Arithmetically shifts right accumulator $acR by 16.
//
// flags out: --xx xx00
//void DSPEmitter::asr16(const UDSPInstruction opc)
//{
// u8 areg = (opc >> 11) & 0x1;
void DSPEmitter::asr16(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 areg = (opc >> 11) & 0x1;
// s64 acc = dsp_get_long_acc(areg);
get_long_acc(areg);
// acc >>= 16;
// zeroWriteBackLog();
SHR(64, R(RAX), Imm8(16));
// dsp_set_long_acc(areg, acc);
set_long_acc(areg);
// Update_SR_Register64(dsp_get_long_acc(areg));
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif
}
// LSL $acR, #I
// 0001 010r 00ii iiii
@ -876,12 +1142,15 @@ void DSPEmitter::lsl(const UDSPInstruction opc)
get_long_acc(rreg);
// acc <<= shift;
SHL(64, R(RAX), Imm8(shift));
SHL(64, R(RAX), Imm8((u8)shift));
// dsp_set_long_acc(rreg, acc);
set_long_acc(rreg);
// Update_SR_Register64(dsp_get_long_acc(rreg));
Update_SR_Register64();
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif
@ -916,17 +1185,26 @@ void DSPEmitter::lsl(const UDSPInstruction opc)
// Logically shifts left accumulator $acR by number specified by value I.
//
// flags out: --xx xx00
//void DSPEmitter::asl(const UDSPInstruction opc)
//{
// u8 rreg = (opc >> 8) & 0x01;
// u16 shift = opc & 0x3f;
void DSPEmitter::asl(const UDSPInstruction opc)
{
#ifdef _M_X64
u8 rreg = (opc >> 8) & 0x01;
u16 shift = opc & 0x3f;
// u64 acc = dsp_get_long_acc(rreg);
get_long_acc(rreg);
// acc <<= shift;
//
SHL(64, R(RAX), Imm8((u8)shift));
// dsp_set_long_acc(rreg, acc);
set_long_acc(rreg);
// Update_SR_Register64(dsp_get_long_acc(rreg));
//}
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif
}
// ASR $acR, #I
// 0001 010r 11ii iiii

136
Source/Core/DSPCore/Src/Jit/DSPJitCCUtil.cpp
View File

@ -29,62 +29,124 @@ using namespace Gen;
// In: RAX: s64 _Value
// In: RCX: 1 = carry, 2 = overflow
// Clobbers RDX
void DSPEmitter::Update_SR_Register64(bool carry, bool overflow)
void DSPEmitter::Update_SR_Register(Gen::X64Reg val)
{
#ifdef _M_X64
// // 0x04
// if (_Value == 0) g_dsp.r[DSP_REG_SR] |= SR_ARITH_ZERO;
CMP(64, R(val), Imm8(0));
FixupBranch notZero = J_CC(CC_NZ);
OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_ARITH_ZERO));
SetJumpTarget(notZero);
// // 0x08
// if (_Value < 0) g_dsp.r[DSP_REG_SR] |= SR_SIGN;
CMP(64, R(val), Imm8(0));
FixupBranch greaterThanEqual = J_CC(CC_GE);
OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_SIGN));
SetJumpTarget(greaterThanEqual);
// // 0x10
// if (_Value != (s32)_Value) g_dsp.r[DSP_REG_SR] |= SR_OVER_S32;
MOVSX(64, 32, RDX, R(val));
CMP(64, R(RDX), R(val));
FixupBranch noOverS32 = J_CC(CC_E);
OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_OVER_S32));
SetJumpTarget(noOverS32);
// // 0x20 - Checks if top bits of m are equal
// if (((_Value & 0xc0000000) == 0) || ((_Value & 0xc0000000) == 0xc0000000))
AND(32, R(val), Imm32(0xc0000000));
CMP(32, R(val), Imm32(0));
FixupBranch zeroC = J_CC(CC_E);
CMP(32, R(val), Imm32(0xc0000000));
FixupBranch cC = J_CC(CC_NE);
SetJumpTarget(zeroC);
// g_dsp.r[DSP_REG_SR] |= SR_TOP2BITS;
OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_TOP2BITS));
SetJumpTarget(cC);
#endif
}
// In: RAX: s64 _Value
// In: RCX: 1 = carry, 2 = overflow
// Clobbers RDX
void DSPEmitter::Update_SR_Register64(Gen::X64Reg val)
{
#ifdef _M_X64
// g_dsp.r[DSP_REG_SR] &= ~SR_CMP_MASK;
AND(16, MDisp(R11, DSP_REG_SR * 2), Imm16(~SR_CMP_MASK));
Update_SR_Register(val);
#endif
}
// In: RAX: s64 _Value
// In: RCX: 1 = carry, 2 = overflow
// Clobbers RDX
void DSPEmitter::Update_SR_Register64_Carry(Gen::X64Reg val)
{
#ifdef _M_X64
// g_dsp.r[DSP_REG_SR] &= ~SR_CMP_MASK;
AND(16, MDisp(R11, DSP_REG_SR * 2), Imm16(~SR_CMP_MASK));
CMP(64, R(RCX), R(val));
// 0x01
// g_dsp.r[DSP_REG_SR] |= SR_CARRY;
TEST(8, R(RSI), Imm8(1));
FixupBranch noCarry = J_CC(CC_NZ);
// Carry = (acc>res)
FixupBranch noCarry = J_CC(CC_BE);
OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_CARRY));
SetJumpTarget(noCarry);
// 0x02 and 0x80
// g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW;
// g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW_STICKY;
TEST(8, R(RSI), Imm8(2));
FixupBranch noOverflow = J_CC(CC_NZ);
// Overflow = ((acc ^ res) & (ax ^ res)) < 0
XOR(64, R(RCX), R(val));
XOR(64, R(RDX), R(val));
AND(64, R(RCX), R(RDX));
CMP(64, R(RCX), Imm8(0));
FixupBranch noOverflow = J_CC(CC_GE);
OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_OVERFLOW | SR_OVERFLOW_STICKY));
SetJumpTarget(noOverflow);
// // 0x04
// if (_Value == 0) g_dsp.r[DSP_REG_SR] |= SR_ARITH_ZERO;
TEST(64, R(RAX), R(RAX));
FixupBranch notZero = J_CC(CC_NZ);
OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_ARITH_ZERO));
SetJumpTarget(notZero);
// // 0x08
// if (_Value < 0) g_dsp.r[DSP_REG_SR] |= SR_SIGN;
FixupBranch greaterThanEqual = J_CC(CC_NS);
OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_SIGN));
SetJumpTarget(greaterThanEqual);
// // 0x10
// if (_Value != (s32)_Value) g_dsp.r[DSP_REG_SR] |= SR_OVER_S32;
MOVSX(64, 32, RDX, R(RAX));
CMP(64, R(RDX), R(RAX));
FixupBranch noOverS32 = J_CC(CC_E);
OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_OVER_S32));
SetJumpTarget(noOverS32);
// // 0x20 - Checks if top bits of m are equal
// if (((_Value & 0xc0000000) == 0) || ((_Value & 0xc0000000) == 0xc0000000))
AND(32, R(EAX), Imm32(0xc0000000));
CMP(32, R(EAX), Imm32(0));
FixupBranch zeroC = J_CC(CC_E);
CMP(32, R(EAX), Imm32(0xc0000000));
FixupBranch cC = J_CC(CC_NE);
SetJumpTarget(zeroC);
// g_dsp.r[DSP_REG_SR] |= SR_TOP2BITS;
OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_TOP2BITS));
SetJumpTarget(cC);
Update_SR_Register(val);
#endif
}
// In: RAX: s64 _Value
// In: RCX: 1 = carry, 2 = overflow
// Clobbers RDX
void DSPEmitter::Update_SR_Register64_Carry2(Gen::X64Reg val)
{
#ifdef _M_X64
// g_dsp.r[DSP_REG_SR] &= ~SR_CMP_MASK;
AND(16, MDisp(R11, DSP_REG_SR * 2), Imm16(~SR_CMP_MASK));
CMP(64, R(RCX), R(val));
// 0x01
// g_dsp.r[DSP_REG_SR] |= SR_CARRY;
// Carry2 = (acc>=res)
FixupBranch noCarry2 = J_CC(CC_B);
OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_CARRY));
SetJumpTarget(noCarry2);
// 0x02 and 0x80
// g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW;
// g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW_STICKY;
// Overflow = ((acc ^ res) & (ax ^ res)) < 0
XOR(64, R(RCX), R(val));
XOR(64, R(RDX), R(val));
AND(64, R(RCX), R(RDX));
CMP(64, R(RCX), Imm8(0));
FixupBranch noOverflow = J_CC(CC_GE);
OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_OVERFLOW | SR_OVERFLOW_STICKY));
SetJumpTarget(noOverflow);
Update_SR_Register();
#endif
}
//void DSPEmitter::Update_SR_Register16(s16 _Value, bool carry, bool overflow, bool overS32)
//{

4
Source/Core/DSPCore/Src/Jit/DSPJitLoadStore.cpp
View File

@ -319,7 +319,7 @@ void DSPEmitter::ilrrd(const UDSPInstruction opc)
MOV(16, MDisp(R11,dreg*2), R(RAX));
#endif
dsp_conditional_extend_accum(dreg);
dsp_decrement_addr_reg(reg);
decrement_addr_reg(reg);
}
// ILRRI $acD.m, @$S
@ -345,7 +345,7 @@ void DSPEmitter::ilrri(const UDSPInstruction opc)
MOV(16, MDisp(R11,dreg*2), R(RAX));
#endif
dsp_conditional_extend_accum(dreg);
dsp_increment_addr_reg(reg);
increment_addr_reg(reg);
}
// ILRRN $acD.m, @$arS

57
Source/Core/DSPCore/Src/Jit/DSPJitMultiplier.cpp
View File

@ -22,6 +22,7 @@
#include "../DSPIntUtil.h"
#include "../DSPEmitter.h"
#include "../DSPAnalyzer.h"
#include "x64Emitter.h"
#include "ABI.h"
using namespace Gen;
@ -166,10 +167,13 @@ void DSPEmitter::clrp(const UDSPInstruction opc)
void DSPEmitter::tstprod(const UDSPInstruction opc)
{
#ifdef _M_X64
// s64 prod = dsp_get_long_prod();
get_long_prod();
// Update_SR_Register64(prod);
Update_SR_Register64();
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
// s64 prod = dsp_get_long_prod();
get_long_prod();
// Update_SR_Register64(prod);
Update_SR_Register64();
}
#else
Default(opc);
#endif
@ -192,7 +196,10 @@ void DSPEmitter::movp(const UDSPInstruction opc)
// dsp_set_long_acc(dreg, acc);
set_long_acc(dreg);
// Update_SR_Register64(acc);
Update_SR_Register64();
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif
@ -215,7 +222,10 @@ void DSPEmitter::movnp(const UDSPInstruction opc)
// dsp_set_long_acc(dreg, acc);
set_long_acc(dreg);
// Update_SR_Register64(acc);
Update_SR_Register64();
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif
@ -237,7 +247,10 @@ void DSPEmitter::movpz(const UDSPInstruction opc)
// dsp_set_long_acc(dreg, acc);
set_long_acc(dreg);
// Update_SR_Register64(acc);
Update_SR_Register64();
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif
@ -342,7 +355,10 @@ void DSPEmitter::mulac(const UDSPInstruction opc)
POP(64, R(RAX));
set_long_acc(rreg);
// Update_SR_Register64(dsp_get_long_acc(rreg));
Update_SR_Register64();
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif
@ -368,7 +384,10 @@ void DSPEmitter::mulmv(const UDSPInstruction opc)
POP(64, R(RAX));
set_long_acc(rreg);
// Update_SR_Register64(dsp_get_long_acc(rreg));
Update_SR_Register64();
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif
@ -395,7 +414,10 @@ void DSPEmitter::mulmvz(const UDSPInstruction opc)
POP(64, R(RAX));
set_long_acc(rreg);
// Update_SR_Register64(dsp_get_long_acc(rreg));
Update_SR_Register64();
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif
@ -555,7 +577,10 @@ void DSPEmitter::mulcac(const UDSPInstruction opc)
POP(64, R(RAX));
set_long_acc(rreg);
// Update_SR_Register64(dsp_get_long_acc(rreg));
Update_SR_Register64();
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif
@ -591,7 +616,10 @@ void DSPEmitter::mulcmv(const UDSPInstruction opc)
POP(64, R(RAX));
set_long_acc(rreg);
// Update_SR_Register64(dsp_get_long_acc(rreg));
Update_SR_Register64();
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif
@ -629,7 +657,10 @@ void DSPEmitter::mulcmvz(const UDSPInstruction opc)
POP(64, R(RAX));
set_long_acc(rreg);
// Update_SR_Register64(dsp_get_long_acc(rreg));
Update_SR_Register64();
if (!(DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_START_OF_INST) || (DSPAnalyzer::code_flags[compilePC] & DSPAnalyzer::CODE_UPDATE_SR))
{
Update_SR_Register64();
}
#else
Default(opc);
#endif

88
Source/Core/DSPCore/Src/Jit/DSPJitUtil.cpp
View File

@ -466,14 +466,15 @@ void DSPEmitter::dmem_read_imm(u16 address)
// Returns s64 in RAX
// Clobbers RSI, RDI
void DSPEmitter::get_long_prod()
void DSPEmitter::get_long_prod(X64Reg long_prod)
{
#ifdef _M_X64
/*
MOV(64, R(R11), ImmPtr(&g_dsp.r));
//s64 val = (s8)(u8)g_dsp.r[DSP_REG_PRODH];
MOVSX(64, 8, RAX, MDisp(R11,DSP_REG_PRODH*2));
MOVSX(64, 8, long_prod, MDisp(R11,DSP_REG_PRODH*2));
//val <<= 32;
SHL(64, R(RAX), Imm8(32));
SHL(64, R(long_prod), Imm8(32));
//s64 low_prod = g_dsp.r[DSP_REG_PRODM];
MOVSX(64, 16, RSI, MDisp(R11,DSP_REG_PRODM*2));
//low_prod += g_dsp.r[DSP_REG_PRODM2];
@ -481,33 +482,50 @@ void DSPEmitter::get_long_prod()
ADD(16, R(RSI), R(EDI));
//low_prod <<= 16;
SHL(64, R(RSI), Imm8(16));
OR(64, R(RAX), R(RSI));
OR(64, R(long_prod), R(RSI));
//low_prod |= g_dsp.r[DSP_REG_PRODL];
MOV(16, R(RAX), MDisp(R11,DSP_REG_PRODL*2));
MOV(16, R(long_prod), MDisp(R11,DSP_REG_PRODL*2));
//return val;
*/
MOV(64, R(R11), ImmPtr(&g_dsp.r));
//s64 val = (s8)(u8)g_dsp.r[DSP_REG_PRODH];
MOVSX(64, 8, long_prod, MDisp(R11,DSP_REG_PRODH*2));
//val <<= 32;
SHL(64, R(long_prod), Imm8(16));
//s64 low_prod = g_dsp.r[DSP_REG_PRODM];
OR(16, R(long_prod), MDisp(R11,DSP_REG_PRODM*2));
//low_prod += g_dsp.r[DSP_REG_PRODM2];
ADD(16, R(long_prod), MDisp(R11,DSP_REG_PRODM2*2));
//low_prod <<= 16;
SHL(64, R(long_prod), Imm8(16));
//low_prod |= g_dsp.r[DSP_REG_PRODL];
OR(16, R(long_prod), MDisp(R11,DSP_REG_PRODL*2));
//return val;
#endif
}
// Returns s64 in RAX
// Clobbers RSI
void DSPEmitter::get_long_prod_round_prodl()
void DSPEmitter::get_long_prod_round_prodl(X64Reg long_prod)
{
#ifdef _M_X64
//s64 prod = dsp_get_long_prod();
get_long_prod();
//if (prod & 0x10000) prod = (prod + 0x8000) & ~0xffff;
TEST(32, R(EAX), Imm32(0x10000));
TEST(32, R(long_prod), Imm32(0x10000));
FixupBranch jump = J_CC(CC_Z);
ADD(64, R(RAX), Imm32(0x8000));
ADD(64, R(long_prod), Imm32(0x8000));
MOV(64, R(ESI), Imm64(~0xffff));
AND(64, R(RAX), R(RSI));
AND(64, R(long_prod), R(RSI));
FixupBranch ret = J();
//else prod = (prod + 0x7fff) & ~0xffff;
SetJumpTarget(jump);
ADD(64, R(RAX), Imm32(0x7fff));
ADD(64, R(long_prod), Imm32(0x7fff));
MOV(64, R(RSI), Imm64(~0xffff));
AND(64, R(RAX), R(RSI));
AND(64, R(long_prod), R(RSI));
SetJumpTarget(ret);
//return prod;
#endif
@ -523,13 +541,13 @@ void DSPEmitter::set_long_prod()
MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11, DSP_REG_PRODL * 2), R(AX));
// val >>= 16;
SHR(64, R(RAX), Imm8(16));
SAR(64, R(RAX), Imm8(16));
// g_dsp.r[DSP_REG_PRODM] = (u16)val;
MOV(16, MDisp(R11, DSP_REG_PRODM * 2), R(AX));
// val >>= 16;
SHR(64, R(RAX), Imm8(16));
SAR(64, R(RAX), Imm8(16));
// g_dsp.r[DSP_REG_PRODH] = (u8)val;
MOVZX(64, 8, RAX, R(AL));
MOVSX(64, 8, RAX, R(AL));
MOV(8, MDisp(R11, DSP_REG_PRODH * 2), R(AL));
// g_dsp.r[DSP_REG_PRODM2] = 0;
MOV(16, MDisp(R11, DSP_REG_PRODM2 * 2), Imm16(0));
@ -537,40 +555,38 @@ void DSPEmitter::set_long_prod()
}
// Returns s64 in RAX
// Clobbers ESI
void DSPEmitter::get_long_acc(int _reg)
void DSPEmitter::get_long_acc(int _reg, X64Reg acc)
{
#ifdef _M_X64
// s64 high = (s64)(s8)g_dsp.r[DSP_REG_ACH0 + reg] << 32;
MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVSX(64, 8, EAX, MDisp(R11, (DSP_REG_ACH0 + _reg) * 2));
SHL(64, R(EAX), Imm8(32));
MOVSX(64, 8, acc, MDisp(R11, (DSP_REG_ACH0 + _reg) * 2));
SHL(64, R(acc), Imm8(16));
// u32 mid_low = ((u32)g_dsp.r[DSP_REG_ACM0 + reg] << 16) | g_dsp.r[DSP_REG_ACL0 + reg];
MOVZX(64, 16, RSI, MDisp(R11, (DSP_REG_ACM0 + _reg) * 2));
SHL(32, R(RSI), Imm8(16));
OR(64, R(EAX), R(RSI));
MOVZX(64, 16, RSI, MDisp(R11, (DSP_REG_ACL0 + _reg) * 2));
OR(64, R(EAX), R(RSI));
OR(16, R(acc), MDisp(R11, (DSP_REG_ACM0 + _reg) * 2));
SHL(64, R(acc), Imm8(16));
OR(16, R(acc), MDisp(R11, (DSP_REG_ACL0 + _reg) * 2));
// return high | mid_low;
#endif
}
// In: RAX = s64 val
void DSPEmitter::set_long_acc(int _reg)
// Clobbers the input reg
void DSPEmitter::set_long_acc(int _reg, X64Reg acc)
{
#ifdef _M_X64
// g_dsp.r[DSP_REG_ACL0 + _reg] = (u16)val;
MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11, (DSP_REG_ACL0 + _reg) * 2), R(AX));
MOV(16, MDisp(R11, (DSP_REG_ACL0 + _reg) * 2), R(acc));
// val >>= 16;
SHR(64, R(RAX), Imm8(16));
SHR(64, R(acc), Imm8(16));
// g_dsp.r[DSP_REG_ACM0 + _reg] = (u16)val;
MOV(16, MDisp(R11, (DSP_REG_ACM0 + _reg) * 2), R(AX));
MOV(16, MDisp(R11, (DSP_REG_ACM0 + _reg) * 2), R(acc));
// val >>= 16;
SHR(64, R(RAX), Imm8(16));
SHR(64, R(acc), Imm8(16));
// g_dsp.r[DSP_REG_ACH0 + _reg] = (u16)(s16)(s8)(u8)val;
MOVSX(16, 8, AX, R(AX));
MOV(16, MDisp(R11, (DSP_REG_ACH0 + _reg) * 2), R(AX));
MOVSX(64, 8, acc, R(acc));
MOV(16, MDisp(R11, (DSP_REG_ACH0 + _reg) * 2), R(acc));
#endif
}
@ -584,6 +600,18 @@ void DSPEmitter::get_acc_m(int _reg)
#endif
}
// Returns u32 in EAX
void DSPEmitter::get_long_acx(int _reg, X64Reg acx)
{
// return ((u32)g_dsp.r[DSP_REG_AXH0 + _reg] << 16) | g_dsp.r[DSP_REG_AXL0 + _reg];
#ifdef _M_X64
MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVSX(64, 16, acx, MDisp(R11, (DSP_REG_AXH0 + _reg) * 2));
SHL(64, R(acx), Imm8(16));
OR(16, R(acx), MDisp(R11, (DSP_REG_AXL0 + _reg) * 2));
#endif
}
// Returns s16 in EAX
void DSPEmitter::get_ax_l(int _reg)
{