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JIT: Add support for memory accesses with scaled index register but without base register
This is mostly useful for removing SHLs by constant 1, 2, 3, which this commit implements in one place. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@7652 8ced0084-cf51-0410-be5f-012b33b47a6e
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@ -110,23 +110,22 @@ void Jit64::psq_st(UGeckoInstruction inst)
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MOVZX(32, 8, EDX, R(AL));
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// FIXME: Fix ModR/M encoding to allow [EDX*4+disp32] without a base register!
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#ifdef _M_IX86
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int addr_shift = 2;
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int addr_scale = SCALE_4;
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#else
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int addr_shift = 3;
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int addr_scale = SCALE_8;
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#endif
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SHL(32, R(EDX), Imm8(addr_shift));
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if (inst.W) {
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// One value
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XORPS(XMM0, R(XMM0)); // TODO: See if we can get rid of this cheaply by tweaking the code in the singleStore* functions.
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CVTSD2SS(XMM0, fpr.R(s));
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ABI_AlignStack(0);
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CALLptr(MDisp(EDX, (u32)(u64)asm_routines.singleStoreQuantized));
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CALLptr(MScaled(EDX, addr_scale, (u32)(u64)asm_routines.singleStoreQuantized));
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ABI_RestoreStack(0);
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} else {
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// Pair of values
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CVTPD2PS(XMM0, fpr.R(s));
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ABI_AlignStack(0);
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CALLptr(MDisp(EDX, (u32)(u64)asm_routines.pairedStoreQuantized));
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CALLptr(MScaled(EDX, addr_scale, (u32)(u64)asm_routines.pairedStoreQuantized));
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ABI_RestoreStack(0);
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}
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gpr.UnlockAll();
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@ -169,14 +168,13 @@ void Jit64::psq_l(UGeckoInstruction inst)
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MOV(32, gpr.R(inst.RA), R(ECX));
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MOVZX(32, 16, EAX, M(((char *)&GQR(inst.I)) + 2));
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MOVZX(32, 8, EDX, R(AL));
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// FIXME: Fix ModR/M encoding to allow [EDX*4+disp32]! (MComplex can do this, no?)
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#ifdef _M_IX86
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SHL(32, R(EDX), Imm8(2));
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int addr_scale = SCALE_4;
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#else
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SHL(32, R(EDX), Imm8(3));
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int addr_scale = SCALE_8;
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#endif
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ABI_AlignStack(0);
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CALLptr(MDisp(EDX, (u32)(u64)asm_routines.pairedLoadQuantized));
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CALLptr(MScaled(EDX, addr_scale, (u32)(u64)asm_routines.pairedLoadQuantized));
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ABI_RestoreStack(0);
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// MEMCHECK_START // FIXME: MMU does not work here because of unsafe memory access
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