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Merge pull request #8755 from Sintendo/jit64intopts

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Jit64: More addx and subfx optimizations
This commit is contained in:
Markus Wick 2020-04-24 07:40:07 +02:00 committed by GitHub
commit 703f7d4fc0
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 40 additions and 10 deletions
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48
Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
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@ -932,6 +932,10 @@ void Jit64::subfx(UGeckoInstruction inst)
MOV(32, Rd, Rb);
SUB(32, Rd, R(RSCRATCH));
}
else if (Rb.IsSimpleReg() && Ra.IsImm() && !inst.OE)
{
LEA(32, Rd, MDisp(Rb.GetSimpleReg(), -Ra.SImm32()));
}
else
{
MOV(32, Rd, Rb);
@ -1330,25 +1334,51 @@ void Jit64::addx(UGeckoInstruction inst)
RCX64Reg Rd = gpr.Bind(d, RCMode::Write);
RegCache::Realize(Ra, Rb, Rd);
if (d == a)
if ((d == a) || (d == b))
{
ADD(32, Rd, Rb);
RCOpArg& Rnotd = (d == a) ? Rb : Ra;
if (!Rnotd.IsZero() || inst.OE)
{
ADD(32, Rd, Rnotd);
}
else if (d == b)
{
ADD(32, Rd, Ra);
}
else if (Ra.IsSimpleReg() && Rb.IsSimpleReg() && !inst.OE)
{
LEA(32, Rd, MRegSum(Ra.GetSimpleReg(), Rb.GetSimpleReg()));
}
else if (Ra.IsSimpleReg() && Rb.IsImm() && !inst.OE)
else if ((Ra.IsSimpleReg() || Rb.IsSimpleReg()) && (Ra.IsImm() || Rb.IsImm()) && !inst.OE)
{
LEA(32, Rd, MDisp(Ra.GetSimpleReg(), Rb.SImm32()));
RCOpArg& Rimm = Ra.IsImm() ? Ra : Rb;
RCOpArg& Rreg = Ra.IsImm() ? Rb : Ra;
if (Rimm.IsZero())
{
MOV(32, Rd, Rreg);
}
else if (Rb.IsSimpleReg() && Ra.IsImm() && !inst.OE)
else
{
LEA(32, Rd, MDisp(Rb.GetSimpleReg(), Ra.SImm32()));
LEA(32, Rd, MDisp(Rreg.GetSimpleReg(), Rimm.SImm32()));
}
}
else if (Ra.IsImm() || Rb.IsImm())
{
RCOpArg& Rimm = Ra.IsImm() ? Ra : Rb;
RCOpArg& Rother = Ra.IsImm() ? Rb : Ra;
s32 imm = Rimm.SImm32();
if (imm >= -128 && imm <= 127)
{
MOV(32, Rd, Rother);
if (imm != 0 || inst.OE)
{
ADD(32, Rd, Rimm);
}
}
else
{
MOV(32, Rd, Rimm);
ADD(32, Rd, Rother);
}
}
else
{