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Merge pull request #8755 from Sintendo/jit64intopts
Jit64: More addx and subfx optimizations
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commit
703f7d4fc0
@ -932,6 +932,10 @@ void Jit64::subfx(UGeckoInstruction inst)
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MOV(32, Rd, Rb);
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SUB(32, Rd, R(RSCRATCH));
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}
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else if (Rb.IsSimpleReg() && Ra.IsImm() && !inst.OE)
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{
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LEA(32, Rd, MDisp(Rb.GetSimpleReg(), -Ra.SImm32()));
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}
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else
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{
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MOV(32, Rd, Rb);
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@ -1330,25 +1334,51 @@ void Jit64::addx(UGeckoInstruction inst)
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RCX64Reg Rd = gpr.Bind(d, RCMode::Write);
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RegCache::Realize(Ra, Rb, Rd);
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if (d == a)
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if ((d == a) || (d == b))
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{
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ADD(32, Rd, Rb);
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}
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else if (d == b)
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{
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ADD(32, Rd, Ra);
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RCOpArg& Rnotd = (d == a) ? Rb : Ra;
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if (!Rnotd.IsZero() || inst.OE)
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{
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ADD(32, Rd, Rnotd);
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}
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}
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else if (Ra.IsSimpleReg() && Rb.IsSimpleReg() && !inst.OE)
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{
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LEA(32, Rd, MRegSum(Ra.GetSimpleReg(), Rb.GetSimpleReg()));
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}
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else if (Ra.IsSimpleReg() && Rb.IsImm() && !inst.OE)
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else if ((Ra.IsSimpleReg() || Rb.IsSimpleReg()) && (Ra.IsImm() || Rb.IsImm()) && !inst.OE)
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{
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LEA(32, Rd, MDisp(Ra.GetSimpleReg(), Rb.SImm32()));
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RCOpArg& Rimm = Ra.IsImm() ? Ra : Rb;
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RCOpArg& Rreg = Ra.IsImm() ? Rb : Ra;
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if (Rimm.IsZero())
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{
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MOV(32, Rd, Rreg);
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}
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else
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{
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LEA(32, Rd, MDisp(Rreg.GetSimpleReg(), Rimm.SImm32()));
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}
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}
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else if (Rb.IsSimpleReg() && Ra.IsImm() && !inst.OE)
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else if (Ra.IsImm() || Rb.IsImm())
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{
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LEA(32, Rd, MDisp(Rb.GetSimpleReg(), Ra.SImm32()));
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RCOpArg& Rimm = Ra.IsImm() ? Ra : Rb;
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RCOpArg& Rother = Ra.IsImm() ? Rb : Ra;
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s32 imm = Rimm.SImm32();
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if (imm >= -128 && imm <= 127)
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{
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MOV(32, Rd, Rother);
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if (imm != 0 || inst.OE)
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{
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ADD(32, Rd, Rimm);
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}
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}
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else
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{
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MOV(32, Rd, Rimm);
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ADD(32, Rd, Rother);
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}
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}
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else
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{
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