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https://github.com/dolphin-emu/dolphin.git
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DSPLLE - flags&stuff,xar->subarn,0x80 kinda figured out,... (experimental)
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@5174 8ced0084-cf51-0410-be5f-012b33b47a6e
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@ -37,6 +37,7 @@
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// ---------------------------------------------------------------------------------------
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// --- SR
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// ---------------------------------------------------------------------------------------
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inline void dsp_SR_set_flag(int flag)
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{
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g_dsp.r[DSP_REG_SR] |= flag;
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@ -47,9 +48,13 @@ inline bool dsp_SR_is_flag_set(int flag)
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return (g_dsp.r[DSP_REG_SR] & flag) != 0;
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}
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// ---------------------------------------------------------------------------------------
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// --- AR increments, decrements
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// ---------------------------------------------------------------------------------------
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//
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// HORRIBLE UGLINESS, someone please fix.
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// See http://code.google.com/p/dolphin-emu/source/detail?r=3125
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inline u16 ToMask(u16 a)
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{
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a = a | (a >> 8);
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@ -112,6 +117,24 @@ inline s16 dsp_increase_addr_reg(int reg, s16 value)
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return tmp;
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}
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inline s16 dsp_decrease_addr_reg(int reg, s16 value)
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{
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s16 tmp = - 1;
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// TODO: DO RIGHT!
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if (value > 0) {
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for (int i = 0; i < value; i++) {
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tmp = dsp_decrement_addr_reg(reg, tmp);
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}
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} else if (value < 0) {
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for (int i = 0; i < (int)(-value); i++) {
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tmp = dsp_increment_addr_reg(reg, tmp);
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}
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} else
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tmp = g_dsp.r[reg];
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return tmp;
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}
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// ---------------------------------------------------------------------------------------
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// --- reg
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@ -143,18 +166,8 @@ inline void dsp_op_write_reg(int reg, u16 val)
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case DSP_REG_ACM0:
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case DSP_REG_ACM1:
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g_dsp.r[reg] = val;
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// Enabling the below sign extension code breaks things.
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// There's probably some condition that enable it, maybe one of
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// the status flags like M2.
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// Or maybe it only happens when this call is a result of 'l and similar extended opcodes.
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// Sign extend the loaded register. ACM0
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// g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACH0] = ((s16)val < 0 ? 0xFFFF : 0);
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// g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACL0] = 0; // ?
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break;
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// There might also be something similar for AX.L but I'm not at all sure about that.
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// Stack registers.
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case DSP_REG_ST0:
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case DSP_REG_ST1:
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@ -262,21 +275,18 @@ inline s16 dsp_get_acc_l(int _reg)
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return g_dsp.r[DSP_REG_ACL0 + _reg];
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}
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inline s16 dsp_get_acc_m(int _reg)
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{
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_assert_(_reg < 2);
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return g_dsp.r[DSP_REG_ACM0 + _reg];
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}
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inline s16 dsp_get_acc_h(int _reg)
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{
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_assert_(_reg < 2);
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return g_dsp.r[DSP_REG_ACH0 + _reg];
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}
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// ---------------------------------------------------------------------------------------
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// --- AX - extra accumulators (32-bit)
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// ---------------------------------------------------------------------------------------
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