mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2024-11-14 21:37:52 -07:00
JIT: more optimizing of float ops based on known input characteristics
If the inputs are both float singles, and the top half is known to be identical to the bottom half, we can use packed arithmetic instead of scalar to skip the movddup. This is slower on a few rather old CPUs, plus the Atom+Silvermont, so detect Atom and disable it in that case. Also avoid PPC_FP on stores if we know that the output came from a float op.
This commit is contained in:
parent
4e0591cdf1
commit
72c96c20d3
@ -50,10 +50,10 @@ struct CPUInfo
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bool bMOVBE;
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// This flag indicates that the hardware supports some mode
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// in which denormal inputs _and_ outputs are automatically set to (signed) zero.
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// TODO: ARM
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bool bFlushToZero;
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bool bLAHFSAHF64;
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bool bLongMode;
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bool bAtom;
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// ARM specific CPUInfo
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bool bSwp;
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@ -129,6 +129,12 @@ void CPUInfo::Detect()
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if (max_std_fn >= 1)
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{
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__cpuid(cpu_id, 0x00000001);
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int family = ((cpu_id[0] >> 8) & 0xf) + ((cpu_id[0] >> 20) & 0xff);
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int model = ((cpu_id[0] >> 4) & 0xf) + ((cpu_id[0] >> 12) & 0xf0);
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// Detect people unfortunate enough to be running Dolphin on an Atom
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if (family == 6 && (model == 0x1C || model == 0x26 ||model == 0x27 || model == 0x35 || model == 0x36 ||
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model == 0x37 || model == 0x4A || model == 0x4D || model == 0x5A || model == 0x5D))
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bAtom = true;
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logical_cpu_count = (cpu_id[1] >> 16) & 0xFF;
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ht = (cpu_id[3] >> 28) & 1;
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@ -151,7 +151,7 @@ public:
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void regimmop(int d, int a, bool binary, u32 value, Operation doop, void (Gen::XEmitter::*op)(int, const Gen::OpArg&, const Gen::OpArg&),
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bool Rc = false, bool carry = false);
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void fp_tri_op(int d, int a, int b, bool reversible, bool single, void (Gen::XEmitter::*avxOp)(Gen::X64Reg, Gen::X64Reg, Gen::OpArg),
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void (Gen::XEmitter::*sseOp)(Gen::X64Reg, Gen::OpArg), UGeckoInstruction inst, bool roundRHS = false);
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void (Gen::XEmitter::*sseOp)(Gen::X64Reg, Gen::OpArg), UGeckoInstruction inst, bool packed = false, bool roundRHS = false);
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void FloatCompare(UGeckoInstruction inst, bool upper = false);
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// OPCODES
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@ -11,11 +11,12 @@
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using namespace Gen;
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static const u64 GC_ALIGNED16(psSignBits[2]) = {0x8000000000000000ULL, 0x0000000000000000ULL};
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static const u64 GC_ALIGNED16(psSignBits2[2]) = {0x8000000000000000ULL, 0x8000000000000000ULL};
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static const u64 GC_ALIGNED16(psAbsMask[2]) = {0x7FFFFFFFFFFFFFFFULL, 0xFFFFFFFFFFFFFFFFULL};
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static const double GC_ALIGNED16(half_qnan_and_s32_max[2]) = {0x7FFFFFFF, -0x80000};
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void Jit64::fp_tri_op(int d, int a, int b, bool reversible, bool single, void (XEmitter::*avxOp)(X64Reg, X64Reg, OpArg),
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void (XEmitter::*sseOp)(X64Reg, OpArg), UGeckoInstruction inst, bool roundRHS)
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void (XEmitter::*sseOp)(X64Reg, OpArg), UGeckoInstruction inst, bool packed, bool roundRHS)
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{
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fpr.Lock(d, a, b);
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fpr.BindToRegister(d, d == a || d == b || !single);
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@ -34,13 +35,20 @@ void Jit64::fp_tri_op(int d, int a, int b, bool reversible, bool single, void (X
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}
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else
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{
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avx_op(avxOp, sseOp, fpr.RX(d), fpr.R(a), fpr.R(b), false, reversible);
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avx_op(avxOp, sseOp, fpr.RX(d), fpr.R(a), fpr.R(b), packed, reversible);
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}
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if (single)
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{
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ForceSinglePrecisionS(fpr.RX(d));
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if (packed)
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{
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ForceSinglePrecisionP(fpr.RX(d), fpr.RX(d));
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}
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else
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{
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ForceSinglePrecisionS(fpr.RX(d), fpr.RX(d));
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MOVDDUP(fpr.RX(d), fpr.R(d));
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}
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}
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SetFPRFIfNeeded(inst, fpr.RX(d));
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fpr.UnlockAll();
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}
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@ -63,14 +71,32 @@ void Jit64::fp_arith(UGeckoInstruction inst)
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JITDISABLE(bJITFloatingPointOff);
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FALLBACK_IF(inst.Rc);
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int a = inst.FA;
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int b = inst.FB;
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int c = inst.FC;
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int d = inst.FD;
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int arg2 = inst.SUBOP5 == 25 ? c : b;
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bool single = inst.OPCD == 59;
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bool round_input = single && !jit->js.op->fprIsSingle[inst.FC];
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// If both the inputs are known to have identical top and bottom halves, we can skip the MOVDDUP at the end by
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// using packed arithmetic instead.
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bool packed = single && jit->js.op->fprIsDuplicated[a] && jit->js.op->fprIsDuplicated[arg2];
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// Packed divides are slower than scalar divides on basically all x86, so this optimization isn't worth it in that case.
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// Atoms (and a few really old CPUs) are also slower on packed operations than scalar ones.
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if (inst.SUBOP5 == 18 || cpu_info.bAtom)
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packed = false;
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switch (inst.SUBOP5)
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{
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case 18: fp_tri_op(inst.FD, inst.FA, inst.FB, false, single, &XEmitter::VDIVSD, &XEmitter::DIVSD, inst); break; //div
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case 20: fp_tri_op(inst.FD, inst.FA, inst.FB, false, single, &XEmitter::VSUBSD, &XEmitter::SUBSD, inst); break; //sub
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case 21: fp_tri_op(inst.FD, inst.FA, inst.FB, true, single, &XEmitter::VADDSD, &XEmitter::ADDSD, inst); break; //add
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case 25: fp_tri_op(inst.FD, inst.FA, inst.FC, true, single, &XEmitter::VMULSD, &XEmitter::MULSD, inst, round_input); break; //mul
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case 18: fp_tri_op(d, a, b, false, single, packed ? &XEmitter::VDIVPD : &XEmitter::VDIVSD,
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packed ? &XEmitter::DIVPD : &XEmitter::DIVSD, inst, packed); break;
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case 20: fp_tri_op(d, a, b, false, single, packed ? &XEmitter::VSUBPD : &XEmitter::VSUBSD,
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packed ? &XEmitter::SUBPD : &XEmitter::SUBSD, inst, packed); break;
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case 21: fp_tri_op(d, a, b, true, single, packed ? &XEmitter::VADDPD : &XEmitter::VADDSD,
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packed ? &XEmitter::ADDPD : &XEmitter::ADDSD, inst, packed); break;
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case 25: fp_tri_op(d, a, c, true, single, packed ? &XEmitter::VMULPD : &XEmitter::VMULSD,
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packed ? &XEmitter::MULPD : &XEmitter::MULSD, inst, packed, round_input); break;
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default:
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_assert_msg_(DYNA_REC, 0, "fp_arith WTF!!!");
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}
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@ -88,6 +114,9 @@ void Jit64::fmaddXX(UGeckoInstruction inst)
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int d = inst.FD;
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bool single = inst.OPCD == 59;
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bool round_input = single && !jit->js.op->fprIsSingle[c];
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bool packed = single && jit->js.op->fprIsDuplicated[a] && jit->js.op->fprIsDuplicated[b] && jit->js.op->fprIsDuplicated[c];
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if (cpu_info.bAtom)
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packed = false;
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fpr.Lock(a, b, c, d);
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@ -109,9 +138,15 @@ void Jit64::fmaddXX(UGeckoInstruction inst)
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switch (inst.SUBOP5)
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{
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case 28: //msub
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if (packed)
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VFMSUB132PD(XMM0, fpr.RX(b), fpr.R(a));
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else
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VFMSUB132SD(XMM0, fpr.RX(b), fpr.R(a));
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break;
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case 29: //madd
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if (packed)
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VFMADD132PD(XMM0, fpr.RX(b), fpr.R(a));
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else
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VFMADD132SD(XMM0, fpr.RX(b), fpr.R(a));
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break;
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// PowerPC and x86 define NMADD/NMSUB differently
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@ -119,9 +154,15 @@ void Jit64::fmaddXX(UGeckoInstruction inst)
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// PPC: D = -(A*C (+/-) B)
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// so we have to swap them; the ADD/SUB here isn't a typo.
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case 30: //nmsub
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if (packed)
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VFNMADD132PD(XMM0, fpr.RX(b), fpr.R(a));
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else
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VFNMADD132SD(XMM0, fpr.RX(b), fpr.R(a));
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break;
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case 31: //nmadd
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if (packed)
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VFNMSUB132PD(XMM0, fpr.RX(b), fpr.R(a));
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else
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VFNMSUB132SD(XMM0, fpr.RX(b), fpr.R(a));
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break;
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}
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@ -133,32 +174,57 @@ void Jit64::fmaddXX(UGeckoInstruction inst)
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Force25BitPrecision(XMM1, fpr.R(c), XMM0);
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else
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MOVAPD(XMM1, fpr.R(c));
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MULSD(XMM1, fpr.R(a));
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MOVAPD(XMM0, fpr.R(b));
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if (packed)
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{
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MULPD(XMM1, fpr.R(a));
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SUBPD(XMM0, R(XMM1));
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}
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else
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{
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MULSD(XMM1, fpr.R(a));
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SUBSD(XMM0, R(XMM1));
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}
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}
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else
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{
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if (single && round_input)
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Force25BitPrecision(XMM0, fpr.R(c), XMM1);
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else
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MOVAPD(XMM0, fpr.R(c));
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MULSD(XMM0, fpr.R(a));
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if (packed)
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{
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MULPD(XMM0, fpr.R(a));
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if (inst.SUBOP5 == 28) //msub
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SUBSD(XMM0, fpr.R(b));
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SUBPD(XMM0, fpr.R(b));
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else //(n)madd
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ADDPD(XMM0, fpr.R(b));
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}
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else
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{
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MULSD(XMM0, fpr.R(a));
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if (inst.SUBOP5 == 28)
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SUBSD(XMM0, fpr.R(b));
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else
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ADDSD(XMM0, fpr.R(b));
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}
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if (inst.SUBOP5 == 31) //nmadd
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PXOR(XMM0, M((void*)&psSignBits));
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PXOR(XMM0, M((void*)&(packed ? psSignBits2 : psSignBits)));
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}
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fpr.BindToRegister(d, !single);
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//YES it is necessary to dupe the result :(
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//TODO : analysis - does the top reg get used? If so, dupe, if not, don't.
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if (single)
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{
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ForceSinglePrecisionS(XMM0);
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MOVDDUP(fpr.RX(d), R(XMM0));
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if (packed)
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{
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ForceSinglePrecisionP(fpr.RX(d), XMM0);
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}
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else
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{
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ForceSinglePrecisionS(fpr.RX(d), XMM0);
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MOVDDUP(fpr.RX(d), fpr.R(d));
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}
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}
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else
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{
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@ -427,7 +493,7 @@ void Jit64::frspx(UGeckoInstruction inst)
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fpr.BindToRegister(d, d == b);
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if (b != d)
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MOVAPD(fpr.RX(d), fpr.R(b));
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ForceSinglePrecisionS(fpr.RX(d));
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ForceSinglePrecisionS(fpr.RX(d), fpr.RX(d));
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MOVDDUP(fpr.RX(d), fpr.R(d));
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SetFPRFIfNeeded(inst, fpr.RX(d));
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fpr.UnlockAll();
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@ -107,9 +107,16 @@ void Jit64::stfXXX(UGeckoInstruction inst)
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FALLBACK_IF(update && js.memcheck && a == b);
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if (single)
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{
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if (jit->js.op->fprIsStoreSafe[s])
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{
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CVTSD2SS(XMM0, fpr.R(s));
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}
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else
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{
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fpr.BindToRegister(s, true, false);
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ConvertDoubleToSingle(XMM0, fpr.RX(s));
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}
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MOVD_xmm(R(RSCRATCH), XMM0);
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}
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else
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@ -667,13 +667,17 @@ void EmuCodeBlock::WriteToConstRamAddress(int accessSize, OpArg arg, u32 address
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MOV(accessSize, MDisp(RMEM, address & 0x3FFFFFFF), R(reg));
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}
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void EmuCodeBlock::ForceSinglePrecisionS(X64Reg xmm)
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void EmuCodeBlock::ForceSinglePrecisionS(X64Reg output, X64Reg input)
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{
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// Most games don't need these. Zelda requires it though - some platforms get stuck without them.
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if (jit->jo.accurateSinglePrecision)
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{
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CVTSD2SS(xmm, R(xmm));
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CVTSS2SD(xmm, R(xmm));
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CVTSD2SS(input, R(input));
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CVTSS2SD(output, R(input));
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}
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else if (output != input)
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{
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MOVAPD(output, R(input));
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}
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}
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@ -130,7 +130,7 @@ public:
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void avx_op(void (Gen::XEmitter::*avxOp)(Gen::X64Reg, Gen::X64Reg, Gen::OpArg, u8), void (Gen::XEmitter::*sseOp)(Gen::X64Reg, Gen::OpArg, u8),
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Gen::X64Reg regOp, Gen::OpArg arg1, Gen::OpArg arg2, u8 imm);
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void ForceSinglePrecisionS(Gen::X64Reg xmm);
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void ForceSinglePrecisionS(Gen::X64Reg output, Gen::X64Reg input);
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void ForceSinglePrecisionP(Gen::X64Reg output, Gen::X64Reg input);
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void Force25BitPrecision(Gen::X64Reg output, Gen::OpArg input, Gen::X64Reg tmp);
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@ -830,18 +830,45 @@ u32 PPCAnalyzer::Analyze(u32 address, CodeBlock *block, CodeBuffer *buffer, u32
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fprInUse[code[i].fregOut] = true;
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}
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// Forward scan, for flags that need the other direction for calculation
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BitSet32 fprIsSingle;
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// Forward scan, for flags that need the other direction for calculation.
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BitSet32 fprIsSingle, fprIsDuplicated, fprIsStoreSafe;
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for (u32 i = 0; i < block->m_num_instructions; i++)
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{
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code[i].fprIsSingle = fprIsSingle;
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code[i].fprIsDuplicated = fprIsDuplicated;
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code[i].fprIsStoreSafe = fprIsStoreSafe;
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if (code[i].fregOut >= 0)
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{
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// This instruction outputs float, so we can omit the special rounding done in fmuls/fmadds
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if (code[i].opinfo->type == OPTYPE_SINGLEFP || code[i].opinfo->type == OPTYPE_PS || strncmp(code[i].opinfo->opname, "lfs", 3))
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fprIsSingle[code[i].fregOut] = true;
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else
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fprIsSingle[code[i].fregOut] = false;
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fprIsDuplicated[code[i].fregOut] = false;
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fprIsStoreSafe[code[i].fregOut] = false;
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// Single, duplicated, and doesn't need PPC_FP.
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if (code[i].opinfo->type == OPTYPE_SINGLEFP)
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{
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fprIsSingle[code[i].fregOut] = true;
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fprIsDuplicated[code[i].fregOut] = true;
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fprIsStoreSafe[code[i].fregOut] = true;
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}
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// Single and duplicated, but might be a denormal (not safe to skip PPC_FP).
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// TODO: if we go directly from a load to store, skip conversion entirely?
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// TODO: if we go directly from a load to a float instruction, and the value isn't used
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// for anything else, we can skip PPC_FP on a load too.
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if (!strncmp(code[i].opinfo->opname, "lfs", 3))
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{
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fprIsSingle[code[i].fregOut] = true;
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fprIsDuplicated[code[i].fregOut] = true;
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}
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// Paired are still floats, but the top/bottom halves may differ.
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if (code[i].opinfo->type == OPTYPE_PS || code[i].opinfo->type == OPTYPE_LOADPS)
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{
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fprIsSingle[code[i].fregOut] = true;
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fprIsStoreSafe[code[i].fregOut] = true;
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}
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// Careful: changing the float mode in a block breaks this optimization, since
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// a previous float op might have had had FTZ off while the later store has FTZ
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// on. So, discard all information we have.
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if (!strncmp(code[i].opinfo->opname, "mtfs", 4))
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fprIsStoreSafe = BitSet32(0);
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}
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}
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return address;
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@ -53,6 +53,11 @@ struct CodeOp //16B
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BitSet32 fprInXmm;
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// whether an fpr is known to be an actual single-precision value at this point in the block.
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BitSet32 fprIsSingle;
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// whether an fpr is known to have identical top and bottom halves (e.g. due to a single instruction)
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BitSet32 fprIsDuplicated;
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// whether an fpr is the output of a single-precision arithmetic instruction, i.e. whether we can safely
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// skip PPC_FP.
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BitSet32 fprIsStoreSafe;
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};
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struct BlockStats
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