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JIT: update some rather outdated comments
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@ -27,10 +27,9 @@
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using namespace Gen;
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using namespace Gen;
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using namespace PowerPC;
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using namespace PowerPC;
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// Dolphin's PowerPC->x86 JIT dynamic recompiler
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// Dolphin's PowerPC->x86_64 JIT dynamic recompiler
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// (Nearly) all code by ector (hrydgard)
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// Written mostly by ector (hrydgard)
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// Features:
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// Features:
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// * x86 & x64 support, lots of shared code.
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// * Basic block linking
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// * Basic block linking
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// * Fast dispatcher
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// * Fast dispatcher
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@ -50,10 +49,6 @@ using namespace PowerPC;
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// Other considerations
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// Other considerations
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//
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//
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// Many instructions have shorter forms for EAX. However, I believe their performance boost
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// will be as small to be negligible, so I haven't dirtied up the code with that. AMD recommends it in their
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// optimization manuals, though.
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//
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// We support block linking. Reserve space at the exits of every block for a full 5-byte jmp. Save 16-bit offsets
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// We support block linking. Reserve space at the exits of every block for a full 5-byte jmp. Save 16-bit offsets
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// from the starts of each block, marking the exits so that they can be nicely patched at any time.
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// from the starts of each block, marking the exits so that they can be nicely patched at any time.
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//
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//
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@ -88,48 +83,16 @@ using namespace PowerPC;
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CR2-CR4 are non-volatile, rest of CR is volatile -> dropped on blr.
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CR2-CR4 are non-volatile, rest of CR is volatile -> dropped on blr.
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R5-R12 are volatile -> dropped on blr.
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R5-R12 are volatile -> dropped on blr.
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* classic inlining across calls.
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* classic inlining across calls.
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* Track which registers a block clobbers without using, then take advantage of this knowledge
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Low hanging fruit:
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when compiling a block that links to that block.
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stfd -- guaranteed in memory
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* Track more dependencies between instructions, e.g. avoiding PPC_FP code, single/double
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cmpl
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conversion, movddup on non-paired singles, etc where possible.
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mulli
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* Support loads/stores directly from xmm registers in jit_util and the backpatcher; this might
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stfs
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help AMD a lot since gpr/xmm transfers are slower there.
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stwu
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* Smarter register allocation in general; maybe learn to drop values once we know they won't be
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lb/stzx
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used again before being overwritten?
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* More flexible reordering; there's limits to how far we can go because of exception handling
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bcx - optimize!
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and such, but it's currently limited to integer ops only. This can definitely be made better.
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bcctr
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stfs
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psq_st
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addx
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orx
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rlwimix
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fcmpo
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DSP_UpdateARAMDMA
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lfd
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stwu
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cntlzwx
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bcctrx
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WriteBigEData
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TODO
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lha
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srawx
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addic_rc
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addex
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subfcx
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subfex
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fmaddx
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fmulx
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faddx
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fnegx
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frspx
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frsqrtex
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ps_sum0
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ps_muls0
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ps_adds1
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*/
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*/
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void Jit64::Init()
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void Jit64::Init()
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@ -222,10 +222,10 @@ void Jit64::bclrx(UGeckoInstruction inst)
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!(inst.BO_2 & BO_BRANCH_IF_TRUE));
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!(inst.BO_2 & BO_BRANCH_IF_TRUE));
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}
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}
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// This below line can be used to prove that blr "eats flags" in practice.
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// This below line can be used to prove that blr "eats flags" in practice.
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// This observation will let us do a lot of fun observations.
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// This observation could let us do some useful optimizations.
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#ifdef ACID_TEST
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#ifdef ACID_TEST
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AND(32, PPCSTATE(cr), Imm32(~(0xFF000000)));
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AND(32, PPCSTATE(cr), Imm32(~(0xFF000000)));
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#endif
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#endif
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MOV(32, R(RSCRATCH), PPCSTATE_LR);
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MOV(32, R(RSCRATCH), PPCSTATE_LR);
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