piwalker/dolphin
1
0
Fork 0
mirror of https://github.com/dolphin-emu/dolphin.git synced 2025-07-23 22:29:39 -06:00
Code Issues Packages Projects Releases Wiki Activity

Clean up most (99.99%) of the tab/space mismatches in the VideoSoftware project.

Browse Source 
Got rid of trailing spaces that were unnecessary too.

Also update the license header for this project. We don't use SVN anymore.
This commit is contained in:
Lioncash
2013-04-13 23:54:02 -04:00
parent 48927c17d2
commit 7ab0cca645
51 changed files with 4633 additions and 4567 deletions
Download Patch File Download Diff File Expand all files Collapse all files

224
Source/Plugins/Plugin_VideoSoftware/Src/SWPixelEngine.h
View File

@ -12,7 +12,7 @@
// A copy of the GPL 2.0 should have been included with the program.
// If not, see http://www.gnu.org/licenses/
// Official SVN repository and contact information can be found at
// Official Git repository and contact information can be found at
// http://code.google.com/p/dolphin-emu/
#ifndef _PIXELENGINE_H
#define _PIXELENGINE_H
@ -24,20 +24,20 @@ class PointerWrap;
namespace SWPixelEngine
{
// internal hardware addresses
enum
{
PE_ZCONF = 0x000, // Z Config
PE_ALPHACONF = 0x002, // Alpha Config
PE_DSTALPHACONF = 0x004, // Destination Alpha Config
PE_ALPHAMODE = 0x006, // Alpha Mode Config
PE_ALPHAREAD = 0x008, // Alpha Read
PE_CTRL_REGISTER = 0x00a, // Control
PE_TOKEN_REG = 0x00e, // Token
PE_BBOX_LEFT = 0x010, // Flip Left
PE_BBOX_RIGHT = 0x012, // Flip Right
PE_BBOX_TOP = 0x014, // Flip Top
PE_BBOX_BOTTOM = 0x016, // Flip Bottom
// internal hardware addresses
enum
{
PE_ZCONF = 0x000, // Z Config
PE_ALPHACONF = 0x002, // Alpha Config
PE_DSTALPHACONF = 0x004, // Destination Alpha Config
PE_ALPHAMODE = 0x006, // Alpha Mode Config
PE_ALPHAREAD = 0x008, // Alpha Read
PE_CTRL_REGISTER = 0x00a, // Control
PE_TOKEN_REG = 0x00e, // Token
PE_BBOX_LEFT = 0x010, // Flip Left
PE_BBOX_RIGHT = 0x012, // Flip Right
PE_BBOX_TOP = 0x014, // Flip Top
PE_BBOX_BOTTOM = 0x016, // Flip Bottom
// NOTE: Order not verified
// These indicate the number of quads that are being used as input/output for each particular stage
@ -53,98 +53,98 @@ namespace SWPixelEngine
PE_PERF_BLEND_INPUT_H = 0x2a,
PE_PERF_EFB_COPY_CLOCKS_L = 0x2c,
PE_PERF_EFB_COPY_CLOCKS_H = 0x2e,
};
};
union UPEZConfReg
{
u16 Hex;
struct
{
u16 ZCompEnable : 1; // Z Comparator Enable
u16 Function : 3;
u16 ZUpdEnable : 1;
u16 : 11;
};
};
union UPEZConfReg
{
u16 Hex;
struct
{
u16 ZCompEnable : 1; // Z Comparator Enable
u16 Function : 3;
u16 ZUpdEnable : 1;
u16 : 11;
};
};
union UPEAlphaConfReg
{
u16 Hex;
struct
{
u16 BMMath : 1; // GX_BM_BLEND || GX_BM_SUBSTRACT
u16 BMLogic : 1; // GX_BM_LOGIC
u16 Dither : 1;
u16 ColorUpdEnable : 1;
u16 AlphaUpdEnable : 1;
u16 DstFactor : 3;
u16 SrcFactor : 3;
u16 Substract : 1; // Additive mode by default
u16 BlendOperator : 4;
};
};
union UPEAlphaConfReg
{
u16 Hex;
struct
{
u16 BMMath : 1; // GX_BM_BLEND || GX_BM_SUBSTRACT
u16 BMLogic : 1; // GX_BM_LOGIC
u16 Dither : 1;
u16 ColorUpdEnable : 1;
u16 AlphaUpdEnable : 1;
u16 DstFactor : 3;
u16 SrcFactor : 3;
u16 Substract : 1; // Additive mode by default
u16 BlendOperator : 4;
};
};
union UPEDstAlphaConfReg
{
u16 Hex;
struct
{
u16 DstAlpha : 8;
u16 Enable : 1;
u16 : 7;
};
};
union UPEDstAlphaConfReg
{
u16 Hex;
struct
{
u16 DstAlpha : 8;
u16 Enable : 1;
u16 : 7;
};
};
union UPEAlphaModeConfReg
{
u16 Hex;
struct
{
u16 Threshold : 8;
u16 CompareMode : 8;
};
};
union UPEAlphaModeConfReg
{
u16 Hex;
struct
{
u16 Threshold : 8;
u16 CompareMode : 8;
};
};
union UPEAlphaReadReg
{
u16 Hex;
struct
{
u16 ReadMode : 3;
u16 : 13;
};
};
union UPEAlphaReadReg
{
u16 Hex;
struct
{
u16 ReadMode : 3;
u16 : 13;
};
};
union UPECtrlReg
{
struct
{
u16 PETokenEnable : 1;
u16 PEFinishEnable : 1;
u16 PEToken : 1; // write only
u16 PEFinish : 1; // write only
u16 : 12;
};
u16 Hex;
UPECtrlReg() {Hex = 0; }
UPECtrlReg(u16 _hex) {Hex = _hex; }
};
union UPECtrlReg
{
struct
{
u16 PETokenEnable : 1;
u16 PEFinishEnable : 1;
u16 PEToken : 1; // write only
u16 PEFinish : 1; // write only
u16 : 12;
};
u16 Hex;
UPECtrlReg() {Hex = 0; }
UPECtrlReg(u16 _hex) {Hex = _hex; }
};
struct PEReg
{
UPEZConfReg zconf;
UPEAlphaConfReg alphaConf;
UPEDstAlphaConfReg dstAlpha;
UPEAlphaModeConfReg alphaMode;
UPEAlphaReadReg alphaRead;
UPECtrlReg ctrl;
u16 unk0;
u16 token;
struct PEReg
{
UPEZConfReg zconf;
UPEAlphaConfReg alphaConf;
UPEDstAlphaConfReg dstAlpha;
UPEAlphaModeConfReg alphaMode;
UPEAlphaReadReg alphaRead;
UPECtrlReg ctrl;
u16 unk0;
u16 token;
u16 boxLeft;
u16 boxRight;
u16 boxTop;
u16 boxBottom;
u16 boxLeft;
u16 boxRight;
u16 boxTop;
u16 boxBottom;
u16 perfZcompInputZcomplocLo;
u16 perfZcompInputZcomplocHi;
@ -206,24 +206,24 @@ namespace SWPixelEngine
if (++perfBlendInputLo == 0)
perfBlendInputHi++;
}
};
};
extern PEReg pereg;
extern PEReg pereg;
void Init();
void DoState(PointerWrap &p);
void Init();
void DoState(PointerWrap &p);
// Read
void Read16(u16& _uReturnValue, const u32 _iAddress);
// Read
void Read16(u16& _uReturnValue, const u32 _iAddress);
// Write
void Write16(const u16 _iValue, const u32 _iAddress);
void Write32(const u32 _iValue, const u32 _iAddress);
// Write
void Write16(const u16 _iValue, const u32 _iAddress);
void Write32(const u32 _iValue, const u32 _iAddress);
// gfx backend support
void SetToken(const u16 _token, const int _bSetTokenAcknowledge);
void SetFinish(void);
bool AllowIdleSkipping();
// gfx backend support
void SetToken(const u16 _token, const int _bSetTokenAcknowledge);
void SetFinish(void);
bool AllowIdleSkipping();
} // end of namespace SWPixelEngine