mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2025-07-23 06:09:50 -06:00
Clean up most (99.99%) of the tab/space mismatches in the VideoSoftware project.
Got rid of trailing spaces that were unnecessary too. Also update the license header for this project. We don't use SVN anymore.
This commit is contained in:
@ -12,7 +12,7 @@
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// Official Git repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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#ifndef _PIXELENGINE_H
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#define _PIXELENGINE_H
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@ -24,20 +24,20 @@ class PointerWrap;
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namespace SWPixelEngine
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{
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// internal hardware addresses
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enum
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{
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PE_ZCONF = 0x000, // Z Config
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PE_ALPHACONF = 0x002, // Alpha Config
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PE_DSTALPHACONF = 0x004, // Destination Alpha Config
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PE_ALPHAMODE = 0x006, // Alpha Mode Config
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PE_ALPHAREAD = 0x008, // Alpha Read
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PE_CTRL_REGISTER = 0x00a, // Control
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PE_TOKEN_REG = 0x00e, // Token
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PE_BBOX_LEFT = 0x010, // Flip Left
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PE_BBOX_RIGHT = 0x012, // Flip Right
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PE_BBOX_TOP = 0x014, // Flip Top
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PE_BBOX_BOTTOM = 0x016, // Flip Bottom
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// internal hardware addresses
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enum
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{
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PE_ZCONF = 0x000, // Z Config
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PE_ALPHACONF = 0x002, // Alpha Config
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PE_DSTALPHACONF = 0x004, // Destination Alpha Config
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PE_ALPHAMODE = 0x006, // Alpha Mode Config
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PE_ALPHAREAD = 0x008, // Alpha Read
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PE_CTRL_REGISTER = 0x00a, // Control
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PE_TOKEN_REG = 0x00e, // Token
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PE_BBOX_LEFT = 0x010, // Flip Left
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PE_BBOX_RIGHT = 0x012, // Flip Right
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PE_BBOX_TOP = 0x014, // Flip Top
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PE_BBOX_BOTTOM = 0x016, // Flip Bottom
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// NOTE: Order not verified
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// These indicate the number of quads that are being used as input/output for each particular stage
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@ -53,98 +53,98 @@ namespace SWPixelEngine
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PE_PERF_BLEND_INPUT_H = 0x2a,
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PE_PERF_EFB_COPY_CLOCKS_L = 0x2c,
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PE_PERF_EFB_COPY_CLOCKS_H = 0x2e,
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};
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};
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union UPEZConfReg
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{
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u16 Hex;
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struct
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{
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u16 ZCompEnable : 1; // Z Comparator Enable
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u16 Function : 3;
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u16 ZUpdEnable : 1;
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u16 : 11;
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};
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};
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union UPEZConfReg
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{
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u16 Hex;
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struct
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{
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u16 ZCompEnable : 1; // Z Comparator Enable
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u16 Function : 3;
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u16 ZUpdEnable : 1;
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u16 : 11;
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};
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};
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union UPEAlphaConfReg
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{
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u16 Hex;
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struct
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{
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u16 BMMath : 1; // GX_BM_BLEND || GX_BM_SUBSTRACT
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u16 BMLogic : 1; // GX_BM_LOGIC
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u16 Dither : 1;
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u16 ColorUpdEnable : 1;
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u16 AlphaUpdEnable : 1;
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u16 DstFactor : 3;
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u16 SrcFactor : 3;
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u16 Substract : 1; // Additive mode by default
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u16 BlendOperator : 4;
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};
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};
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union UPEAlphaConfReg
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{
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u16 Hex;
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struct
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{
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u16 BMMath : 1; // GX_BM_BLEND || GX_BM_SUBSTRACT
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u16 BMLogic : 1; // GX_BM_LOGIC
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u16 Dither : 1;
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u16 ColorUpdEnable : 1;
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u16 AlphaUpdEnable : 1;
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u16 DstFactor : 3;
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u16 SrcFactor : 3;
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u16 Substract : 1; // Additive mode by default
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u16 BlendOperator : 4;
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};
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};
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union UPEDstAlphaConfReg
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{
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u16 Hex;
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struct
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{
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u16 DstAlpha : 8;
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u16 Enable : 1;
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u16 : 7;
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};
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};
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union UPEDstAlphaConfReg
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{
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u16 Hex;
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struct
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{
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u16 DstAlpha : 8;
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u16 Enable : 1;
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u16 : 7;
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};
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};
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union UPEAlphaModeConfReg
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{
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u16 Hex;
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struct
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{
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u16 Threshold : 8;
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u16 CompareMode : 8;
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};
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};
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union UPEAlphaModeConfReg
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{
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u16 Hex;
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struct
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{
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u16 Threshold : 8;
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u16 CompareMode : 8;
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};
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};
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union UPEAlphaReadReg
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{
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u16 Hex;
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struct
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{
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u16 ReadMode : 3;
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u16 : 13;
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};
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};
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union UPEAlphaReadReg
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{
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u16 Hex;
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struct
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{
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u16 ReadMode : 3;
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u16 : 13;
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};
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};
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union UPECtrlReg
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{
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struct
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{
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u16 PETokenEnable : 1;
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u16 PEFinishEnable : 1;
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u16 PEToken : 1; // write only
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u16 PEFinish : 1; // write only
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u16 : 12;
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};
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u16 Hex;
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UPECtrlReg() {Hex = 0; }
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UPECtrlReg(u16 _hex) {Hex = _hex; }
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};
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union UPECtrlReg
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{
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struct
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{
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u16 PETokenEnable : 1;
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u16 PEFinishEnable : 1;
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u16 PEToken : 1; // write only
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u16 PEFinish : 1; // write only
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u16 : 12;
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};
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u16 Hex;
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UPECtrlReg() {Hex = 0; }
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UPECtrlReg(u16 _hex) {Hex = _hex; }
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};
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struct PEReg
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{
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UPEZConfReg zconf;
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UPEAlphaConfReg alphaConf;
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UPEDstAlphaConfReg dstAlpha;
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UPEAlphaModeConfReg alphaMode;
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UPEAlphaReadReg alphaRead;
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UPECtrlReg ctrl;
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u16 unk0;
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u16 token;
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struct PEReg
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{
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UPEZConfReg zconf;
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UPEAlphaConfReg alphaConf;
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UPEDstAlphaConfReg dstAlpha;
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UPEAlphaModeConfReg alphaMode;
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UPEAlphaReadReg alphaRead;
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UPECtrlReg ctrl;
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u16 unk0;
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u16 token;
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u16 boxLeft;
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u16 boxRight;
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u16 boxTop;
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u16 boxBottom;
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u16 boxLeft;
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u16 boxRight;
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u16 boxTop;
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u16 boxBottom;
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u16 perfZcompInputZcomplocLo;
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u16 perfZcompInputZcomplocHi;
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@ -206,24 +206,24 @@ namespace SWPixelEngine
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if (++perfBlendInputLo == 0)
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perfBlendInputHi++;
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}
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};
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};
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extern PEReg pereg;
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extern PEReg pereg;
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void Init();
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void DoState(PointerWrap &p);
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void Init();
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void DoState(PointerWrap &p);
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// Read
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void Read16(u16& _uReturnValue, const u32 _iAddress);
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// Read
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void Read16(u16& _uReturnValue, const u32 _iAddress);
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// Write
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void Write16(const u16 _iValue, const u32 _iAddress);
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void Write32(const u32 _iValue, const u32 _iAddress);
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// Write
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void Write16(const u16 _iValue, const u32 _iAddress);
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void Write32(const u32 _iValue, const u32 _iAddress);
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// gfx backend support
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void SetToken(const u16 _token, const int _bSetTokenAcknowledge);
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void SetFinish(void);
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bool AllowIdleSkipping();
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// gfx backend support
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void SetToken(const u16 _token, const int _bSetTokenAcknowledge);
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void SetFinish(void);
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bool AllowIdleSkipping();
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} // end of namespace SWPixelEngine
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