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Merge pull request #249 from SeannyM/master
(Rebase) Fixes two bugs in the ARM JIT core.
This commit is contained in:
@ -401,7 +401,7 @@ void ARMXEmitter::SetJumpTarget(FixupBranch const &branch)
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_dbg_assert_msg_(DYNA_REC, distance > -0x2000000 && distance <= 0x2000000,
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_dbg_assert_msg_(DYNA_REC, distance > -0x2000000 && distance <= 0x2000000,
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"SetJumpTarget out of range (%p calls %p)", code, branch.ptr);
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"SetJumpTarget out of range (%p calls %p)", code, branch.ptr);
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u32 instr = (u32)(branch.condition | ((distance >> 2) & 0x00FFFFFF));
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u32 instr = (u32)(branch.condition | ((distance >> 2) & 0x00FFFFFF));
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instr |= branch.type ? /* B */ 0x0A000000 : /* BL */ 0x0B000000;
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instr |= (0 == branch.type) ? /* B */ 0x0A000000 : /* BL */ 0x0B000000;
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*(u32*)branch.ptr = instr;
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*(u32*)branch.ptr = instr;
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}
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}
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void ARMXEmitter::B(const void *fnptr)
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void ARMXEmitter::B(const void *fnptr)
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@ -19,7 +19,7 @@
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void JitArm::UnsafeStoreFromReg(ARMReg dest, ARMReg value, int accessSize, s32 offset)
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void JitArm::UnsafeStoreFromReg(ARMReg dest, ARMReg value, int accessSize, s32 offset)
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{
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{
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// All this gets replaced on backpatch
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// All this gets replaced on backpatch
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Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
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Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
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BIC(dest, dest, mask); // 1
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BIC(dest, dest, mask); // 1
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MOVI2R(R14, (u32)Memory::base, false); // 2-3
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MOVI2R(R14, (u32)Memory::base, false); // 2-3
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ADD(dest, dest, R14); // 4
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ADD(dest, dest, R14); // 4
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@ -212,7 +212,7 @@ void JitArm::UnsafeLoadToReg(ARMReg dest, ARMReg addr, int accessSize, s32 offse
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ADD(addr, addr, rA); // - 1
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ADD(addr, addr, rA); // - 1
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// All this gets replaced on backpatch
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// All this gets replaced on backpatch
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Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
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Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
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BIC(addr, addr, mask); // 1
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BIC(addr, addr, mask); // 1
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MOVI2R(rA, (u32)Memory::base, false); // 2-3
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MOVI2R(rA, (u32)Memory::base, false); // 2-3
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ADD(addr, addr, rA); // 4
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ADD(addr, addr, rA); // 4
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@ -461,7 +461,7 @@ void JitArm::lmw(UGeckoInstruction inst)
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MOVI2R(rA, inst.SIMM_16);
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MOVI2R(rA, inst.SIMM_16);
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if (a)
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if (a)
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ADD(rA, rA, gpr.R(a));
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ADD(rA, rA, gpr.R(a));
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Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
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Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
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BIC(rA, rA, mask); // 3
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BIC(rA, rA, mask); // 3
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MOVI2R(rB, (u32)Memory::base, false); // 4-5
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MOVI2R(rB, (u32)Memory::base, false); // 4-5
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ADD(rA, rA, rB); // 6
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ADD(rA, rA, rB); // 6
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@ -493,7 +493,7 @@ void JitArm::stmw(UGeckoInstruction inst)
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MOVI2R(rA, inst.SIMM_16);
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MOVI2R(rA, inst.SIMM_16);
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if (a)
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if (a)
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ADD(rA, rA, gpr.R(a));
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ADD(rA, rA, gpr.R(a));
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Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
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Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
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BIC(rA, rA, mask); // 3
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BIC(rA, rA, mask); // 3
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MOVI2R(rB, (u32)Memory::base, false); // 4-5
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MOVI2R(rB, (u32)Memory::base, false); // 4-5
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ADD(rA, rA, rB); // 6
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ADD(rA, rA, rB); // 6
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@ -129,7 +129,7 @@ void JitArm::lfXX(UGeckoInstruction inst)
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if (Core::g_CoreStartupParameter.bFastmem)
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if (Core::g_CoreStartupParameter.bFastmem)
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{
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{
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Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
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Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
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BIC(rB, rB, mask); // 1
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BIC(rB, rB, mask); // 1
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MOVI2R(rA, (u32)Memory::base, false); // 2-3
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MOVI2R(rA, (u32)Memory::base, false); // 2-3
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ADD(rB, rB, rA); // 4
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ADD(rB, rB, rA); // 4
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@ -291,7 +291,7 @@ void JitArm::stfXX(UGeckoInstruction inst)
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}
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}
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if (Core::g_CoreStartupParameter.bFastmem)
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if (Core::g_CoreStartupParameter.bFastmem)
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{
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{
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Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
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Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
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BIC(rB, rB, mask); // 1
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BIC(rB, rB, mask); // 1
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MOVI2R(rA, (u32)Memory::base, false); // 2-3
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MOVI2R(rA, (u32)Memory::base, false); // 2-3
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ADD(rB, rB, rA); // 4
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ADD(rB, rB, rA); // 4
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