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https://github.com/dolphin-emu/dolphin.git
synced 2025-07-24 14:49:42 -06:00
x64Emitter: Adjust position of reference and pointer indicators
Matches the coding style.
This commit is contained in:
Lioncash
@ -145,11 +145,11 @@ struct OpArg
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return operandReg == b.operandReg && scale == b.scale && offsetOrBaseReg == b.offsetOrBaseReg &&
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indexReg == b.indexReg && offset == b.offset;
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}
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void WriteREX(XEmitter *emit, int opBits, int bits, int customOp = -1) const;
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void WriteREX(XEmitter* emit, int opBits, int bits, int customOp = -1) const;
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void WriteVEX(XEmitter* emit, X64Reg regOp1, X64Reg regOp2, int L, int pp, int mmmmm, int W = 0) const;
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void WriteRest(XEmitter *emit, int extraBytes=0, X64Reg operandReg=INVALID_REG, bool warn_64bit_offset = true) const;
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void WriteFloatModRM(XEmitter *emit, FloatOp op);
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void WriteSingleByteOp(XEmitter *emit, u8 op, X64Reg operandReg, int bits);
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void WriteRest(XEmitter* emit, int extraBytes=0, X64Reg operandReg=INVALID_REG, bool warn_64bit_offset = true) const;
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void WriteFloatModRM(XEmitter* emit, FloatOp op);
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void WriteSingleByteOp(XEmitter* emit, u8 op, X64Reg operandReg, int bits);
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u64 Imm64() const { _dbg_assert_(DYNA_REC, scale == SCALE_IMM64); return (u64)offset; }
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u32 Imm32() const { _dbg_assert_(DYNA_REC, scale == SCALE_IMM32); return (u32)offset; }
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@ -161,7 +161,7 @@ struct OpArg
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s16 SImm16() const { _dbg_assert_(DYNA_REC, scale == SCALE_IMM16); return (s16)offset; }
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s8 SImm8() const { _dbg_assert_(DYNA_REC, scale == SCALE_IMM8); return (s8)offset; }
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void WriteNormalOp(XEmitter *emit, bool toRM, NormalOp op, const OpArg &operand, int bits) const;
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void WriteNormalOp(XEmitter* emit, bool toRM, NormalOp op, const OpArg& operand, int bits) const;
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bool IsImm() const {return scale == SCALE_IMM8 || scale == SCALE_IMM16 || scale == SCALE_IMM32 || scale == SCALE_IMM64;}
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bool IsSimpleReg() const {return scale == SCALE_NONE;}
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bool IsSimpleReg(X64Reg reg) const
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@ -171,7 +171,7 @@ struct OpArg
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return GetSimpleReg() == reg;
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}
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bool CanDoOpWith(const OpArg &other) const
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bool CanDoOpWith(const OpArg& other) const
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{
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if (IsSimpleReg()) return true;
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if (!IsSimpleReg() && !other.IsSimpleReg() && !other.IsImm()) return false;
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@ -214,7 +214,7 @@ private:
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};
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template <typename T>
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inline OpArg M(const T *ptr) {return OpArg((u64)(const void *)ptr, (int)SCALE_RIP);}
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inline OpArg M(const T* ptr) {return OpArg((u64)(const void*)ptr, (int)SCALE_RIP);}
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inline OpArg R(X64Reg value) {return OpArg(0, SCALE_NONE, value);}
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inline OpArg MatR(X64Reg value) {return OpArg(0, SCALE_ATREG, value);}
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@ -275,7 +275,7 @@ inline u32 PtrOffset(const void* ptr, const void* base)
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struct FixupBranch
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{
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u8 *ptr;
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u8* ptr;
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int type; //0 = 8bit 1 = 32bit
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};
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@ -297,7 +297,7 @@ class XEmitter
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{
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friend struct OpArg; // for Write8 etc
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private:
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u8 *code;
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u8* code;
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bool flags_locked;
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void CheckFlags();
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@ -307,8 +307,8 @@ private:
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void WriteSimple2Byte(int bits, u8 byte1, u8 byte2, X64Reg reg);
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void WriteMulDivType(int bits, OpArg src, int ext);
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void WriteBitSearchType(int bits, X64Reg dest, OpArg src, u8 byte2, bool rep = false);
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void WriteShift(int bits, OpArg dest, OpArg &shift, int ext);
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void WriteBitTest(int bits, OpArg &dest, OpArg &index, int ext);
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void WriteShift(int bits, OpArg dest, OpArg& shift, int ext);
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void WriteBitTest(int bits, OpArg& dest, OpArg& index, int ext);
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void WriteMXCSR(OpArg arg, int ext);
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void WriteSSEOp(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes = 0);
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void WriteSSSE3Op(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes = 0);
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@ -323,7 +323,7 @@ private:
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void WriteBMI2Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
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void WriteMOVBE(int bits, u8 op, X64Reg regOp, OpArg arg);
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void WriteFloatLoadStore(int bits, FloatOp op, FloatOp op_80b, OpArg arg);
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void WriteNormalOp(int bits, NormalOp op, const OpArg &a1, const OpArg &a2);
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void WriteNormalOp(int bits, NormalOp op, const OpArg& a1, const OpArg& a2);
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void ABI_CalculateFrameSize(BitSet32 mask, size_t rsp_alignment, size_t needed_frame_size, size_t* shadowp, size_t* subtractionp, size_t* xmm_offsetp);
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@ -335,19 +335,19 @@ protected:
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public:
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XEmitter() { code = nullptr; flags_locked = false; }
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XEmitter(u8 *code_ptr) { code = code_ptr; flags_locked = false; }
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XEmitter(u8* code_ptr) { code = code_ptr; flags_locked = false; }
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virtual ~XEmitter() {}
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void WriteModRM(int mod, int rm, int reg);
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void WriteSIB(int scale, int index, int base);
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void SetCodePtr(u8 *ptr);
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void SetCodePtr(u8* ptr);
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void ReserveCodeSpace(int bytes);
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const u8 *AlignCode4();
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const u8 *AlignCode16();
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const u8 *AlignCodePage();
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const u8 *GetCodePtr() const;
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u8 *GetWritableCodePtr();
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const u8* AlignCode4();
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const u8* AlignCode16();
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const u8* AlignCodePage();
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const u8* GetCodePtr() const;
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u8* GetWritableCodePtr();
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void LockFlags() { flags_locked = true; }
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void UnlockFlags() { flags_locked = false; }
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@ -380,8 +380,8 @@ public:
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// Stack control
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void PUSH(X64Reg reg);
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void POP(X64Reg reg);
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void PUSH(int bits, const OpArg ®);
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void POP(int bits, const OpArg ®);
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void PUSH(int bits, const OpArg& reg);
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void POP(int bits, const OpArg& reg);
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void PUSHF();
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void POPF();
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@ -391,20 +391,20 @@ public:
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void UD2();
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FixupBranch J(bool force5bytes = false);
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void JMP(const u8 * addr, bool force5Bytes = false);
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void JMPptr(const OpArg &arg);
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void JMP(const u8* addr, bool force5Bytes = false);
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void JMPptr(const OpArg& arg);
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void JMPself(); //infinite loop!
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#ifdef CALL
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#undef CALL
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#endif
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void CALL(const void *fnptr);
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void CALL(const void* fnptr);
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void CALLptr(OpArg arg);
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FixupBranch J_CC(CCFlags conditionCode, bool force5bytes = false);
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//void J_CC(CCFlags conditionCode, JumpTarget target);
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void J_CC(CCFlags conditionCode, const u8* addr);
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void SetJumpTarget(const FixupBranch &branch);
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void SetJumpTarget(const FixupBranch& branch);
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void SETcc(CCFlags flag, OpArg dest);
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// Note: CMOV brings small if any benefit on current CPUs.
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@ -473,24 +473,24 @@ public:
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// Integer arithmetic
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void NEG (int bits, OpArg src);
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void ADD (int bits, const OpArg &a1, const OpArg &a2);
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void ADC (int bits, const OpArg &a1, const OpArg &a2);
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void SUB (int bits, const OpArg &a1, const OpArg &a2);
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void SBB (int bits, const OpArg &a1, const OpArg &a2);
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void AND (int bits, const OpArg &a1, const OpArg &a2);
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void CMP (int bits, const OpArg &a1, const OpArg &a2);
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void ADD (int bits, const OpArg& a1, const OpArg& a2);
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void ADC (int bits, const OpArg& a1, const OpArg& a2);
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void SUB (int bits, const OpArg& a1, const OpArg& a2);
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void SBB (int bits, const OpArg& a1, const OpArg& a2);
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void AND (int bits, const OpArg& a1, const OpArg& a2);
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void CMP (int bits, const OpArg& a1, const OpArg& a2);
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// Bit operations
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void NOT (int bits, OpArg src);
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void OR (int bits, const OpArg &a1, const OpArg &a2);
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void XOR (int bits, const OpArg &a1, const OpArg &a2);
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void MOV (int bits, const OpArg &a1, const OpArg &a2);
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void TEST(int bits, const OpArg &a1, const OpArg &a2);
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void OR (int bits, const OpArg& a1, const OpArg& a2);
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void XOR (int bits, const OpArg& a1, const OpArg& a2);
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void MOV (int bits, const OpArg& a1, const OpArg& a2);
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void TEST(int bits, const OpArg& a1, const OpArg& a2);
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void CMP_or_TEST(int bits, const OpArg &a1, const OpArg &a2);
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void CMP_or_TEST(int bits, const OpArg& a1, const OpArg& a2);
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// Are these useful at all? Consider removing.
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void XCHG(int bits, const OpArg &a1, const OpArg &a2);
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void XCHG(int bits, const OpArg& a1, const OpArg& a2);
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void XCHG_AHAL();
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// Byte swapping (32 and 64-bit only).
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@ -661,9 +661,9 @@ public:
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// one is the xmm reg.
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// ie: "MOVD_xmm(eax, R(xmm1))" generates incorrect code (movd xmm0, rcx)
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// use "MOVD_xmm(R(eax), xmm1)" instead.
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void MOVD_xmm(X64Reg dest, const OpArg &arg);
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void MOVD_xmm(X64Reg dest, const OpArg& arg);
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void MOVQ_xmm(X64Reg dest, OpArg arg);
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void MOVD_xmm(const OpArg &arg, X64Reg src);
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void MOVD_xmm(const OpArg& arg, X64Reg src);
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void MOVQ_xmm(OpArg arg, X64Reg src);
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// SSE/SSE2: Generates a mask from the high bits of the components of the packed register in question.
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@ -701,10 +701,10 @@ public:
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void PACKUSDW(X64Reg dest, OpArg arg);
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void PACKUSWB(X64Reg dest, OpArg arg);
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void PUNPCKLBW(X64Reg dest, const OpArg &arg);
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void PUNPCKLWD(X64Reg dest, const OpArg &arg);
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void PUNPCKLDQ(X64Reg dest, const OpArg &arg);
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void PUNPCKLQDQ(X64Reg dest, const OpArg &arg);
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void PUNPCKLBW(X64Reg dest, const OpArg& arg);
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void PUNPCKLWD(X64Reg dest, const OpArg& arg);
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void PUNPCKLDQ(X64Reg dest, const OpArg& arg);
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void PUNPCKLQDQ(X64Reg dest, const OpArg& arg);
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void PTEST(X64Reg dest, OpArg arg);
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void PAND(X64Reg dest, OpArg arg);
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@ -908,27 +908,27 @@ public:
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// Utility functions
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// The difference between this and CALL is that this aligns the stack
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// where appropriate.
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void ABI_CallFunction(const void *func);
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void ABI_CallFunction(const void* func);
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void ABI_CallFunctionC16(const void *func, u16 param1);
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void ABI_CallFunctionCC16(const void *func, u32 param1, u16 param2);
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void ABI_CallFunctionC16(const void* func, u16 param1);
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void ABI_CallFunctionCC16(const void* func, u32 param1, u16 param2);
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// These only support u32 parameters, but that's enough for a lot of uses.
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// These will destroy the 1 or 2 first "parameter regs".
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void ABI_CallFunctionC(const void *func, u32 param1);
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void ABI_CallFunctionCC(const void *func, u32 param1, u32 param2);
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void ABI_CallFunctionCP(const void *func, u32 param1, void *param2);
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void ABI_CallFunctionCCC(const void *func, u32 param1, u32 param2, u32 param3);
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void ABI_CallFunctionCCP(const void *func, u32 param1, u32 param2, void *param3);
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void ABI_CallFunctionCCCP(const void *func, u32 param1, u32 param2,u32 param3, void *param4);
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void ABI_CallFunctionPC(const void *func, void *param1, u32 param2);
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void ABI_CallFunctionPPC(const void *func, void *param1, void *param2, u32 param3);
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void ABI_CallFunctionAC(int bits, const void *func, const OpArg &arg1, u32 param2);
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void ABI_CallFunctionA(int bits, const void *func, const OpArg &arg1);
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void ABI_CallFunctionC(const void* func, u32 param1);
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void ABI_CallFunctionCC(const void* func, u32 param1, u32 param2);
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void ABI_CallFunctionCP(const void* func, u32 param1, void* param2);
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void ABI_CallFunctionCCC(const void* func, u32 param1, u32 param2, u32 param3);
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void ABI_CallFunctionCCP(const void* func, u32 param1, u32 param2, void* param3);
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void ABI_CallFunctionCCCP(const void* func, u32 param1, u32 param2,u32 param3, void* param4);
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void ABI_CallFunctionPC(const void* func, void* param1, u32 param2);
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void ABI_CallFunctionPPC(const void* func, void* param1, void* param2, u32 param3);
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void ABI_CallFunctionAC(int bits, const void* func, const OpArg& arg1, u32 param2);
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void ABI_CallFunctionA(int bits, const void* func, const OpArg& arg1);
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// Pass a register as a parameter.
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void ABI_CallFunctionR(const void *func, X64Reg reg1);
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void ABI_CallFunctionRR(const void *func, X64Reg reg1, X64Reg reg2);
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void ABI_CallFunctionR(const void* func, X64Reg reg1);
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void ABI_CallFunctionRR(const void* func, X64Reg reg1, X64Reg reg2);
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// Helper method for the above, or can be used separately.
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void MOVTwo(int bits, Gen::X64Reg dst1, Gen::X64Reg src1, s32 offset, Gen::X64Reg dst2, Gen::X64Reg src2);
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