piwalker/dolphin
1
0
Fork 0
mirror of https://github.com/dolphin-emu/dolphin.git synced 2025-07-23 06:09:50 -06:00
Code Issues Packages Projects Releases Wiki Activity

DSPLLE: Handle cr, sr, and prod.h masking

Browse Source
This commit is contained in:
Pokechu22
2021-08-14 17:26:40 -07:00
parent 3d6ff60a96
commit 858d0675b9
4 changed files with 124 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Source/Core/Core/DSP/DSPCore.h
View File

@ -200,7 +200,7 @@ enum : u16
SR_LOGIC_ZERO = 0x0040,
SR_OVERFLOW_STICKY =
0x0080, // Set at the same time as 0x2 (under same conditions) - but not cleared the same
SR_100 = 0x0100, // Unknown
SR_100 = 0x0100, // Unknown, always reads back as 0
SR_INT_ENABLE = 0x0200, // Not 100% sure but duddie says so. This should replace the hack, if so.
SR_400 = 0x0400, // Unknown
SR_EXT_INT_ENABLE = 0x0800, // Appears in zelda - seems to disable external interrupts

9
Source/Core/Core/DSP/Interpreter/DSPInterpreter.cpp
View File

@ -687,7 +687,7 @@ void Interpreter::OpWriteRegister(int reg_, u16 val)
switch (reg)
{
// 8-bit sign extended registers. Should look at prod.h too...
// 8-bit sign extended registers.
case DSP_REG_ACH0:
case DSP_REG_ACH1:
// sign extend from the bottom 8 bits.
@ -720,10 +720,10 @@ void Interpreter::OpWriteRegister(int reg_, u16 val)
state.r.wr[reg - DSP_REG_WR0] = val;
break;
case DSP_REG_CR:
state.r.cr = val;
state.r.cr = val & 0x00ff;
break;
case DSP_REG_SR:
state.r.sr = val;
state.r.sr = val & ~SR_100;
break;
case DSP_REG_PRODL:
state.r.prod.l = val;
@ -732,7 +732,8 @@ void Interpreter::OpWriteRegister(int reg_, u16 val)
state.r.prod.m = val;
break;
case DSP_REG_PRODH:
state.r.prod.h = val;
// Unlike ac0.h and ac1.h, prod.h is not sign-extended
state.r.prod.h = val & 0x00ff;
break;
case DSP_REG_PRODM2:
state.r.prod.m2 = val;

53
Source/Core/Core/DSP/Jit/x64/DSPJitRegCache.cpp
View File

@ -751,6 +751,7 @@ void DSPJitRegCache::PutReg(int reg, bool dirty)
else if (oparg.IsImm())
{
// TODO: Immediates?
ASSERT(false);
}
else
{
@ -772,6 +773,58 @@ void DSPJitRegCache::PutReg(int reg, bool dirty)
m_emitter.SAR(64, oparg, Imm8(64 - 40));
}
break;
case DSP_REG_CR:
case DSP_REG_PRODH:
if (dirty)
{
if (oparg.IsSimpleReg())
{
// register is already shifted correctly
// (if at all)
// Zero extend from the bottom 8 bits.
m_emitter.MOVZX(16, 8, oparg.GetSimpleReg(), oparg);
}
else if (oparg.IsImm())
{
// TODO: Immediates?
ASSERT(false);
}
else
{
// This works on the memory, so use reg instead
// of real_reg, since it has the right loc
X64Reg tmp = GetFreeXReg();
// Zero extend from the bottom 8 bits.
m_emitter.MOVZX(16, 8, tmp, m_regs[reg].loc);
m_emitter.MOV(16, m_regs[reg].loc, R(tmp));
PutXReg(tmp);
}
}
break;
case DSP_REG_SR:
if (dirty)
{
if (oparg.IsSimpleReg())
{
// register is already shifted correctly
// (if at all)
// Clear SR_100, which always reads back as 0
m_emitter.AND(16, R(oparg.GetSimpleReg()), Gen::Imm16(~SR_100));
}
else if (oparg.IsImm())
{
// TODO: Immediates?
ASSERT(false);
}
else
{
// Clear SR_100, which always reads back as 0
m_emitter.AND(16, m_regs[reg].loc, Gen::Imm16(~SR_100));
}
}
break;
default:
break;
}