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First DSPSpy results. cleanup and commenting.

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git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2999 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
hrydgard
2009-04-18 19:26:06 +00:00
parent 5f0ac1db68
commit 8716a58ae3
6 changed files with 80 additions and 92 deletions
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16
Source/Core/DSPCore/Src/DSPInterpreter.cpp
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@ -1444,7 +1444,7 @@ void sbset(const UDSPInstruction& opc)
// mode to explore for the moment:
// SET40
// CLR15
// M0
// M0
// Gonna be fun to explore all 8 possible combinations .. ugh.
void srbith(const UDSPInstruction& opc)
{
@ -1453,37 +1453,37 @@ void srbith(const UDSPInstruction& opc)
// M0 seems to be the default. M2 is used in functions in Zelda
// and then reset with M0 at the end. Like the other bits here, it's
// done around loops with lots of multiplications.
// I've confirmed with DSPSpy that they flip this bit.
case 0xa: // M2
//ERROR_LOG(DSPLLE, "M2");
g_dsp.r[DSP_REG_SR] &= ~SR_MUL_MODIFY;
break;
// FIXME: Both of these appear in the beginning of the Wind Waker
case 0xb: // M0
//ERROR_LOG(DSPLLE, "M0");
g_dsp.r[DSP_REG_SR] |= SR_MUL_MODIFY;
break;
// 15-bit precision? clamping? no idea :(
// CLR15 seems to be the default.
// nakee: It seems to come around mul operation, and it explains what sets the mul bit. But if so why not set/clr14?
case 0xc: // CLR15
g_dsp.r[DSP_REG_SR] |= SR_MUL_MODIFY;
g_dsp.r[DSP_REG_SR] &= ~SR_TOP_BIT_UNK;
//ERROR_LOG(DSPLLE, "CLR15");
break;
case 0xd: // SET15
g_dsp.r[DSP_REG_SR] &= ~SR_MUL_MODIFY;
g_dsp.r[DSP_REG_SR] |= SR_TOP_BIT_UNK;
//ERROR_LOG(DSPLLE, "SET15");
break;
// 40-bit precision? clamping? no idea :(
// 40 seems to be the default.
case 0xe: // SET40 (really, clear SR's 0x4000?) something about "set 40-bit operation"?
g_dsp.r[DSP_REG_SR] &= ~(1 << 14);
//g_dsp.r[DSP_REG_SR] &= ~(1 << 14);
//ERROR_LOG(DSPLLE, "SET40");
break;
case 0xf: // SET16 (really, set SR's 0x4000?) something about "set 16-bit operation"?
// that doesnt happen on a real console << what does this comment mean?
g_dsp.r[DSP_REG_SR] |= (1 << 14);
//g_dsp.r[DSP_REG_SR] |= (1 << 14);
//ERROR_LOG(DSPLLE, "SET16");
break;

1
Source/Core/DSPCore/Src/gdsp_registers.h
View File

@ -100,6 +100,7 @@
#define SR_LOGIC_ZERO 0x0040 // ?? duddie's doc sometimes say & 1<<6 (0x40), sometimes 1<<14 (0x4000), while we have 0x20 .. eh
#define SR_INT_ENABLE 0x0200 // Not 100% sure but duddie says so. This should replace the hack, if so.
#define SR_MUL_MODIFY 0x2000 // 1 = normal. 0 = x2
#define SR_TOP_BIT_UNK 0x8000 // 1 = normal. 0 = x2
void dsp_reg_store_stack(u8 stack_reg, u16 val);
u16 dsp_reg_load_stack(u8 stack_reg);