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PixelEngine: Convert to BitField and enum class
This commit is contained in:
Pokechu22
@ -5,6 +5,7 @@
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#include <mutex>
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#include "Common/BitField.h"
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#include "Common/ChunkFile.h"
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#include "Common/CommonTypes.h"
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#include "Common/Logging/Log.h"
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@ -24,70 +25,115 @@
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namespace PixelEngine
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{
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// Note: These enums are (assumed to be) identical to the one in BPMemory, but the base type is set
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// to u16 instead of u32 for BitField
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enum class CompareMode : u16
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{
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Never = 0,
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Less = 1,
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Equal = 2,
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LEqual = 3,
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Greater = 4,
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NEqual = 5,
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GEqual = 6,
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Always = 7
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};
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union UPEZConfReg
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{
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u16 Hex;
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struct
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{
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u16 ZCompEnable : 1; // Z Comparator Enable
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u16 Function : 3;
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u16 ZUpdEnable : 1;
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u16 : 11;
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};
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u16 hex;
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BitField<0, 1, bool, u16> z_comparator_enable;
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BitField<1, 3, CompareMode, u16> function;
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BitField<4, 1, bool, u16> z_update_enable;
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};
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enum class SrcBlendFactor : u16
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{
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Zero = 0,
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One = 1,
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DstClr = 2,
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InvDstClr = 3,
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SrcAlpha = 4,
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InvSrcAlpha = 5,
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DstAlpha = 6,
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InvDstAlpha = 7
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};
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enum class DstBlendFactor : u16
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{
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Zero = 0,
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One = 1,
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SrcClr = 2,
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InvSrcClr = 3,
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SrcAlpha = 4,
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InvSrcAlpha = 5,
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DstAlpha = 6,
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InvDstAlpha = 7
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};
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enum class LogicOp : u16
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{
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Clear = 0,
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And = 1,
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AndReverse = 2,
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Copy = 3,
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AndInverted = 4,
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NoOp = 5,
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Xor = 6,
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Or = 7,
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Nor = 8,
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Equiv = 9,
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Invert = 10,
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OrReverse = 11,
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CopyInverted = 12,
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OrInverted = 13,
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Nand = 14,
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Set = 15
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};
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union UPEAlphaConfReg
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{
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u16 Hex;
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struct
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{
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u16 BMMath : 1; // GX_BM_BLEND || GX_BM_SUBSTRACT
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u16 BMLogic : 1; // GX_BM_LOGIC
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u16 Dither : 1;
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u16 ColorUpdEnable : 1;
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u16 AlphaUpdEnable : 1;
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u16 DstFactor : 3;
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u16 SrcFactor : 3;
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u16 Substract : 1; // Additive mode by default
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u16 BlendOperator : 4;
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};
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u16 hex;
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BitField<0, 1, bool, u16> blend; // Set for GX_BM_BLEND or GX_BM_SUBTRACT
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BitField<1, 1, bool, u16> logic; // Set for GX_BM_LOGIC
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BitField<2, 1, bool, u16> dither;
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BitField<3, 1, bool, u16> color_update_enable;
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BitField<4, 1, bool, u16> alpha_update_enable;
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BitField<5, 3, DstBlendFactor, u16> dst_factor;
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BitField<8, 3, SrcBlendFactor, u16> src_factor;
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BitField<11, 1, bool, u16> subtract; // Set for GX_BM_SUBTRACT
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BitField<12, 4, LogicOp, u16> logic_op;
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};
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union UPEDstAlphaConfReg
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{
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u16 Hex;
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struct
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{
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u16 DstAlpha : 8;
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u16 Enable : 1;
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u16 : 7;
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};
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u16 hex;
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BitField<0, 8, u8, u16> alpha;
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BitField<8, 1, bool, u16> enable;
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};
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union UPEAlphaModeConfReg
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{
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u16 Hex;
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struct
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{
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u16 Threshold : 8;
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u16 CompareMode : 8;
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};
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u16 hex;
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BitField<0, 8, u8, u16> threshold;
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// Yagcd and libogc use 8 bits for this, but the enum only needs 3
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BitField<8, 3, CompareMode, u16> compare_mode;
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};
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union UPEAlphaReadReg
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{
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u16 hex;
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BitField<0, 2, AlphaReadMode, u16> read_mode;
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};
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// fifo Control Register
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union UPECtrlReg
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{
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struct
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{
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u16 PETokenEnable : 1;
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u16 PEFinishEnable : 1;
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u16 PEToken : 1; // write only
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u16 PEFinish : 1; // write only
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u16 : 12;
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};
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u16 Hex;
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UPECtrlReg() { Hex = 0; }
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UPECtrlReg(u16 _hex) { Hex = _hex; }
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u16 hex;
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BitField<0, 1, bool, u16> pe_token_enable;
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BitField<1, 1, bool, u16> pe_finish_enable;
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BitField<2, 1, bool, u16> pe_token; // Write only
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BitField<3, 1, bool, u16> pe_finish; // Write only
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};
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// STATE_TO_SAVE
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@ -140,12 +186,12 @@ static void SetTokenFinish_OnMainThread(u64 userdata, s64 cyclesLate);
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void Init()
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{
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m_Control.Hex = 0;
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m_ZConf.Hex = 0;
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m_AlphaConf.Hex = 0;
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m_DstAlphaConf.Hex = 0;
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m_AlphaModeConf.Hex = 0;
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m_AlphaRead.Hex = 0;
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m_Control.hex = 0;
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m_ZConf.hex = 0;
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m_AlphaConf.hex = 0;
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m_DstAlphaConf.hex = 0;
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m_AlphaModeConf.hex = 0;
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m_AlphaRead.hex = 0;
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s_token = 0;
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s_token_pending = 0;
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@ -168,11 +214,11 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
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u32 addr;
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u16* ptr;
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} directly_mapped_vars[] = {
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{PE_ZCONF, &m_ZConf.Hex},
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{PE_ALPHACONF, &m_AlphaConf.Hex},
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{PE_DSTALPHACONF, &m_DstAlphaConf.Hex},
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{PE_ALPHAMODE, &m_AlphaModeConf.Hex},
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{PE_ALPHAREAD, &m_AlphaRead.Hex},
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{PE_ZCONF, &m_ZConf.hex},
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{PE_ALPHACONF, &m_AlphaConf.hex},
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{PE_DSTALPHACONF, &m_DstAlphaConf.hex},
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{PE_ALPHAMODE, &m_AlphaModeConf.hex},
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{PE_ALPHAREAD, &m_AlphaRead.hex},
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};
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for (auto& mapped_var : directly_mapped_vars)
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{
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@ -207,20 +253,20 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
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}
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// Control register
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mmio->Register(base | PE_CTRL_REGISTER, MMIO::DirectRead<u16>(&m_Control.Hex),
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mmio->Register(base | PE_CTRL_REGISTER, MMIO::DirectRead<u16>(&m_Control.hex),
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MMIO::ComplexWrite<u16>([](u32, u16 val) {
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UPECtrlReg tmpCtrl(val);
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UPECtrlReg tmpCtrl{.hex = val};
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if (tmpCtrl.PEToken)
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if (tmpCtrl.pe_token)
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s_signal_token_interrupt = false;
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if (tmpCtrl.PEFinish)
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if (tmpCtrl.pe_finish)
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s_signal_finish_interrupt = false;
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m_Control.PETokenEnable = tmpCtrl.PETokenEnable;
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m_Control.PEFinishEnable = tmpCtrl.PEFinishEnable;
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m_Control.PEToken = 0; // this flag is write only
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m_Control.PEFinish = 0; // this flag is write only
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m_Control.pe_token_enable = tmpCtrl.pe_token_enable.Value();
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m_Control.pe_finish_enable = tmpCtrl.pe_finish_enable.Value();
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m_Control.pe_token = false; // this flag is write only
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m_Control.pe_finish = false; // this flag is write only
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DEBUG_LOG_FMT(PIXELENGINE, "(w16) CTRL_REGISTER: {:#06x}", val);
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UpdateInterrupts();
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@ -244,11 +290,11 @@ static void UpdateInterrupts()
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{
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// check if there is a token-interrupt
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ProcessorInterface::SetInterrupt(INT_CAUSE_PE_TOKEN,
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s_signal_token_interrupt && m_Control.PETokenEnable);
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s_signal_token_interrupt && m_Control.pe_token_enable);
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// check if there is a finish-interrupt
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ProcessorInterface::SetInterrupt(INT_CAUSE_PE_FINISH,
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s_signal_finish_interrupt && m_Control.PEFinishEnable);
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s_signal_finish_interrupt && m_Control.pe_finish_enable);
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}
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static void SetTokenFinish_OnMainThread(u64 userdata, s64 cyclesLate)
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@ -325,9 +371,9 @@ void SetFinish(int cycles_into_future)
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RaiseEvent(cycles_into_future);
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}
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UPEAlphaReadReg GetAlphaReadMode()
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AlphaReadMode GetAlphaReadMode()
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{
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return m_AlphaRead;
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return m_AlphaRead.read_mode;
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}
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} // namespace PixelEngine
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